CN103885362A - Multi-DSP parallel processing board based on CPCI-E bus - Google Patents
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Abstract
The invention relates to the design architecture of a multi-DSP parallel processing board based on a CPCI-E bus. The multi-DSP parallel processing board comprises four TS201 floating point DSPs and an XC7K325TFPGA, wherein each DSP is connected with the other three DSPs through full duplex LINK ports, and the four DSPs are connected with a FPGA through data buses and full duplex LINK ports. The PFGA is connected with a CPCI-Express bridge through a self-defined high-speed interface. According to the multi-DSP parallel processing board, electrified free switching is achieved for the LINK port loading mode of a TS201 array and the passive and active loading modes of the FPGA through the CPCI-E bus, high-speed data transmission of a DSP processing array is achieved through the serial difference characteristics of the CPCI-E bus and the external cache of the FPGA, and the multi-DSP parallel processing board has the advantages of being high in bus transmission speed, small in size, flexible in interface method, large in onboard cache and high in expansibility.
Description
Technical field
The present invention relates to high-speed digital signal Communication processing field, particularly a kind of many DSP co-processing board based on CPCI-E bus.
Background technology
Most disposable plates are all taking traditional cpci bus interface as main on the market now.CPCI belongs to traditional parallel interface bus, does not meet the theory category of serial transmission in modern communication.Not only volume is large for it, signal definition complexity, and also transmission speed only has ten parts of CPCI-E bus.Obviously no matter how the powerful disposable plates this interface of arranging in pairs or groups all can run into the tight bottle of transmission, cannot the inherent advantages of performance own.And the disposable plates also DDR3, gigabit networking, Rapid IO, TigerSharc201, CPCI-E, these high-end modules of Xilinx 7 Series FPGA not being integrated in one on the market at present.Also be certain part of functions realizing above at most, and do not make standardized product, let alone extendible high-speed interface.What industry was main is all taking CPCI as main transmission interface, so there is significant limitation on allomeric function.
Present main flow Digital Design all be unable to do without the application of dsp chip substantially.At the beginning of 2000, along with the technical development such as radar, wireless telecommunications, the mutual transmission mutually of large bandwidth high resolution, multi-signal processing mode and Large Volume Data, makes the requirement of signal real time signal processing and transmission greatly improve.Along with the development of large scale integrated circuit technology, obtain developing fast and applying as the core digital signal processor (DSP) of digital signal processing.Industry was taking the DSP of TI and ADI company as main in occupation of most market at that time, and there are fixed point and floating-point model in two companies, each has something to recommend him in application.ADI company released brand-new generation float-point DSP processor TigerSharc201(TS201 in 2003), as shown in Figure 1, its release is keeping the absolute long-term advantage in Floating-point DSP field when seasonal ADI company to its structure.TS201 cost performance is very high, has the height programmability of FPGA and ASIC signal handling property and instruction set processor concurrently, is applicable to large buffer memory, high-performance, high-speed signal is processed and image processing.As Radar Signal Processing, wireless base station, graphics/audio processing etc.Table 1 is the contrast that ADI company and TI company are used commonplace typical Floating-point DSP performance.
Table
The leading indicator of TS201 is all higher than TMS320C6713B as can be seen from Table 1, and this also meets ADI company and designed originally the original intention of this chip.Especially the buffer memory of inner 3MB and 4 high speed Link mouths are different from traditional DSP design concept, the sensation of finding everything fresh and new to designer completely.And make everybody endure to the fullest extent puzzled " realize simultaneously data high-speed input and output " problem solved.Even if DSP in the past has the synchronous transmission bus of EDMA mode also can only at a time receive or send, make so the large heavy discount of bus transfer bandwidth (at least dwindling a times).Some DSP has just increased some accessory channels in order to solve this problem, such as McBSP, HPI etc.But these interface rates are all very low, the highest also with regard to the speed grade of tens MB.This obviously can not meet the demand of modern signal processing.The transmission broadband of every pair of Link mouth of TS201 is 4, can be operated in full-duplex mode, and total speed reaches 1GB/S.
But TS201 is not applied in the disposable plates based on CPCI-E bus at present, main cause is that TS201 and CPCI-E belong to technical merit is had relatively high expectations, if they are soft together just more difficult, what need to consider is more, is the problem that belongs to 1+1>2.
Summary of the invention
The present invention is for solving the problems of the technologies described above, a kind of many DSP co-processing board based on CPCI-E bus is provided, DDR3, gigabit networking, Rapid IO, TigerSharc201, CPCI-E, these high-end modules of Xilinx 7 Series FPGA can be integrated in one, and volume is little, signal definition is simple, and transmission speed is higher.
Technical scheme of the present invention is as follows:
Many DSP co-processing board based on CPCI-E bus, it is characterized in that: comprise that four TigerSharc201(are TS201) the FPGA(field programmable logic array (FPLA) of the XC7K325T of float-point DSP processor and Xilinx 7 series), each TigerSharc201 float-point DSP processor is all connected by LINK mouth with its excess-three TigerSharc201 float-point DSP processor, and four TigerSharc201 float-point DSP processor are all connected with the FPGA of XC7K325T by full duplex LINK mouth, data bus; Described XC7K325T FPGA connects by self-defined high-speed interface and CPCI-Express bridging; Described CPCI-Express bridge is connected to network processing unit NP by parallel-expansion mouth, and the FPGA of XC7K325T connects four TigerSharc201 float-point DSP processor by external bus, and the FPGA of XC7K325T connects connector by CPCI-E bus.
Described CPCI-E bus is according to × 8 transmission width design, in order to ensure the high-speed transfer (2.5Gbps/ bundle) of signal.
Described connector is differential connector, this differential connector be fully differential to structure, taking each Difference signal pair as one group, the shielding sheet that differential pair outside comprises a ground connection, can effectively reduce crosstalking between signal like this; This connector adopts the differential connector of German ERNI company.
Described CPCI-Express bridge meets V1.1 specification (CPCI.Express.Base.Specification.v1.1), calculates according to the transfer rate of every bundle 2.5Gbps, and × 8 one-way transmission speed can reach 2GB/S altogether.
Described XC7K325T FPGA is circumscribed with large capacity DDR3(third generation double data rate Synchronous Dynamic Random Access Memory) buffer memory.
Between plate and plate, undertaken transmitting between plate by the Rapid IO of XC7K325T FPGA.
Adopt CPCI-E bus to realize LINK mouth load mode to four TS201 and to the passive of FPGA with initiatively from freely switching of mode also.
CPCI-E bus realizes the LINK mouth of TS201 is loaded:
The LINK mouth of TS201 loads need to have peripheral control unit initiatively load clock and load data-signal to its input, and oneself belongs to passive reception.The clock of input and data-signal need to be converted into LVDS level (low-voltage differential signal) and split loading according to the highway width of 4bit.In the process loading, LINK mouth can regularly be carried out the code that previous moment is transfused to, so need the load time of every 128 bits to retain certain interval.The asynchronous bus that CPCI-E bus is held by own Local produces corresponding decoded signal and sequential, and asynchronous bus comprises sheet choosing (CS), read signal (RD), write signal (WR), address wire (Addr) and data line (Data).The loading of DSP belongs to asynchronous slow procedure, and main frame can utilize CPCI-E interface to produce arbitrarily sequential combination any a slice DSP is resetted and loaded, and does not need switch electricity just can realize flexible control and arbitrary code switching.And because loading code can be placed in any one storage medium of any position, therefore can increase the confidentiality of code itself.
To FPGA from string and from and freely the switching of mode, while utilizing FPGA startup with the judgement of carrying out self loading mode of special initialization and mode decision signal.
Beneficial effect of the present invention is as follows:
The present invention is the many DSP parallel processing general digital plate of a new generation based on high speed serialization differential bus (CPCI-E) transmission; General, at a high speed and total digitalization process and run through among its whole design concept, it rolls into one multiple industry transfer bus (interface) up-to-date, most significant end, specific as follows:
1, bus transfer speed is fast, and volume is little; Adopting serial differential cabling mode on every a branch of difference cabling, to realize very high baud rate transmission, adopt 8 bundle differential bus synchronous transmission simultaneously, is that its total transfer rate reaches 2GB/S; In physical form, adopt external high-density connector in less physical space, to realize reliable and stable connection;
2, the DSP of 4 × TS201 shares array mode realization data processing and transmission efficiently, at a high speed; Utilize the exclusive bus sharing mode group battle array of TS201, the external bus of 4 TS201 is directly shorted together, outside cabling number had both been saved in this design, had reduced and the line of FPGA pin, and the DMA that can utilize again the short circuit of bus to realize internal memory exchanges visits; This bus mode combines and realizes several data transmission channel with the connected mode of LINK interface, and the input and output of data are just seamless coherent, greatly brings into play the arithmetic capability of this DSP group battle array sequence;
3: use the XC7K325T FPGA of Xilinx 7 series and the assembled scheme of DDR3 controller; K7 belongs to the FPGA series of XILINX most significant end at present, is the FPGA product that industry first item uses 28nm technique; In the design, independently DDR3 controller of two groups of its exterior arrangement, makes single group access speed reach 10GB/S, can realize the high-speed cache of Large Volume Data;
4, user can utilize Rapid IO to realize between plate to transmit, make the present invention become general high-end full digital processing platform.
Brief description of the drawings
Fig. 1 is the block diagram of TS021;
Fig. 2 is composition array architecture block diagram of the present invention;
Fig. 3 is that the present invention adopts code translator to realize the block diagram loading
Fig. 4 is the concrete Loading Control signal schematic representation that the present invention adopts the Local bus of CPCI-E to coordinate 3-8 code translator to carry out decoded operation
Fig. 5 is the schematic diagram of level conversion design of the present invention
Fig. 6 is the loading sequential chart of DSP link mouth of the present invention
Fig. 7 is the exemplary steps schematic diagram that the present invention loads FPGA
Fig. 8 is the sequential of the present invention's each pin signal while loading FPGA initialization.
Embodiment
As shown in Figure 2, many DSP co-processing board (model BN904) based on CPCI-E bus, four TigerSharc201(that comprise ADI company are TS201) FPGA of the XC7K325T of float-point DSP processor and Xilinx 7 series, each TigerSharc201 float-point DSP processor is all connected by LINK mouth (being " LK " in Fig. 2) with its excess-three TigerSharc201 float-point DSP processor, each TigerSharc201 float-point DSP processor is all connected by LINK mouth with its excess-three TigerSharc201 float-point DSP processor, four TigerSharc201 float-point DSP processor are all connected with the FPGA of XC7K325T with full duplex LINK mouth by data bus, the FPGA of described XC7K325T connects by self-defined high-speed interface and CPCI-Express bridging, CPCI-Express bridge is connected to NP(network processing unit by parallel-expansion mouth), the FPGA of XC7K325T also connects four TigerSharc201 float-point DSP processor by external bus, and the FPGA of XC7K325T connects connector by CPCI-E bus, network processing unit NP connects MAC again, and MAC connects PHY, and PHY connects RJ45.
The FPGA of described XC7K325T also connects four TigerSharc201 float-point DSP processor by external bus, is also connected with the SDRAM of 1GB and the FLASH of 512MB by external bus.
Described CPCI-E bus is according to × 8 transmission width design, in order to ensure the high-speed transfer (2.5Gbps/ bundle) of signal.
Described connector is differential connector, this differential connector be fully differential to structure, taking each Difference signal pair as one group, the shielding sheet that differential pair outside comprises a ground connection, can effectively reduce crosstalking between signal like this; This connector adopts the differential connector of German ERNI company.
Described CPCI-Express bridge meets V1.1 specification, calculates according to the transfer rate of every bundle 2.5Gbps, and × 8 one-way transmission speed can reach 2GB/S altogether.
The FPGA of described XC7K325T has been circumscribed with double data rate Synchronous Dynamic Random Access Memory, and capacity can reach 2GB, and single group DDR3 access rate reaches 10GB/S, can realize the high-speed cache of Large Volume Data.
User can utilize by Rapid IO and realize between the plate of XC7K325T FPGA and transmitting, and makes disposable plates become general high-end full digital processing platform.
User in use needs to upgrade DSP code and FPGA code often, by FPGA from string (× 1) load ports, be linked into CPCI-E bridging chip from the Link load ports of (× 8) load ports and DSP also, utilize its asynchronous decoding expansion interface code to load the combination in any of switching.
Many DSP co-processing board (model BN904) of CPCI-E bus adopts serial differential cabling mode on every a branch of difference cabling, to realize very high baud rate transmission, adopts 8 bundle differential bus synchronous transmission simultaneously, is that its total transfer rate reaches 2GB/S; In physical form, adopt external high-density connector in less physical space, to realize reliable and stable connection; Utilize the exclusive bus sharing mode group battle array of TS201, the external bus of four TS201 is directly shorted together, outside cabling number had both been saved in this design, had reduced and the line of FPGA pin, and the DMA that can utilize again the short circuit of bus to realize internal memory exchanges visits; This bus mode combines and realizes several data transmission channel with the connected mode of LINK interface, and the input and output of data are just seamless coherent, greatly brings into play the arithmetic capability of this DSP group battle array sequence.
Adopt CPCI-E bus to realize LINK mouth load mode to four TS201 and to the passive of FPGA with initiatively from freely switching of mode also.
CPCI-E bus realizes the LINK mouth of TS201 is loaded:
The LINK mouth of TS201 loads need to have peripheral control unit initiatively load clock and load data-signal to its input, and oneself belongs to passive reception.The clock of input and data-signal need to be converted into LVDS level (low-voltage differential signal) and split loading according to the highway width of 4bit.In the process loading, LINK mouth can regularly be carried out the code that previous moment is transfused to, so need the load time of every 128 bits to retain certain interval.The asynchronous bus that CPCI-E bus is held by own Local produces corresponding decoded signal and sequential, and asynchronous bus comprises sheet choosing (CS), read signal (RD), write signal (WR), address wire (Addr) and data line (Data).The loading of DSP belongs to asynchronous slow procedure, and main frame can utilize CPCI-E interface to produce arbitrarily sequential combination any a slice DSP is resetted and loaded, and does not need switch electricity just can realize flexible control and arbitrary code switching.And because loading code can be placed in any one storage medium of any position, therefore can increase the confidentiality of code itself.
As shown in Figure 3, adopt code translator to carry out the concrete framework loading.As shown in Figure 4, the control signal that uses the Local bus of CPCI-E to coordinate 3-8 code translator to carry out the concrete loading of decoded operation in the design.Before loading, first decoding produces a low impulse level reset dsp chip, and this will revert to original upload state the internal state of DSP.Because it is passive receive mode, so only need to be by low corresponding data line 4 assignment in the LINK of DSP mouth receiving end, simultaneously for LVTTL is changed into LVDS signal by the circuit that accurately need to use that ensures level, the company such as TI, MAXIM has a lot of this level transferring chip to realize, and level conversion design as shown in Figure 5.01 square-wave signal changing by code translator is input to the loading clock LCLK of DSP as clock sequence.It is two along clock signal that LCLK belongs to, all can latch 4 bit data on upper edge and the lower edge of clock.In Fig. 5, Addr is the address signal of Local end, and Data is the data-signal of Local end, and RST_DSPx is the reset signal of delivering to each dsp chip, and DSPx_CLK is the two along clock signal of Link mouth loading, and DSPx_LDATA is the data-signal of Link mouth.Time first produce data-signal clocking again in work, can allow like this central authorities of the edge aligned data that loads clock to guarantee the success of loading procedure.The loading sequential of DSP link mouth, as shown in Figure 6.Compared with the load mode traditional with TS201, the required line of this programme is considerably less, the not storage space outside occupying volume; Sequential is simple easily to be realized, and the impact of the sequencing that do not powered on, can dynamically update and Long-distance Control at any time; 128 unique design that load interval can be avoided the conflict in the loading of DSP code, are applicable to very much using the working environment having higher use restriction.
FPGA occurs as a kind of semi-custom circuit in application-specific integrated circuit ASIC (Application Specific Integrated Circuit) field at first, both solve the deficiency of custom circuit, overcome again the limited shortcoming of original programming device gate circuit number.Present FPGA has produced great leap through more than ten years development, almost can complete the function of any digital device.Upper to high performance CPU, can realize with FPGA down to simple combined control circuit.It designs necessary important devices as the present information epoch, and effect and status in various design of electronic products are more and more important, and a lot of products have left fpga chip and just cannot realize at all.But the configuration code of well-known FPGA is all placed on outside independently in storage medium, every task all must be from external load code to sheet in could move.The loading of FPGA generally has this several modes, and passive serial is passive parallel, initiatively serial, initiatively parallel and JTAG pattern etc.The judgement of these patterns determines (000,001,010 by M0, M1, the level state of these three pins of M2 in the time powering up of chip ...).Different patterns is to peripheral hardware configuration circuit, and storage chip type and applied environment have different requirements, even often can between different mode of operations, freely switch.Particularly active above-mentioned and passive load mode are the start-up mode that two species diversity are very large, such as function and the direction of the signal on same pin in these two kinds of loading modes are completely different.In former product design, FPGA is designed to a kind of Starting mode conventionally, if need the switching (such as security requirements, FPGA code can not be placed on board storer, and this just must use Passive Mode) of several modes.Although can design several different configuring chips and several different start-up circuit, will inevitably cause like this complex circuit designs, the increase of device scale and the space of a whole page effectively utilize the problems such as space dwindles.More seriously the switching between this different start-up mode needs equipment in the situation that of power-off, to use physics jumper switch to switch conventionally, and this is definitely unallowed in many working environments.Therefore in the urgent need to a kind of design circuit can be the not power-off of product in the situation that to initiatively and passive start-up mode carry out free switching, and can not bring additionally too much design cost and the reduction of reliability.
This programme to FPGA from string and from and freely the switching of mode, while utilizing FPGA to start with the judgement of carrying out self loading mode of special initialization and mode decision signal, as shown in Figure 7, an exemplary steps figure that FPGA loads, and the 3rd step realizes the key point of above multi-mode switching function just.First the 1st step is chip bootloader, and the 2nd step is that after electrification reset, to remove internal configurations storage space be that subsequent external configuration code imports to space motion in sheet and prepares.
As shown in Figure 8, the sequential of each pin signal while being FPGA loading initialization.Before FPGA code completes loading, INIT_B belongs to input signal.INIT_B signal during from low uprising (rising edge) its can to M0 M1 three signal levels such as M2 sample, FPGA can according to the sampled value to these three signals now (000 001 010 ...) judge it is the Starting mode for which kind of pattern, and then send or receive corresponding clock signal according to corresponding start-up mode.INIT_B signal is extremely important as can be seen here, its rising edge to M0 1 the value of 2 latches determined its start-up mode.
First the design produces a low pulse signal reset FPGA before change loading mode on PROGRAM_B pin, then the in the situation that of not power-off, use decoder circuit on INIT_B pin, to produce a low pulse, simultaneously according to startup demand, M0 12 pins are now set to required low and high level.When set M0 1 first discharge PROGRAM_B signal for high after 2 level value, and then to discharge INIT_B signal be height.The rising edge of INIT_B can be latched in the level value of three pattern pins in internal register start-up mode is judged, and so just can change its start-up mode, realizes the switching between different loading.Because INIT_B belongs to two-way signaling, FPGA can be become output signal after loading completes.In order to prevent the tri-state conflict on signal wire, thus on INIT_B, increase a BUF controller with realize this signal high resistant switch.CCLK signal direction in different patterns is different, is sometimes that to input be sometimes output, so just need to be connected in series equally a BUF controller for fear of this conflict on its signal wire.
Claims (8)
1. the many DSP co-processing board based on CPCI-E bus, it is characterized in that: the FPGA that comprises the XC7K325T of four TigerSharc201 float-point DSP processor and Xilinx 7 series, each TigerSharc201 float-point DSP processor is all connected by LINK mouth with its excess-three TigerSharc201 float-point DSP processor, and four TigerSharc201 float-point DSP processor are all connected with the FPGA of XC7K325T by full duplex LINK mouth, data bus; The FPGA of described XC7K325T connects by self-defined high-speed interface and CPCI-Express bridging; Described CPCI-Express bridge is connected to network processing unit NP by parallel-expansion mouth, and the FPGA of XC7K325T connects four TigerSharc201 float-point DSP processor by external bus, and the FPGA of XC7K325T connects connector by CPCI-E bus.
2. the many DSP co-processing board based on CPCI-E bus according to claim 1, is characterized in that: described CPCI-E bus is according to × 8 transmission width design.
3. the many DSP co-processing board based on CPCI-E bus according to claim 2, it is characterized in that: described connector is differential connector, this differential connector be fully differential signal to structure, taking each differential signal P/N end to as one group, the shielding sheet that differential pair outside comprises a ground connection.
4. the many DSP co-processing board based on CPCI-E bus according to claim 1, is characterized in that: the one-way transmission speed of described CPCI-Express bridge amounts to 2GB/S.
5. the many DSP co-processing board based on CPCI-E bus according to claim 1, is characterized in that: the FPGA of described XC7K325T is circumscribed with double data rate Synchronous Dynamic Random Access Memory.
6. the many DSP co-processing board based on CPCI-E bus according to claim 1, is characterized in that: the FPGA of described XC7K325T is undertaken transmitting between plate by Rapid IO.
7. the many DSP co-processing board based on CPCI-E bus according to claim 1, it is characterized in that: in use, need dynamically update code, and the Link load ports of the passive load ports of FPGA, initiatively load ports and DSP is linked into CPCI-Express bridge, utilize its asynchronous decoding expansion interface to realize the code of any one chip is loaded.
8. the many DSP co-processing board based on CPCI-E bus according to claim 1, it is characterized in that: adopt CPCI-E bus to realize the LINK mouth of four TigerSharc201 float-point DSP processor loaded, and to the passive of FPGA and initiatively from and freely the switching of mode.
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