CN108304336A - A kind of signal processing apparatus and method - Google Patents
A kind of signal processing apparatus and method Download PDFInfo
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- CN108304336A CN108304336A CN201810103293.4A CN201810103293A CN108304336A CN 108304336 A CN108304336 A CN 108304336A CN 201810103293 A CN201810103293 A CN 201810103293A CN 108304336 A CN108304336 A CN 108304336A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
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Abstract
The embodiment of the invention discloses a kind of signal processing apparatus and methods.The signal processing apparatus includes：Signal processing module, and the control module being connect respectively with the signal processing module and at least one display module；Control module, for being configured to signal processing module according to the type of input signal；Wherein, input signal is single-ended signal, differential signal or MIPI DSI signals；Signal processing module is handled input signal according to the configuration of control module for receiving input signal, and at least one display module output treated MIPI DSI signals.The embodiment of the present invention solves in existing VR equipment, and the problems generated after MIPI DSI agreements are realized since FPGA device is additional, and introduces Bridge IC and increase hardware design difficulty, debugging difficulty and the single problem of performance.
Description
Technical field
This application involves but be not limited to field of computer technology, espespecially a kind of signal processing apparatus and method.
Background technology
It is more and more to rely on liquid crystal with the high speed development of computer service ability being substantially improved with display industry
Show device (Liquid Crystal Display, referred to as：LCD), Organic Light Emitting Diode (Organic Light-Emitting
Diode, referred to as：) etc. OLED the new technology of display devices is emerged in large numbers, for example, virtual reality (VirtualReality, referred to as：
VR) equipment.
Since display device uses special mobile Industry Processor Interface (Mobile Industry Processor
Interface, referred to as：MIPI) series display interface (DisplaySerialInterface, referred to as：DSI) agreement is (i.e.
MIPI DSI agreements), non-MIPI DSI signals, for example (,) single-ended signal, low-voltage differential signal (Low-Voltage
Differential Signaling, referred to as：) etc. LVDS input signals need to be encoded to DSI formats.For these reasons,
Non- MIPI DSI signals can not be directly transmitted in VR equipment, for realizing the new algorithm knowledge of various functions in VR equipment
Property right core (Intellectual Property Core, referred to as：IP kernel) engineering verification must add DSI coding.At present
In VR equipment, most of the exploitation of soft (i.e. soft IP kernels) or hard IP kernel (hard IP kernels) is all based on field programmable logic
Gate array (Field-Programmable Gate Array, referred to as：FPGA) device is verified, however, FPGA device
Display look-up table (Look-Up Tables, referred to as：LUT it is big itself to realize that MIPI DSI agreements need to expend for) limited amount
Logical resource is measured, is robbed outside the efficient resource for accounting for new algorithm IP kernel to be verified, is also introduced unnecessary device inside path and prolong
Late, interference new algorithm assessment, influences the accuracy of verification result.
In view of the above-mentioned problems, additional bridge IC chip (the Bridge Integrated of current stage of development generally use
Circuit, referred to as：Bridge IC) mode carry out signal conversion, but which introducing increases setting for system hardware
Difficulty is counted, debugging is difficult, and conversion is single, and a Bridge IC only corresponds to a kind of non-MIPI DSI interfaces to be converted, does not have
There is versatility, while relevant Bridge IC types are less, limitation is big.
Invention content
In order to solve the above-mentioned technical problem, an embodiment of the present invention provides a kind of signal processing apparatus and methods, to realize
It is a kind of that a plurality of types of signal inputs, the proof of algorithm platform of high speed DSI signals output is supported to solve in existing VR equipment,
The problems generated after MIPI DSI agreements are realized since FPGA device is additional, and are introduced Bridge IC increase hardware and set
Count difficulty, debugging difficulty and the single problem of performance.
The embodiment of the present invention provides a kind of signal processing apparatus, including：Signal processing module, and respectively with the signal
The control module of processing module connection and at least one display module；
The control module, for being configured to the signal processing module according to the type of input signal；Wherein, institute
It is single-ended signal, differential signal or mobile industry processor interface series display interface MIPI DSI signals to state input signal；
The signal processing module, for receiving the input signal, according to the configuration of the control module to described defeated
Enter signal to be handled, and at least one display module output treated the MIPI DSI signals.
Optionally, in signal processing apparatus as described above,
The control module is additionally operable to detect the type of the input signal；
The control module configures the signal processing module, including：
According to the input and output IO voltages of signal processing module described in the type configuration of the input signal detected and
Internal pull-up resistor so that the type matching of the configuration information of the signal processing module and the input signal.
Optionally, in signal processing apparatus as described above, the input terminal IO of the signal processing module is divided into advance
Multiple configuration groups；
The control module configures the signal processing module, including：
Each configuration group in the signal processing module is configured accordingly, the configuration of each configuration group
It is identical.
Optionally, in signal processing apparatus as described above, when the input signal is single-ended signal or differential signal,
The signal processing module handles the input signal, including：
Serioparallel exchange processing and coded treatment are carried out to the input signal, corresponding MIPI DSI are generated after coded treatment
Signal；
When the input signal be MIPI DSI signals when, the signal processing module to the input signal at
Reason, including：
Serioparallel exchange processing is carried out to the MIPI DSI signals, corresponding MIPI DSI letters are generated after serioparallel exchange processing
Number.
Optionally, in signal processing apparatus as described above, the signal processing module includes at least one programmable defeated
Exit port；
The control module, the signal for being additionally operable to control in the signal processing module are defeated from the programmable output port
Go out.
The embodiment of the present invention also provides a kind of signal processing method, including：
Signal processing module is configured according to the type of input signal；Wherein, the input signal be single-ended signal,
Differential signal or mobile industry processor interface series display interface MIPI DSI signals；
After receiving the input signal, the input signal is carried out according to the configuration information of the signal processing module
Processing, and export treated the MIPI DSI signals.
Optionally, in signal processing method as described above, the type according to input signal is to signal processing module
Before being configured, the method further includes：
Detect the type of the input signal；
It is described that signal processing module is configured according to the type of input signal, including：
According to the input and output IO voltages of signal processing module described in the type configuration of the input signal detected and
Internal pull-up resistor so that the type matching of the configuration information of the signal processing module and the input signal.
Optionally, in signal processing method as described above, the input terminal IO of the signal processing module is divided into advance
Multiple configuration groups；It is described that signal processing module is configured according to the type of input signal, including：
Each configuration group in the signal processing module is configured accordingly, the configuration of each configuration group
It is identical.
Optionally, in signal processing method as described above, when the input signal is single-ended signal or differential signal,
It is described that the input signal is handled, including：
Serioparallel exchange processing and coded treatment are carried out to the input signal, corresponding MIPI DSI are generated after coded treatment
Signal；
It is described that the input signal is handled when the input signal is MIPI DSI signals, including：
Serioparallel exchange processing is carried out to the MIPI DSI signals, corresponding MIPI DSI letters are generated after serioparallel exchange processing
Number.
Optionally, in signal processing method as described above, the signal processing module includes at least one programmable defeated
Exit port；The method further includes：
By changing the mapped file in the signal processing module by the signal in the signal processing module from described
Programmable output port output.
Signal processing apparatus provided in an embodiment of the present invention and method, control module are believed according to the type configuration of input signal
Number processing module, signal processing module are handled current input signal according to above-mentioned configuration, and will treated MIPI
DSI signals are exported to be shown to display module, wherein input signal may include different types of signal, such as single-ended letter
Number, differential signal or MIPI DSI signals, output signal is the dedicated MIPI DSI signals of display device.The embodiment of the present invention carries
The signal processing apparatus of confession passes through control module (being, for example, FPGA device) binding signal processing module (being, for example, ASSP devices)
System architecture, signal processing module may be implemented to convert different types of input signal under the configuration of control module
Operation, that is, provide and a kind of the input of a plurality of types of signals, the proof of algorithm platform of MIPI DSI signals output supported to be not necessarily to
It occupies the limited logical resource processing MIPI of verification platform and shows docking problem, also without the hardware cost of increase verification platform.
Description of the drawings
Attached drawing is used for providing further understanding technical solution of the present invention, and a part for constitution instruction, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is a kind of structural schematic diagram of signal processing apparatus provided in an embodiment of the present invention；
Fig. 2 is a kind of illustrative view of functional configuration for ASSP devices that signal processing module is realized in the embodiment of the present invention；
Fig. 3 is a kind of structural representation of the IO configuration groups for ASSP devices that signal processing module is realized in the embodiment of the present invention
Figure；
Fig. 4 is a kind of domain distribution schematic diagram for ASSP devices that signal processing module is realized in the embodiment of the present invention；
Fig. 5 is the structural schematic diagram of another signal processing apparatus provided in an embodiment of the present invention；
Fig. 6 is a kind of flow chart of signal processing method provided in an embodiment of the present invention；
Fig. 7 is the flow chart of another signal processing method provided in an embodiment of the present invention；
Fig. 8 is a kind of flow chart of the configuration method of signal processing apparatus provided in an embodiment of the present invention.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature mutually can arbitrarily combine.
The present invention provides following specific embodiment and can be combined with each other, for same or analogous concept or process
It may be repeated no more in some embodiments.
Fig. 1 is a kind of structural schematic diagram of signal processing apparatus provided in an embodiment of the present invention.The embodiment of the present invention provides
Signal processing apparatus 10, may include：Signal processing module 110, and the control that is connect respectively with the signal processing module 110
Molding block 120 and at least one display module 130.
Wherein, control module 120, for being configured to signal processing module 110 according to the type of input signal；Its
In, which is single-ended signal, differential signal or MIPI DSI signals.
Signal processing module 110, for receiving input signal, according to the configuration of control module 120 to the input signal into
Row processing, and to the output of at least one display module 130 treated high speed DSI signals.
Signal processing apparatus 10 provided in an embodiment of the present invention, such as can be a virtual implementing helmet, the signal processing
The display module 130 of device 10 is the explicit panel of virtual implementing helmet, can be passed through when user wears the virtual implementing helmet
The explicit panel in left and right sees vivid and high authenticity video；Control module 120 for example can be a FPGA device or can compile
Journey logical device (Programmable Logic Device, referred to as：PLD) device, it is real by the programming to the FPGA device
Various functions in existing VR equipment, i.e. control module 120 are used to verify the new algorithm for realizing the various functions in VR equipment, user
The FPGA device or PLD devices of disposable type can be chosen according to actual verification demand；Signal processing module 110 is for example, special
Standardized product (Application Specific Standard Parts, referred to as：ASSP) device, for receiving input letter
Number, the input signal received can be different types of signal, such as believe including single-ended signal (single-ended), difference
Number (LVDS) or MIPI DSI signals, signal processing module 110 act as handling its received signal, export MIPI
DSI signals export the signal type that the display module 130 of VR equipment can identify.
In embodiments of the present invention, since the design object of signal processing apparatus 10 is to support a plurality of types of signals defeated
Enter, signal processing module 110 is realized to different types of input signal, output MIPI DSI signals after being handled, at signal
Different types of input signal is converted to MIPI DSI signals by reason module 110, or carries out the processing that MIPI DSI signals direct transfer
Mode can be controlled by control module 120.In practical applications, since signal processing module 110 is receiving different type
Input signal when, different to the set-up mode of its device inside, processing mode is also different, therefore, by 120 basis of control module
The type of varying input signal configures signal processing module 110, matching input so that signal processing module 110 is matched
The type for meeting current input signal is set, so as to realize the conversion process of signal or direct transfer.
Signal processing module 110 and control module 120 in the embodiment of the present invention may be used as FPGA device or class
The ASSP devices of FPGA therefore can be by realizing corresponding work(to the programming of signal processing module 110 and control module 120
Can, for example, by the programming to signal processing module 110, when realizing that input signal is different type, it can export MIPI
DSI signals are realized the type according to varying input signal, are configured and control signal processing by the programming to control module 120
Module 110 is so that it can realize the conversion of signal or direct transfer.
In addition, after signal processing module 110 carries out a series of processing to input signal, MIPI hard IP are transmitted to, are selected
DSI outputs are selected, the MIPI DSI signals of output, to carry out the signal of DSI codings, which can be sent to driving
Display data is sent to display module 130 by IC (Driver IC) after its decoding；Optionally, built-in in display module 130
There is decoder module, the MIPI DSI signals received can be decoded and be shown.
It should be noted that the signal processing module 110 of the embodiment of the present invention is when exporting MIPI DSI signals, it can be only
The MIPI DSI signals are exported to a display module 130, the MIPI can also be exported to two or more display modules 130
DSI signals, the quantity of display module 130 is related to the requirement to display resolution, can be only when the demand of resolution ratio is higher
When the demand of resolution ratio is relatively low multiple display modules 130 can be arranged, Fig. 1 is to be only arranged in one display module 130 of setting
It is shown for one display module 130.
Existing VR equipment by FPGA device to newly energy algorithm is verified for realizing every work(, and realizes VR equipment
Various functions, its reception input signal be non-MIPI DSI signals when, need input signal being encoded to DSI formats,
However, execution new algorithm verification is additional to realize that logical resource is short, introduction means inner track postpones, dry after MIPI DSI agreements
It disturbs the assessment of new algorithm and influences the accuracy of verification result；In addition, though the mode pair of additional Bridge IC may be used
Input signal is converted, but is the increase in hardware design difficulty, the debugging difficulty of VR equipment, and the performance of Bridge IC
It is single, a plurality of types of input signals can not be converted.Signal processing apparatus 10 provided in an embodiment of the present invention passes through control
The system architecture of molding block 120 (be, for example, FPGA device) binding signal processing module 110 (being, for example, ASSP devices), at signal
The operation converted to different types of input signal may be implemented in reason module 110 under the configuration of control module 120, that is, carries
A kind of a plurality of types of signals inputs of support, the proof of algorithm platform of MIPI DSI signals output have been supplied to be verified without occupancy flat
The limited logical resource processing MIPI of platform shows docking problem, also without the hardware cost of increase verification platform, such as introduces
Bridge IC, it is many due to being generated after the additional realization MIPI DSI agreements of FPGA device to solve in existing VR equipment
Problem, and introduce Bridge IC and increase hardware design difficulty, debugging difficulty and the single problem of performance.
Signal processing apparatus provided in an embodiment of the present invention, control module is according to the type configuration signal processing of input signal
Module, signal processing module are handled current input signal according to above-mentioned configuration, and will treated MIPI DSI signals
It exports and is shown to display module, wherein input signal may include different types of signal, such as single-ended signal, difference
Signal or MIPI DSI signals, output signal are the dedicated MIPI DSI signals of display device.Letter provided in an embodiment of the present invention
Number processing unit passes through the system of control module (being, for example, FPGA device) binding signal processing module (being, for example, ASSP devices)
The behaviour converted to different types of input signal may be implemented in framework, signal processing module under the configuration of control module
Make, that is, provides a kind of a plurality of types of signals inputs of support, the proof of algorithm platform of MIPI DSI signals output, without occupying
The limited logical resource processing MIPI of verification platform shows docking problem, also without the hardware cost of increase verification platform.
In an implementation of the embodiment of the present invention, control module 120 can know input letter to be entered in advance
Number type, and signal processing module 110 is configured according to the type, for example, by the artificial configuration of user, selection
The type of input signal.
In another realization method of the embodiment of the present invention, control module 120 is additionally operable to the class of detection input signal
Type；In addition, the realization method that control module 120 configures signal processing module 110, may include：According to what is detected
The type configuration signal processing module 110 of input signal input and output (In Output, referred to as：IO) on voltage and inside
Pull-up resistor so that the configuration information of the signal processing module 110 and the type matching of input signal.
In the realization method, control module 120 can voluntarily be detected the type of input signal, to realization pair
The configuration of signal processing module 110 operates, and signal processing module 110 itself has specific hardware configuration, and part configuration can
To be adapted to the processing to varying input signal, IO voltages for example including signal processing module 110 of the project of configuration and
Internal pull-up resistor.
Optionally, in embodiments of the present invention, the input terminal IO of signal processing module 110 is divided into multiple configurations in advance
Group；In addition, the realization method that control module 120 configures signal processing module 110, may include：To signal processing mould
Each configuration group is configured accordingly in block 110, and the configuration of each configuration group is identical.
The realization method of signal processing module in the embodiment of the present invention 110 is said below by way of a specific example
It is bright, the signal processing module 110 can for example select an integrated circuit (Integrated Circuit, referred to as：IC) chip,
The IC chip of selection can be typical Application Specific Standard Product (Application Specific Standard Parts, abbreviation
For：ASSP) device, for example, in the ASSP devices, input and output that user can configure (Input Output, referred to as：IO) number
Amount is for 15 to (Pairs), and maximum rate is the every channel 1.2Gb/s (per Lane), while the 4-Lane of built-in two standards
MIPI D-PHY (definition of MIPI agreements on a physical layer) stone realizes the high speed data transfer of 6Gb/s.As shown in Fig. 2, being
The illustrative view of functional configuration that a kind of ASSP devices of signal processing module are realized in the embodiment of the present invention, the IO in left side shown in Fig. 2
For Rx signals, i.e. input terminal, right side IO is Tx signals, i.e. output end, which can be used for carrying out turning for signal type
It changes, direct transferring for MIPI DSI-MIPI DSI signals, buffering signals can also be carried out.
As shown in Fig. 2, briefly introducing the basic performance of the ASSP devices for realizing signal processing module, the ASSP devices
Characteristic with FPGA device, all pins are two directions' inputing output, since the pin Rx of Fig. 2 left parts supports D-PHY,
Wherein, in MIPI agreements, D-PHY is provided to series display interface (DSI) and serial utilizing camera interface (Camera
Serial Interface, referred to as：CSI) definition on a physical layer, so the embodiment of the present invention is by the pin of left part
As input, input signal is received, is explained so that input signal is MIPI DSI signals as an example, 15Pairs pins correspond to 3
The ports MIPI (3-Ports), when each MIPI DSI signals include 4 pairs of data channel (corresponding 4Pairs IO) and 1 pair of control
Clock, therefore, 12Pairs pins are for inputting high-speed data signal, and 3Pairs pins signal in order to control, MIPI DSI signals are most
Big input rate is：Vin-max=1.2Gb/s per Lane；The pin of right part is Tx, and 2-Ports is exported, therefore MIPI
DSI signals output the maximum output rate be：Vout-max=1.5Gb/s per Lane.Therefore, which can be same
When input 3 road MIPI DSI signals.It should be noted that the supported every configuration of ASSP devices is shown in Fig. 2, for example,
The programmable I/O in left side can be used as input port (Rx) and output port (Tx), when as Rx, the input signal format of support
Including D-PHY, SubLVDS, LVDS, SLVS200 and CMOS, when as Tx, the output signal format of support include LVDS and
CMOS, black matrix character segment are used as the configuration selected when the signal processing module 110 in the embodiment of the present invention, example for the ASSP devices
If programmable I/O is as Rx, current input signal format is D-PHY, and transmission rate is=1.2Gb/s per Lane, above
Programmable I/O uses the form of 7Pairs IO, following programmable I/O to use the form of 8Pairs IO；The MIPI D- on right side
PHY is as output (Tx), output speed 6Gb/s.
The input terminal IO of the type of characteristic and input signal based on ASSP devices shown in Fig. 2, the ASSP devices is advance
Multiple configuration groups are divided into, each configuration group is a Bank, when input signal is MIPI DSI signals, is divided into 3
Bank, i.e. Bank0, Bank1 and Bank2.The system I/O standard of ASSP devices support, including single-ended IO marks are introduced briefly below
Accurate and difference I/O standard, respectively shown in following Tables 1 and 2：
1 single-ended I/O standard of table
2 difference I/O standard of table
| Standard | VCCIO | Input | Output | It is two-way |
| LVDS | …… | Yes | Yes | No |
| SubLVDS | …… | Yes | No | No |
| MIPI(D-PHY) | …… | Yes (HS-Rx, LP-Rx) | No | Yes(LP) |
| SLVS | …… | Yes | No | No |
| LVCMOS25D | 2.5 | Yes | Yes | Yes |
| LVCMOS33D | 3.3 | Yes | Yes | No |
| LVTTL33D | 3.3 | Yes | Yes | No |
When signal processing module 110 is using ASSP devices shown in Fig. 2, and input signal is MIPI DSI signals, institute
There is Bank to support programmable weak pull-up, Open Drain i.e. high-impedance state is programmed for when Bank is as output.It is single-ended and
Difference LVDS supports tri-state driver (tri-stated Driver).The system I/O buffer of Bank1 and Bank2 can be configured to
Any I/O standard in single-ended (16IOs) or difference (8LVDS IO Pairs), above-mentioned differential part support True-LVDS defeated
Go out, Differential Input comparator, differential termination resistance, on piece dynamic difference input terminal.And Bank0 only supports single-ended format, piece
Upper programmable twin wire universal serial bus (Inter-Integrated Circuit, referred to as：I2C) pull-up resistor is：3.3 kilo-ohm
Nurse (k Ω), 6.8k Ω, 10k Ω.Above-mentioned Tables 1 and 2 list respectively ASSP devices shown in Fig. 2 support single-ended I/O standard and
Difference I/O standard needs to illustrate LVCMOS33, LVTTL33, LVCMOS25 and LVCMOS18 have input hysteresis phenomenon.
Hardware feature and MIPI DSI based on above-mentioned ASSP devices are as input signal, the input terminal of ASSP devices
IO is divided for three configuration groups, i.e., above-mentioned Bank0~2 in advance, as shown in figure 3, to realize signal in the embodiment of the present invention
The structural schematic diagram of the IO configuration groups of a kind of ASSP devices of processing module, refering to what is shown in Fig. 2, being defeated on the left of Fig. 2 and Fig. 3
Outlet, two standard MIPI D-PHY (i.e. MIPI D-PHY 0 and MIPI D-PHY 1) built in the ASSP devices are for exporting
The 15Pairs IO of MIPI DSI signals, right side are divided in 3 groups of Bank, and the IO in each Bank passes through VCCIO(IO is powered up
Pin) it powers on, VCCIOThere are tetra- kinds of configurations of 1.2V, 1.8V, 2.5V and 3.3V, each Bank can be independently-powered, and can be used
Above-mentioned four kinds of configurations, Bank0~2 correspond to VCCIO0~1, drive Single-end output and LVTTL, LVCMOS etc. proportional defeated without reference
Enter buffering, i.e. input signal and the proportional relationship of output signal, performance is stablized.Wherein, single-ended LVTTL, LVCMOS33,
LVCMOS25 and LVCMOS12 has fixed threshold value, it is allowed to be positioned in arbitrary Bank.It is applied to the V of some BankCCIOElectricity
Pressure determines which proportional input standard this Bank supports, simultaneously can be used for difference output driving power supply.In addition, VCCIO0
Power supply system configures (sysCONFIG) signal, works as VCCIOWhen=2.5V, VCCIO0V must be connectedCCAUX25VPP(VCCAUX25VPPFor difference
Tap is received and the power supply of 100 Ω terminals of ASSP device insides IO).Following table 3 lists the IO marks of the supports of above-mentioned Bank0~2 in detail
It is accurate.
The I/O standard that 3 each Bank of table is supported
Illustrate the domain of above-mentioned ASSP devices briefly below, as shown in figure 4, to realize signal processing in the embodiment of the present invention
A kind of domain distribution schematic diagram of ASSP devices of module, the ASSP devices include that 5936 4 inputs show look-up table LUT4
(four input Look Up Tables), corresponding 10 editable functional unit (Programmable Functional
Units, referred to as：PFU) (square in Fig. 4 in PFU schematically indicates multiple LUT4, but not the number of LUT4 is in figure
The quantity of square), to realize logic (logic), operation (arithmetic), random access memory (Random-Access
Memory, referred to as：RAM) and read-only memory (Read-Only Memory, referred to as：The functions such as ROM).Intert between PFU
The embedded RAM of Installed System Memory (sys MEMTMEmbedded Block RAM, referred to as：EBR) row, surrounding are distributed editable
(Programmable) (Bank0, Bank1 and Bank2 in such as Fig. 4, Bank0~2 in corresponding diagram 3) IO Banks, it is embedded
Formulas I 2C (i.e. Embedded I2C) (I2C0 in such as Fig. 4 and I2C1) and the Embedded MIPI D-PHY (MIPI in such as Fig. 4
D-PHY 0 and MIPI D-PHY 1, MIPI D-PHY0 and the MIPI D-PHY 1 in corresponding diagram 2 and Fig. 3), clear area in Fig. 4
Domain is other function modules in ASSP devices, is not introduced one by one herein.The domain of ASSP devices shown in Fig. 4 is to signal processor
110 for ASSP devices shown in Fig. 2 when, the division of Bank, and the I/O standard that each Bank can be supported provide hardware supported.
In above-mentioned example, the dividing mode of Bank0~2 is directed to the case where input signal is MIPI DSI signals, and unexpectedly
Taste, and Bank0~2 and 3 road MIPI DSI signals correspond, and above-mentioned have been described above in each MIPI DSI signals has
4Pairs data-signals and 1Pair control signal, for a MIPI DSI signal, the pin of 4Pairs data-signals
It can be introduced from Bank1 and 2, the pin of 1Pair control signals can be drawn from Bank0.
It should be noted that above-mentioned example is ASSP devices shown in Fig. 2 with signal processing module 110, and input signal is
For MIPI DSI signals, illustrate that input terminal IO in signal processing module 110 is divided into the mode of multiple configuration groups；Signal processing
Input terminal IO is divided into the hardware configuration of the concrete mode and signal processing module 110 of configuration group, and input in module 110
The type of signal is related, and the embodiment of the present invention is not specifically limited.
Optionally, in embodiments of the present invention, when input signal is single-ended signal or differential signal, signal processing module
The realization method that 110 pairs of input signals are handled may include：Input signal is carried out at serioparallel exchange processing and coding
It manages, corresponding MIPI DSI signals is generated after coded treatment.That is, the display module 130 due to VR equipment is only capable of identifying
Therefore MIPI DSI signals when signal processing module 110 handles non-MIPI DSI signals, can go here and there it
And conversion process and coding can carry decoding function to generate corresponding MIPI DSI signals in display module 130, decoding
And show the MIPI DSI signals received.
Optionally, in embodiments of the present invention, when input signal is MIPI DSI signals, signal processing module 110 is right
The realization method that input signal is handled may include：Serioparallel exchange processing, serioparallel exchange are carried out to the MIPI DSI signals
Corresponding MIPI DSI signals are generated after processing.In practical applications, signal processing module 110 receives the MIPI DSI of input
Signal can will be converted to multichannel (such as 8 tunnels) speed parallel signals by high speed serialization MIPI DSI signals all the way, then to its into
Row improves the processing such as path delay, then multi-path parallel signal is converted to high speed serialization MIPI DSI signals output all the way.
Optionally, in signal processing apparatus 10 provided in an embodiment of the present invention, signal processing mould 110 may include at least one
A programmable (Programmable) IO is as output port；Correspondingly, control module 120 are additionally operable to control signal processing mould
Signal in block 110 may be programmed output port output from this.In embodiments of the present invention, equally it is with signal processing module 110
It is shown for one ASSP devices, is used as output by reserving 1~2 Programmable IO on ASSP devices, it should
Programmable IO can be the idle IO of ASSP device insides, can also be multiplexed ASSP device insides for realizing other
The IO of function, such as start IO, software configuration can be carried out to the either signal in ASSP devices, by configuring mapping
(mapping) either signal of ASSP device insides is output to the Programmable IO, and is captured and is seen by oscillograph
It examines, convenient for the different fortune constrained in actual design product such as versus speed (speed), region (area), sequential (timing)
Row effect, while Improving Working Timing can contrast simulation result fast hardware orientation problem, greatly improve debugging efficiency.Separately
Outside, reserved Programmable IO can be also used for subsequent expansion and the upgrading of signal processing apparatus 10.
Further, as shown in figure 5, being the structural representation of another signal processing apparatus provided in an embodiment of the present invention
Scheme, on the architecture basics of device shown in Fig. 1, the control module 120 in the embodiment of the present invention is configurable to and user interface
(User Interface, referred to as：UI) 20 are connected；The control module 120 is additionally operable to the operation to UI 20 according to user,
Execute the control to signal processing module 110.
UI 20 in the embodiment of the present invention can be a personal computer (Personal Computer, referred to as：PC),
For running the upper layer software (applications) write under the programming development environments such as Labview, C-shop, calling 110 debugging software of control module
Associated with realizes a key operations of the UI 20 to entire signal processing apparatus 10 such as Xilinx ISE/Vivado.tcl files,
Keep signal processing apparatus 10 easily operated and debugs.
The signal input of different system may be implemented in signal processing apparatus 10 provided in an embodiment of the present invention, different realizing
It, can be by debugging acid in control module 120 (such as a FPGA device) and message processing module 110 when system function switches
Script file such as Xilinx ISE/Vivado.tcl files are write in (such as an ASSP devices)), rank is arranged with executing
(LevelSetting), IP Instant are synthesized (Synthesize), compiling and drawing (Translate＆Map), position and road
Diameter (Place＆Route) executes (Implement), downloads the control of operations such as (Download), it is direct that PC runs upper layer software (applications)
Call the script file that can be sequentially completed aforesaid operations automatically, be easy to system operatio debugging, power consumption and Time-Series analysis, safeguard and
Upgrading.
Based on the signal processing apparatus 10 that the various embodiments described above of the present invention provide, the embodiment of the present invention also provides a kind of signal
Processing method, the signal processing method are the method that the signal processing apparatus 10 that above-described embodiment provides through the invention executes.
As shown in fig. 6, being a kind of flow chart of signal processing method provided in an embodiment of the present invention.The embodiment of the present invention carries
The signal processing method of confession may include steps of, i.e. S110~S120：
S110 configures signal processing module according to the type of input signal；Wherein, which is single-ended letter
Number, differential signal or MIPI DSI signals；
S120 after receiving input signal, is handled the input signal according to the configuration information of signal processing module,
And export treated MIPI DSI signals.
Signal processing method provided in an embodiment of the present invention can be held by the signal processing apparatus that above-described embodiment provides
Row, for example, a virtual implementing helmet have been described in hardware configuration above-described embodiment of virtual implementing helmet, herein not
It repeats again.The virtual implementing helmet can receive input signal, and the input signal received can be different types of signal, example
Such as include single-ended signal (single-ended), differential signal (LVDS) or MIPI DSI signals, the effect of signal processing module
To handle its received signal, MIPI DSI signals are exported, that is, export the signal that the display of VR equipment can identify
Type.
In embodiments of the present invention, since design object is to support a plurality of types of signal inputs, wherein signal processing mould
Block may be implemented to different types of input signal, export MIPI DSI signals after being handled, i.e. signal processing module can be with
Different types of input signal is converted into MIPI DSI signals, or carries out direct transferring for MIPI DSI signals, above-mentioned processing
It is controlled by the controller (such as a FPGA device) inside VR equipment.In practical applications, since signal processing module exists
Different to the set-up mode of its device inside when receiving different types of input signal, processing mode is also different, therefore, at it
Before receiving input signal, the signal processing module can be configured according to the type of varying input signal, matching input makes
The configuration for obtaining signal processing module meets the type of current input signal, so as to realize the conversion process of signal or direct transfer.
The controller inside signal processing module and VR equipment in the embodiment of the present invention may be used as FPGA device
Or the ASSP devices of class FPGA therefore can be by realizing corresponding function, example to the programming of signal processing module and controller
Such as, MIPI DSI signals can be exported when realizing that input signal is different type by the programming to signal processing module,
By the programming to controller, realize the type according to varying input signal, configure and control signal processing module so that it can
It realizes the conversion of signal or direct transfers.
In addition, after signal processing module carries out a series of processing to input signal, MIPI hard IP are transmitted to, are selected
DSI is exported, the MIPI DSI signals of output, and to carry out the signal of DSI codings, which can be sent to driving IC
Display data is sent to display by (Driver IC) after its decoding；Optionally, it is built-in with decoder module in display, it can
The MIPI DSI signals received are decoded and be shown.
It should be noted that the signal processing module of the embodiment of the present invention is when exporting MIPI DSI signals, can only to
One display exports the MIPI DSI signals, and the MIPI DSI signals can also be exported to two or more displays, shows
Show that the quantity of device is related to the requirement to display resolution, when the demand of resolution ratio is higher, a display can be only set,
When the demand of resolution ratio is relatively low, multiple displays can be set.
Existing VR equipment by FPGA device to newly energy algorithm is verified for realizing every work(, and realizes VR equipment
Various functions, its reception input signal be non-MIPI DSI signals when, need input signal being encoded to DSI formats,
However, execution new algorithm verification is additional to realize that logical resource is short, introduction means inner track postpones, dry after MIPI DSI agreements
It disturbs the assessment of new algorithm and influences the accuracy of verification result；In addition, though the mode pair of additional Bridge IC may be used
Input signal is converted, but is the increase in hardware design difficulty, the debugging difficulty of VR equipment, and the performance of Bridge IC
It is single, a plurality of types of input signals can not be converted.Signal processing method provided in an embodiment of the present invention is set by VR
The processing mode of standby existing controller binding signal processing module (being, for example, ASSP devices), signal processing module is configured
In the case of the operation converted to different types of input signal may be implemented, that is, provide it is a kind of support it is a plurality of types of
Signal inputs, the proof of algorithm platform of MIPI DSI signals output, without occupying the limited logical resource processing of verification platform
MIPI shows docking problem, also without the hardware cost of increase verification platform, such as introduces Bridge IC, existing to solve
In VR equipment, the problems generated after MIPI DSI agreements are realized since FPGA device is additional, and are introduced Bridge IC and increased
Stiffened part design difficulty, debugging difficulty and the single problem of performance.
Signal processing method provided in an embodiment of the present invention, according to the type configuration signal processing module of input signal, letter
Number processing module is handled current input signal according to above-mentioned configuration, and exports that treated MIPI DSI signals are shown
Show, wherein input signal may include different type, such as single-ended signal, differential signal or MIPI DSI signals, output signal
For the dedicated MIPI DSI signals of display device.Signal processing method provided in an embodiment of the present invention passes through having for VR equipment
The processing mode of controller binding signal processing module (being, for example, ASSP devices), signal processing module is in the case of configured
The operation converted to different types of input signal may be implemented, that is, it is defeated to provide a kind of a plurality of types of signals of support
Enter, the proof of algorithm platform of MIPI DSI signals output, is shown without occupying the limited logical resource processing MIPI of verification platform
Docking problem, also without the hardware cost of increase verification platform.
In an implementation of the embodiment of the present invention, VR equipment can know the class of input signal to be entered in advance
Type, and signal processing module is configured according to the type, for example, by the artificial configuration of user, select input signal
Type.
In another realization method of the embodiment of the present invention, as shown in fig. 7, being another kind provided in an embodiment of the present invention
The flow chart of signal processing method, on the basis of flow shown in Fig. 6, method provided in an embodiment of the present invention, before S110
Can also include：
S100 detects the type of input signal；
Correspondingly, in the embodiment of the present invention S110 realization method, may include：According to the class of the input signal detected
Type configures the IO voltages and internal pull-up resistor of signal processing module so that the configuration information of the signal processing module is believed with input
Number type matching.
In the realization method, VR equipment can voluntarily be detected the type of input signal, to realize to signal
The configuration of processing module operates, and there is signal processing module itself specific hardware configuration, part configuration can adjust with suitable
Cope with the processing of varying input signal, project such as the IO voltages and internal pull-up resistor including signal processing module of configuration.
Optionally, in embodiments of the present invention, the input terminal IO of signal processing module is divided into multiple configuration groups, phase in advance
The realization method of Ying Di, S110 may include：
Each configuration group in signal processing module is configured accordingly, the configuration of each configuration group is identical.
The input terminal IO of signal processing module is divided into multiple configuration groups in advance in the embodiment of the present invention, and to each
The realization method that configuration group is configured can refer to the specific example in above-described embodiment, and details are not described herein.In addition, letter
Input terminal IO is divided into the concrete mode of configuration group and the hardware configuration of signal processing module, and input in number processing module
The type of signal is related, and the embodiment of the present invention is not specifically limited.
Optionally, in embodiments of the present invention, when input signal be single-ended signal or differential signal when, to input signal into
Row processing realization method, may include：Serioparallel exchange processing and coded treatment are carried out to input signal, generated after coded treatment
Corresponding MIPI DSI signals.That is, since the display of VR equipment is only capable of identification MIPI DSI signals, believing
When number processing module handles non-MIPI DSI signals, serioparallel exchange processing and coding can be carried out to it, to generate phase
The MIPI DSI signals answered can carry decoding function in the display of VR equipment, decode and show the MIPI DSI received
Signal.
Optionally, in embodiments of the present invention, when input signal is MIPI DSI signals, input signal is handled
Realization method, may include：Serioparallel exchange processing is carried out to MIPI DSI signals, is generated after serioparallel exchange processing corresponding
MIPI DSI signals.In practical applications, signal processing module receives the MIPI DSI signals of input, can will all the way high speed
Serial MIPI DSI signals are converted to multichannel (such as 8 tunnels) speed parallel signals, then carry out improving path delay etc. to it
Reason, then multi-path parallel signal is converted into high speed serialization MIPI DSI signals output all the way.
Optionally, in the present invention is example, at least one programmable I/O can be configured to signal processing module as defeated
Exit port；Correspondingly, method provided in an embodiment of the present invention can also include：By changing the mapping text in signal processing module
Signal in the signal processing module may be programmed output port output by part from this.In embodiments of the present invention, by signal
1~2 Programmable IO is reserved in processing module as output, can to the either signal in signal processing module into
Either signal inside signal processing module is output to this by row software configuration by configuring mapping (mapping)
Programmable IO, and captured and observed by oscillograph, convenient for versus speed (speed), region (area), sequential
(timing) the different operational effects constrained in actual design product such as, while Improving Working Timing can contrast simulation result it is quick
Hardware positioning problem, greatly improves debugging efficiency.In addition, reserved Programmable IO can be also used for VR equipment
Subsequent expansion and upgrading.
Based on the signal processing apparatus 10 that the various embodiments described above of the present invention provide, the embodiment of the present invention also provides a kind of signal
The configuration method of the configuration method of processing unit, the signal processing apparatus is used for by any of the above-described embodiment offer of the present invention
Signal processing apparatus 10 carries out software configuration.
As shown in figure 8, being a kind of flow chart of the configuration method of signal processing apparatus provided in an embodiment of the present invention.This reality
The method for applying example offer is used for the signal processing module in the signal processing apparatus 10 in any embodiment shown in Fig. 1 and Fig. 5
110 and control module 120 carry out software configuration, method provided in an embodiment of the present invention may include steps of：
S201, control module detect input signal, are configured to signal processing module according to the type of input signal.
In the embodiment of the present invention, control module detects input signal, and configures the mode of signal processing module in above-mentioned reality
It applies in example and has been described in, details are not described herein.
S202 generates program, initializes DCS ROM, and configure the external equipment of DSI.The external equipment of the DSI can be
Input equipment and output equipment.
S203, the generated program of exampleization generate the simulation document for verifying the program.
In practical applications, control module and signal processing module select suitable FPGA device or ASSP to this hair embodiment
After device, engineering can be created in device programming software, and program (i.e. DSI IP kernels) is generated in IPexpress tools,
And DCS ROM are initialized, the external equipment of DSI is configured.Then, in program in top document the generated IP of exampleization
Core, changes dsi2dsi_rtl.do files, which is the document form in device programming software, design
Personnel change the simulation document that file generated is directed to above procedure according to demand, and the simulation document is for verifying generated program
Whether design requirement can be met.
It should be noted that the control module and signal processing module in the embodiment of the present invention can be by writing script
File realizes operations, i.e. the journey that the program generated in S202 can execute on module and signal processing module respectively in order to control
Sequence.
S204 emulates program using simulation document；
S205：When verification emulates successfully, the operating procedure of program is executed.
The effect for generating simulation document is in order to which whether proving program meets design requirement, and therefore, it is necessary to using emulation text
Part emulates program, in practical application.When functional simulation verification IP kernel example is melted into work(, illustrate that the program of above-mentioned generation is full
Sufficient design requirement executes entire design, that is, executes the operating procedure of program.
S206 generates the execution file of program.
The configuration method of signal processing apparatus provided in an embodiment of the present invention, at signal based on the embodiment of the present invention
The hardware configuration of device 10 is managed, software configuration can be carried out to control module and signal processing module, to realize IP exampleizations, adjust
With the functions such as the, conversion of input signal and transmission and verification new algorithm.The above-mentioned program that is generated in S202 of having been described above can be with
The program executed respectively on module and signal processing module in order to control, correspondingly, the execution file generated in S206 may be
For the execution file of control module and signal processing module.
In the design scheme of the embodiment of the present invention, the program for executing operation is pre-configured, to signal processing
Before 120 configuration software program of module 110 or control module, the preconfigured program can be executed in device programming software
Operating procedure, such as including：It synthesizes (Synthesize), compiling and drawing (Translate＆Map), position and path
(Place＆Route) etc., the execution file of the program can be generated on the basis of program meets design requirement.
S207 will execute in file download to control module and signal processing module, carry out hardware verification.
In embodiments of the present invention, the execution file of the program, the execution file example are generated after execution program is errorless
Such as be " .bit " file then can download to control mould by " .bit " file by programmer (Programmer)
In block and signal processing module, to carry out hardware verification, i.e. whether access control module and signal processing module may be implemented
Various functions in signal processing apparatus provided in an embodiment of the present invention.
Optionally, the configuration method of signal processing apparatus provided in an embodiment of the present invention can also include before S205：
Time stimulatiom is carried out to program；
According to the path delay in the result verification signal processing apparatus of time stimulatiom, power consumption is assessed.
In embodiments of the present invention, it after executing the operating procedure of program, generates and executes file (" .bit " file)
Before, a post-simulation can also be carried out, this time emulation is specially time stimulatiom, and the purpose of the secondary emulation is primarily to verification
Each path delay inside signal processing apparatus, assessment power consumption etc. after layout wiring.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not limited to the present invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of signal processing apparatus, which is characterized in that including：Signal processing module, and respectively with the signal processing mould
The control module of block connection and at least one display module；
The control module, for being configured to the signal processing module according to the type of input signal；Wherein, described defeated
It is single-ended signal, differential signal or mobile industry processor interface series display interface MIPI DSI signals to enter signal；
The signal processing module believes the input according to the configuration of the control module for receiving the input signal
It number is handled, and at least one display module output treated MIPI DSI signals.
2. signal processing apparatus according to claim 1, which is characterized in that
The control module is additionally operable to detect the type of the input signal；
The control module configures the signal processing module, including：
According to the input and output IO voltages of signal processing module described in the type configuration of the input signal detected and inside
Pull-up resistor so that the type matching of the configuration information of the signal processing module and the input signal.
3. signal processing apparatus according to claim 2, which is characterized in that the input terminal IO of the signal processing module is pre-
First it is divided into multiple configuration groups；
The control module configures the signal processing module, including：
Each configuration group in the signal processing module is configured accordingly, the configuration phase of each configuration group
Together.
4. signal processing apparatus according to claim 1, which is characterized in that when the input signal is single-ended signal or difference
When sub-signal, the signal processing module handles the input signal, including：
Serioparallel exchange processing and coded treatment are carried out to the input signal, corresponding MIPI DSI letters are generated after coded treatment
Number；
When the input signal is MIPI DSI signals, the signal processing module handles the input signal, packet
It includes：
Serioparallel exchange processing is carried out to the MIPI DSI signals, corresponding MIPI DSI signals are generated after serioparallel exchange processing.
5. signal processing apparatus according to claim 1, which is characterized in that the signal processing module includes at least one
Programmable output port；
The control module is additionally operable to control the signal in the signal processing module and is exported from the programmable output port.
6. a kind of signal processing method, which is characterized in that including：
Signal processing module is configured according to the type of input signal；Wherein, the input signal is single-ended signal, difference
Signal or mobile industry processor interface series display interface MIPI DSI signals；
After receiving the input signal, according to the configuration information of the signal processing module to the input signal at
Reason, and export treated the MIPI DSI signals.
7. signal processing method according to claim 6, which is characterized in that the type according to input signal is to signal
Before processing module is configured, the method further includes：
Detect the type of the input signal；
It is described that signal processing module is configured according to the type of input signal, including：
According to the input and output IO voltages of signal processing module described in the type configuration of the input signal detected and inside
Pull-up resistor so that the type matching of the configuration information of the signal processing module and the input signal.
8. signal processing method according to claim 7, which is characterized in that the input terminal IO of the signal processing module is pre-
First it is divided into multiple configuration groups；It is described that signal processing module is configured according to the type of input signal, including：
Each configuration group in the signal processing module is configured accordingly, the configuration phase of each configuration group
Together.
9. signal processing method according to claim 6, which is characterized in that when the input signal is single-ended signal or difference
It is described that the input signal is handled when sub-signal, including：
Serioparallel exchange processing and coded treatment are carried out to the input signal, corresponding MIPI DSI letters are generated after coded treatment
Number；
It is described that the input signal is handled when the input signal is MIPI DSI signals, including：
Serioparallel exchange processing is carried out to the MIPI DSI signals, corresponding MIPI DSI signals are generated after serioparallel exchange processing.
10. signal processing method according to claim 6, which is characterized in that the signal processing module includes at least one
A programmable output port；The method further includes：
The signal in the signal processing module is compiled from described by changing the mapped file in the signal processing module
Journey output port exports.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109558177A (en) * | 2018-12-07 | 2019-04-02 | 天津光电通信技术有限公司 | Input signal Auto-matching coding/decoding method in a kind of multi-standard decoding equipment |
| CN109857451A (en) * | 2019-02-13 | 2019-06-07 | 广东高云半导体科技股份有限公司 | IP kernel document generating method, device, equipment and medium |
| CN110632866A (en) * | 2019-07-18 | 2019-12-31 | 青岛经济技术开发区海尔热水器有限公司 | Control system, control method and electronic device |
| CN114019344A (en) * | 2021-09-23 | 2022-02-08 | 惠州高盛达智显科技有限公司 | Automatic detection method and system for MIPI-DSI interface protocol signal |
| CN116561035A (en) * | 2023-07-07 | 2023-08-08 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201699873U (en) * | 2010-06-22 | 2011-01-05 | 深圳市英康仕电子有限公司 | Video conversion device |
| US20120287140A1 (en) * | 2011-05-13 | 2012-11-15 | Ming-Chieh Lin | Display Interface Circuit |
| CN103327281A (en) * | 2012-03-20 | 2013-09-25 | 联想(北京)有限公司 | Format conversion method and format conversion circuit |
| CN104780334A (en) * | 2015-04-30 | 2015-07-15 | 武汉精测电子技术股份有限公司 | Method and device achieving MIPI LANE signal serial output on basis of FPGA |
| CN104980679A (en) * | 2014-04-14 | 2015-10-14 | 亚德诺半导体集团 | Pure differential signal based MIPI DSI/CSI-2 receiver systems |
| CN105573952A (en) * | 2015-12-31 | 2016-05-11 | 西安中颖电子有限公司 | Multi-channel data transmission system |
-
2018
- 2018-02-01 CN CN201810103293.4A patent/CN108304336A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201699873U (en) * | 2010-06-22 | 2011-01-05 | 深圳市英康仕电子有限公司 | Video conversion device |
| US20120287140A1 (en) * | 2011-05-13 | 2012-11-15 | Ming-Chieh Lin | Display Interface Circuit |
| CN103327281A (en) * | 2012-03-20 | 2013-09-25 | 联想(北京)有限公司 | Format conversion method and format conversion circuit |
| CN104980679A (en) * | 2014-04-14 | 2015-10-14 | 亚德诺半导体集团 | Pure differential signal based MIPI DSI/CSI-2 receiver systems |
| CN104780334A (en) * | 2015-04-30 | 2015-07-15 | 武汉精测电子技术股份有限公司 | Method and device achieving MIPI LANE signal serial output on basis of FPGA |
| CN105573952A (en) * | 2015-12-31 | 2016-05-11 | 西安中颖电子有限公司 | Multi-channel data transmission system |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109558177A (en) * | 2018-12-07 | 2019-04-02 | 天津光电通信技术有限公司 | Input signal Auto-matching coding/decoding method in a kind of multi-standard decoding equipment |
| CN109857451A (en) * | 2019-02-13 | 2019-06-07 | 广东高云半导体科技股份有限公司 | IP kernel document generating method, device, equipment and medium |
| CN110632866A (en) * | 2019-07-18 | 2019-12-31 | 青岛经济技术开发区海尔热水器有限公司 | Control system, control method and electronic device |
| CN114019344A (en) * | 2021-09-23 | 2022-02-08 | 惠州高盛达智显科技有限公司 | Automatic detection method and system for MIPI-DSI interface protocol signal |
| CN116561035A (en) * | 2023-07-07 | 2023-08-08 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
| CN116561035B (en) * | 2023-07-07 | 2023-10-31 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
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