CN113391190A - Method for testing IC scan chain circuit based on multiple FPGA - Google Patents
Method for testing IC scan chain circuit based on multiple FPGA Download PDFInfo
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- CN113391190A CN113391190A CN202110611407.8A CN202110611407A CN113391190A CN 113391190 A CN113391190 A CN 113391190A CN 202110611407 A CN202110611407 A CN 202110611407A CN 113391190 A CN113391190 A CN 113391190A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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Abstract
The invention relates to a method for testing an IC scan chain circuit based on a plurality of FPGAs, which adopts the idea of cascade expansion to solve the problem of insufficient storage resources when a single FPGA is used as a storage entity of SCAN CHAIN pattern, and through a self-defined communication handshake mode among the FPGAs, a next-stage FPGA can know that the last-stage FPGA completes the test and needs to start the work of the current-stage FPGA, and after the test of the current-stage FPGA is completed, the next-stage FPGA is informed to start the work.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a method for testing an IC scan chain circuit based on a plurality of FPGAs.
Background
The insertion of scan chain in chip design is one of the important methods for digital integrated circuit test, and the method can effectively screen out bad chips and improve product quality. For the scan chain test, the method generally adopted in the industry is to use ATE equipment (atomic test equipment) to test the scan chain, and the equipment is highly specialized, high in price, limited in use scene and only capable of being used in a specialized IC test factory;
later, design house adopts fpga platform-based design, a scan chain test method is invented, but the method is limited by fpga resources of the selected fpga platform, for large-scale IC projects, excitation and comparison files of the scan chain may be more than XX gigabits, if resources of a RAM and an LUT of the fpga platform are insufficient, the test requirement on a scan chain circuit cannot be completed at one time, and the scan chain test scheme needs to be divided into a plurality of small schemes for completion, so that the time and the labor are consumed, and the efficiency is low.
Disclosure of Invention
The invention mainly aims to solve the problem that the realization of an IC scan chain test based on an FPGA platform is limited by insufficient FPGA resources, and provides a method for testing an IC scan chain circuit based on a plurality of FPGAs.
A method for testing an IC scan chain circuit based on a plurality of FPGAs (field programmable gate arrays), which is characterized by comprising the following steps:
a method for testing an IC scan chain circuit based on a plurality of FPGAs (field programmable gate arrays), which is characterized by comprising the following steps:
a first FPGA device sends a test request to an IC scan chain circuit of a device to be tested;
after the IC scan chain circuit of the device to be tested responds to the test request, the first FPGA device tests the test vector, when the test vector of the first FPGA device is finished, the first FPGA device sends a starting signal to the second FPGA device, the second FPGA device responds and returns a handshake success signal to the first FPGA device, and meanwhile, the second FPGA device sends the test vector to the IC scan chain circuit of the device to be tested through the first FPGA device for continuous test;
and when the test vector of the second FPGA device is tested, sending a starting signal to a third FPGA device, responding and returning a handshake success signal to the second FPGA device by the third FPGA device, sending the test vector to the IC scan chain circuit of the device to be tested by the third FPGA device sequentially through the second FPGA device and the first FPGA device, continuing the test, and so on until the test vector of the Nth FPGA device is tested, wherein the value of N is determined by the size of the IC scan chain circuit of the device to be tested.
Further, the test method for the FPGA device to perform the test vector includes a test system of a scan chain circuit implemented based on an FPGA chip, the test system is integrated on the FPGA chip, and the test method includes: the device comprises a first signal transceiving unit, a data analysis unit, a storage unit, a time sequence generation unit, a control unit, a test vector judgment unit, a result output unit and a second signal transceiving unit;
the first signal transceiving unit is used for receiving a test starting signal of a scan chain circuit of an IC to be tested or an input starting signal of a front-stage FPGA device, returning a handshake success signal of a lower-stage FPGA device to a higher-stage FPGA device, and receiving an excitation signal of an original scan chain circuit and an expected output signal of the original scan chain circuit, which are generated by simulation;
the data analysis unit is used for carrying out data analysis on the excitation signal of the original scan chain circuit generated by simulation and the expected output signal of the original scan chain circuit;
the storage unit is used for encoding the excitation signal which is analyzed by the data analysis unit and used for the scan chain circuit, exciting the detection point through the scan chain circuit after the detection point is determined, storing the output signal after excitation, and encoding and storing the expected output signal of the scan chain circuit after the analysis by the data analysis unit;
the timing sequence generating unit is used for sending out a timing sequence waveform for testing the scan chain circuit;
the control unit is used for sampling the excited output signal at the sampling time sequence provided by the time sequence generating unit according to the detection requirement of the scan chain circuit and comparing the sampling data with the stored expected output signal;
the test vector judging unit is used for detecting whether the test vector of the FPGA equipment at the current stage is tested;
the second signal receiving and sending unit is used for sending a finishing signal to the lower-level FPGA device after the test vector of the current-level FPGA device is detected, so that the lower-level FPGA device is started, and is also used for returning a handshake success signal of the lower-level FPGA device to the upper-level FPGA device;
and the result output unit is used for outputting the comparison result of the control unit, reporting an error when the comparison result is inconsistent, and outputting the comparison result when the comparison result is correct.
Further, after the previous FPGA device and the next FPGA device successfully handshake, the next FPGA device needs to send an interface timing sequence for the scan chain circuit test of the present FPGA device to the previous FPGA device, and sequentially sends the interface timing sequence to the IC scan chain circuit of the device to be tested through the previous FPGA device.
Further, the first FPGA device sends a test request to an IC scan chain circuit of the device to be tested, and the test request comprises a request and a scan chain circuit test interface.
The invention has the beneficial effects that:
the idea of cascade expansion is adopted, the problem that storage resources are insufficient when a single FPGA is used as a storage entity of a scan chain pattern is solved, through a communication handshake mode between self-defined FPGAs, a next-stage FPGA can know that a previous-stage FPGA completes testing and needs to start the work of the current-stage FPGA, and after the test of the current-stage FPGA is completed, the next-stage FPGA is informed to start working, and the test of huge scan chain circuit test vectors is realized by adopting a series chain working principle.
Drawings
Fig. 1 is a schematic flow chart in the embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a rapid charging protocol test board and a test method thereof.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," or "having," and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
For ease of understanding, the following describes a specific flow of the system and method of embodiments of the present invention.
As shown in fig. 1, a DUT (an IC scan chain circuit of a device to be tested) is connected to a first FPGA device (FPGA #0), an interface between the DUT and the first FPGA device is a scan chain interface defined by the DUT device, and for the DUT device, it can be considered that a test device is FPGA #0, and it is not necessary to sense how many FPGA devices are connected behind FPGA # 0. The FPGA #0 device initiates a scan chain test, when the test vector of the FPGA #0 is tested, the #0 device sends a test start signal to a second FPGA device (FPGA #1), the FPGA #1 returns a test ack signal to the FPGA #0, the two FPGA devices are successfully handshake-jointed, the FPGA #0 becomes a direct-through mode, and the FPGA #1 starts to send the interface timing sequence and the test vector of the scan chain and transmits the interface timing sequence and the test vector to the DUT device for testing through the # 0. It is still seen to the DUT device that FPGA #0 is sending test vectors to itself. Similarly, after the test of the FPGA #1 test vector is finished, the FPGA #1 is handshake-connected with the FPGA #2 device and is simultaneously converted into a direct-through mode, the FPGA #2 carries out the test of the test vector, …, and so on, the test vectors of the FPGA # 0-FPGA # N devices can be continuously tested all the time. Therefore, a large number of scan chain test vectors are uniformly distributed in the N +1 FPGA devices, the FPGA devices are not affected by the problems of time delay and the like caused by cascade connection of the test devices, and the sensed test devices are connected with the FPGA devices and work. According to the test principle, the cascade of test equipment of any number of stages can be realized theoretically. According to the invention, 5-level FPGAs are adopted for cascade connection, and the test of 10K + scan chain test vectors is completed.
It should be noted that the test of the scan chain circuit by a single FPGA device is a test system of the scan chain circuit implemented based on an FPGA chip, and specifically includes: the device comprises a first signal transceiving unit, a data analysis unit, a storage unit, a time sequence generation unit, a control unit, a test vector judgment unit, a result output unit and a second signal transceiving unit;
the first signal transceiving unit is used for receiving a test starting signal of a scan chain circuit of an IC to be tested or an input starting signal of a front-stage FPGA device, returning a handshake success signal of a lower-stage FPGA device to a higher-stage FPGA device, and receiving an excitation signal of an original scan chain circuit and an expected output signal of the original scan chain circuit, which are generated by simulation;
the data analysis unit is used for carrying out data analysis on the excitation signal of the original scan chain circuit generated by simulation and the expected output signal of the original scan chain circuit;
the storage unit is used for coding the excitation signal analyzed by the data analysis unit and used for the scan chain circuit, exciting the detected point through the scan chain circuit after determining the detected point, and storing the output signal after excitation, and also used for coding and storing the expected output signal of the scan chain circuit after analyzing the data analysis unit, wherein it needs to be explained that the excitation signal of the scan chain circuit is coded and the expected output signal of the scan chain circuit is coded aiming at the detected point when the detected point is coded, and the time point and the detected point are matched, because not all parts in the scan chain circuit need to be detected, but the specific points need to be detected, and marking is needed aiming at the specific points, so coding is needed;
the time sequence generating unit is used for sending out a time sequence waveform of the test scan chain circuit, is realized by using a state machine, and sends out the time sequence waveform of the test scan chain according to the waveform file stored by the storage unit;
the control unit is used for sampling the excited output signal at the sampling time sequence provided by the time sequence generating unit according to the detection requirement of the scan chain circuit and comparing the sampling data with the stored expected output signal;
the test vector judging unit is used for detecting whether the test vector of the FPGA equipment at the current stage is tested;
the second signal receiving and sending unit is used for sending a finishing signal to the lower-level FPGA device after the test vector of the current-level FPGA device is detected, so that the lower-level FPGA device is started, and is also used for returning a handshake success signal of the lower-level FPGA device to the upper-level FPGA device;
and the result output unit is used for outputting the comparison result of the control unit, reporting an error when the comparison result is inconsistent, and outputting the comparison result when the comparison result is correct. The result output unit comprises a correct comparison result output unit and an error comparison result output unit, different detection results are output through two output channels, in the embodiment, according to the check requirement of the scan chain, when the rising edge of a timing waveform scan clk of a scan chain circuit is tested, the scan data is sampled and compared with stored data, if the comparison result is inconsistent, an error is reported, if the comparison is correct, the check of the next cycle is continued until the check data check is finished, and the comparison result is output.
The system also comprises a test result display unit which is used for displaying the comparison result according to the output display time sequence which is defined in advance and respectively displaying the correct comparison result output unit and the wrong comparison result output unit.
It should be noted that, in this embodiment, the first FPGA device receives a test start signal of a scan chain circuit of an IC to be tested, and after handshaking, the first FPGA device establishes a scan chain interface connection with the scan chain circuit, and receives an excitation signal of an original scan chain circuit and an expected output signal of the original scan chain circuit, which are generated by simulation, through the first signal transceiver unit;
carrying out data analysis on the excitation signal of the original scan chain circuit generated by simulation and the expected output signal of the original scan chain circuit by a data analysis unit;
then, the excitation signal analyzed by the data analysis unit and used for the scan chain circuit is encoded by storage, the point to be detected is determined and then is excited by the scan chain circuit, the output signal after excitation is stored, and the expected output signal of the scan chain circuit analyzed by the data analysis unit is encoded and stored;
according to the time sequence waveform of the test scan chain circuit sent by the time sequence generating unit and the detection requirement of the scan chain circuit, sampling the excited output signal at the sampling time sequence provided by the time sequence generating unit, and comparing the sampling data with the stored expected output signal;
whether the testing of the testing vector of the FPGA equipment at the current stage is finished is detected, after the testing is finished, firstly, a result output unit is required to output a result compared by a control unit, when the comparison result is inconsistent, an error is reported, when the comparison result is correct, the comparison result is output, secondly, a finishing signal is required to be sent to the next stage FPGA equipment by a second signal receiving and sending unit, the next stage FPGA equipment is started, a handshake success signal of the next stage FPGA equipment is returned to the previous stage FPGA equipment, and the like, the next stage FPGA equipment is started, except that the targets and directions of receiving and sending signals of the next stage FPGA equipment are different, and the specific testing method of the testing vector is the same as that of the previous stage FPGA equipment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (4)
1. A method for testing an IC scan chain circuit based on a plurality of FPGAs (field programmable gate arrays), which is characterized by comprising the following steps:
a first FPGA device sends a test request to an IC scan chain circuit of a device to be tested;
after the IC scan chain circuit of the device to be tested responds to the test request, the first FPGA device tests the test vector, when the test vector of the first FPGA device is finished, the first FPGA device sends a starting signal to the second FPGA device, the second FPGA device responds and returns a handshake success signal to the first FPGA device, and meanwhile, the second FPGA device sends the test vector to the IC scan chain circuit of the device to be tested through the first FPGA device for continuous test;
and when the test vector of the second FPGA device is tested, sending a starting signal to a third FPGA device, responding and returning a handshake success signal to the second FPGA device by the third FPGA device, sending the test vector to the IC scan chain circuit of the device to be tested by the third FPGA device sequentially through the second FPGA device and the first FPGA device, continuing the test, and so on until the test vector of the Nth FPGA device is tested, wherein the value of N is determined by the size of the IC scan chain circuit of the device to be tested.
2. The method for testing an IC scan chain circuit based on multiple FPGAs of claim 1, wherein the testing method for the FPGA device to perform the test vector includes a testing system of the scan chain circuit based on the FPGA chip, the testing system is integrated on the FPGA chip, and includes: the device comprises a first signal transceiving unit, a data analysis unit, a storage unit, a time sequence generation unit, a control unit, a test vector judgment unit, a result output unit and a second signal transceiving unit;
the first signal transceiving unit is used for receiving a test starting signal of a scan chain circuit of an IC to be tested or an input starting signal of a front-stage FPGA device, returning a handshake success signal of a lower-stage FPGA device to a higher-stage FPGA device, and receiving an excitation signal of an original scan chain circuit and an expected output signal of the original scan chain circuit, which are generated by simulation;
the data analysis unit is used for carrying out data analysis on the excitation signal of the original scan chain circuit generated by simulation and the expected output signal of the original scan chain circuit;
the storage unit is used for encoding the excitation signal which is analyzed by the data analysis unit and used for the scan chain circuit, exciting the detection point through the scan chain circuit after the detection point is determined, storing the output signal after excitation, and encoding and storing the expected output signal of the scan chain circuit after the analysis by the data analysis unit;
the timing sequence generating unit is used for sending out a timing sequence waveform for testing the scan chain circuit;
the control unit is used for sampling the excited output signal at the sampling time sequence provided by the time sequence generating unit according to the detection requirement of the scan chain circuit and comparing the sampling data with the stored expected output signal;
the test vector judging unit is used for detecting whether the test vector of the FPGA equipment at the current stage is tested;
the second signal receiving and sending unit is used for sending a finishing signal to the lower-level FPGA device after the test vector of the current-level FPGA device is detected, so that the lower-level FPGA device is started, and is also used for returning a handshake success signal of the lower-level FPGA device to the upper-level FPGA device;
and the result output unit is used for outputting the comparison result of the control unit, reporting an error when the comparison result is inconsistent, and outputting the comparison result when the comparison result is correct.
3. The method of claim 1, wherein the method comprises: after the previous FPGA device and the next FPGA device successfully handshake, the next FPGA device needs to send an interface time sequence for the FPGA device to perform scan chain circuit test to the previous FPGA device, and the interface time sequence is sent to an IC scan chain circuit of a device to be tested through the previous FPGA device in sequence.
4. The method of claim 1, wherein the method comprises: the first FPGA device sends a test request to an IC scan chain circuit of a device to be tested, wherein the test request comprises a request and a scan chain circuit test interface.
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