CN116414765A - FPGA chip, transparent transmission method, logic test module and method - Google Patents

Abstract

The invention relates to the technical field of chips, and provides an FPGA chip, a transparent transmission method, a logic test module and a logic test method. The FPGA chip comprises a first serial interface, a first control module, a second control module and a second serial interface; the first control module is also connected with an upper-level FPGA chip, and the second control module is connected with a lower-level FPGA chip to realize the transparent transmission of read-write commands; the first serial interface is connected with a corresponding serial interface of the upper FPGA chip, and the second serial interface is connected with a corresponding serial interface of the lower FPGA chip, so that transparent transmission of read-write data is realized. The invention can support vector depth expansion of the test vector, further carries out corresponding depth expansion according to the test requirement, does not need to change addressing logic when carrying out vector depth expansion, and realizes data transmission through the addressing logic inside each FPGA chip, thereby increasing the expansion flexibility.

Description

FPGA chip, transparent transmission method, logic test module and method

Technical Field

The invention relates to the technical field of chips, in particular to an FPGA chip, a transparent transmission method, a logic test module and a logic test method.

Background

In the prior art, the integration level of the GPU chip is high, the larger the circuit scale is, the larger the test vector corresponding to the required design is, but the existing aging technology can only provide the vector depth of 24M patterns per channel at maximum, and can only support 128 channels at maximum, under the specification, the aging coverage rate of the chip is less than 50%, but in actual use, the aging coverage rate of the aging case is often at least 80% to have the reliability of testing aging, otherwise, the quality risk is brought to the future by the internal modules and circuits which cannot cover part of the circuit.

In the prior art, the storage of the test vector is realized through a single DDR memory, but due to the capacity limitation of the DDR memory, the vector depth of 24M per channel of the single DDR memory can only be realized, which is far from supporting 80% of aging coverage rate, and the reliability of the aging test is insufficient.

In view of this, overcoming the drawbacks of the prior art is a problem to be solved in the art.

Disclosure of Invention

The invention aims to solve the technical problems that the aging coverage rate of a chip is not high and the aging reliability is not enough due to insufficient vector depth of a test vector which can be supported by the prior art.

The invention adopts the following technical scheme:

In a first aspect, the invention provides an FPGA chip supporting transparent transmission, including a first serial interface, a first control module, a second control module, and a second serial interface;

the first serial interface is connected with a first control module, the first control module is connected with the second control module, and the second control module is connected with the second serial interface;

the first control module is also used for being connected with a corresponding control module of the upper-level FPGA chip to form an uplink control data transmission channel; the second control module is used for being connected with a corresponding control module of the lower-level FPGA chip to form a downlink control data transmission channel; through the uplink control data transmission channel and the downlink control data transmission channel, transparent transmission of a read command and/or a write command is realized;

the first serial interface is used for being connected with a corresponding serial interface of the upper FPGA chip to form an upper-level read-write data transmission channel; the second serial interface is used for being connected with a corresponding serial interface of the lower-level FPGA chip to form a lower-level read-write data transmission channel; and through the upper read-write data transmission channel and the lower read-write data transmission channel, the transparent transmission of read data and/or write data is realized.

Preferably, the first control module is connected to the second control module through an AXI bus and an APB bus, where the AXI bus is used to form an intermediate read/write data transmission channel, and the APB bus is used to form an intermediate control data transmission channel.

In a second aspect, the present invention provides a transparent transmission method, using the FPGA chip supporting transparent transmission according to the first aspect, where the method includes:

the first control module obtains a Bank address carried in a read command or a write command according to the read command or the write command issued by the upper FPGA chip;

addressing a memory connected with the FPGA chip according to the Bank address, if the addressing results in that the Bank address does not belong to the memory, transmitting the read command or the write command to a second control module, and transmitting the read command or the write command to a subordinate FPGA chip through a downlink control data transmission channel by the second control module;

if the addressing results in that the Bank address belongs to the memory, finding out the target address corresponding to the memory according to the read command or the write command, and performing read operation or write operation on the target address.

Preferably, the method further comprises:

The second serial interface receives the read data from the lower FPGA module through the lower read-write data transmission channel, the read data is transmitted to the second control module, the second control module transmits the read data to the first control module, the first control module transmits the read data to the first serial interface, and the first serial interface transmits the read data to the upper FPGA chip through the upper read-write data transmission channel.

Preferably, a chip mark number is preset in an FPGA chip, and the chip mark number is carried in a Bank address of the read command or the write command;

the addressing the memory according to the Bank address specifically includes:

judging whether the chip mark number carried in the read command or the write command is consistent with the chip mark number of the memory, if so, addressing to obtain the Bank address belongs to the memory, otherwise, addressing to obtain the Bank address does not belong to the memory.

Preferably, the read command includes a Bank address, a row address, and a column address, and the write command includes a Bank address, a row address, and a column address.

In a third aspect, the present invention provides a logic test module, including a master FPGA chip, a plurality of slave FPGA chips, and a plurality of memories, where the master FPGA chip and the plurality of slave FPGA chips are sequentially cascaded, each FPGA chip is connected to a corresponding memory, based on a cascade relationship, the slave FPGA chips located in a middle position of the cascade relationship are used as middle FPGA chips, each middle FPGA chip is the FPGA chip supporting transparent transmission described in the first aspect, and each middle FPGA chip executes the transparent transmission method described in the second aspect;

The serial interface of the master FPGA chip is connected with the first serial interface of the first slave FPGA chip, and the control module of the master FPGA chip is connected with the first control module of the first slave FPGA chip;

in each intermediate FPGA chip, a second serial interface of the upper-stage FPGA chip is connected with a first serial interface of the lower-stage FPGA chip, and a second control module of the upper-stage FPGA chip is connected with a first control module of the lower-stage FPGA chip;

the second serial interface of the last intermediate FPGA chip is connected with the serial interface of the last slave FPGA chip, and the second control module of the last intermediate FPGA chip is connected with the control module of the last slave FPGA chip.

Preferably, the main FPGA chip includes a PCIE interface, a control module, and a serial interface;

the control module is connected with the serial interface, and the PCIE interface is connected with the control module;

the PCIE interface is used for being connected with the upper computer so as to receive a read command or a write command from the upper computer or return a test result to the upper computer;

and the control module is used for carrying out read operation or write operation on the corresponding memory according to the read command or the write command, or transmitting the read command or the write command to the first slave FPGA chip.

In a fourth aspect, the present embodiment provides a logic testing method, using the logic testing module of the third aspect, the method including:

before testing, the main FPGA chip receives a write command from an upper computer, and performs write operation on a memory of the main FPGA chip or performs write operation on a memory of a corresponding slave FPGA chip according to the write command so as to write each test vector into the main FPGA chip or the slave FPGA chip, and returns a corresponding memory address to the upper computer, so that the upper computer can generate a corresponding read command according to each memory address during testing;

when testing is carried out, the main FPGA chip receives a read command from an upper computer, and corresponding test vectors are read from a memory of the main FPGA chip or a memory of the FPGA chip according to the read command;

and testing the chip to be tested according to the test vector to obtain a test result, and transmitting the test result to an upper computer.

Preferably, the testing of the chip to be tested according to the test vector, to obtain a test result, specifically includes:

generating a test waveform and a judgment waveform according to the test vector, and sending the test waveform to a test vector input end of a chip to be tested;

Receiving an output waveform from a chip to be tested, and comparing the output waveform with the judging waveform to obtain a test result;

wherein data 0 and data 1 are converted into test waveforms; data 0 transitions to a low level and data 1 transitions to a high level; converting the data L, the data H and the data X into judging waveforms; the data L is switched to low level and the data H is switched to high level, the data X representing that the output waveforms are not compared.

The invention provides the transparent FPGA chip and the corresponding transparent transmission method, and the logic test module and the logic test method are realized by using the chip and the method, so that vector depth expansion of test vectors can be supported, corresponding depth expansion is further carried out according to test requirements, the aging coverage rate and the aging reliability of the chip are ensured, and the addressing logic is not required to be changed while the vector depth expansion is carried out, but the transparent transmission of data is realized through the addressing logic in each FPGA chip, thereby increasing the flexibility of expansion.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the embodiments of the present invention will be briefly described below. It is evident that the drawings described below are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic diagram of an architecture of an FPGA supporting transparent transmission according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an architecture of a transparent FPGA in a cascade relationship according to an embodiment of the present invention;

FIG. 3 is a schematic flow chart of a transparent transmission method according to an embodiment of the present invention;

FIG. 4 is a schematic flow chart of another transparent transmission method according to an embodiment of the present invention;

FIG. 5 is a schematic flow chart of another transparent transmission method according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a logic test module according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another logic test module according to an embodiment of the present invention;

FIG. 8 is a schematic flow chart of a logic test method according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a test waveform, a judgment waveform and an output waveform of a chip to be tested in a logic test method according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a logic test module applied in an actual application scenario according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The terms "first," "second," and the like herein are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the present application, unless explicitly specified and limited otherwise, the term "coupled" is to be construed broadly, and for example, "coupled" may be either fixedly coupled, detachably coupled, or integrally formed; can be directly connected or indirectly connected through an intermediate medium. Furthermore, the term "coupled" may be a means of electrical connection for achieving signal transmission.

In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

In order to solve the problem that the aging coverage rate of a chip is not high due to insufficient vector depth of a test vector which can be supported by the prior art, the embodiment of the invention provides an FPGA (Field-Programmable Gate Array, field programmable gate array) chip supporting transparent transmission, as shown in fig. 1, comprising a first serial interface, a first control module, a second control module and a second serial interface; one of the FPGA chips corresponds to a memory (not shown in the figure), and the memory is located outside the FPGA chip and connected to a data bus of the FPGA (i.e., a data bus for connecting the first control module and the second control module) through a memory interface, so as to implement read-write control of the FPGA chip on the memory. In some embodiments, as shown in fig. 2, the first serial interface and the second serial interface may be SerDes (Serializer-Deserializer) interfaces, the first serial interface and the second serial interface may be GTH (Gigabyte Transceiver-H, H-model G-bit transceiver) interfaces in the SerDes interfaces, the memory may be DDR (Double Data Rate SDRAM, double rate synchronous dynamic random access memory) memories, the first control module and the second control module may be CTRL (controller) modules, also referred to as GTH controllers, for data transmission control of the first GTH interface or the second GTH interface, and the data bus to which the memory is connected to the first control module may be an AXI (Advanced eXtensible Interface ) bus. The first serial interface is connected with a first control module, the first control module is connected with the second control module, and the second control module is connected with the second serial interface; the first control module is used for being connected with a corresponding control module of the upper-level FPGA chip to form an uplink control data transmission channel; the second control module is used for being connected with a corresponding control module of the lower-level FPGA chip to form a downlink control data transmission channel; through the uplink control data transmission channel and the downlink control data transmission channel, transparent transmission of a read command and/or a write command is realized; the upper-level FPGA chip and the lower-level FPGA chip are both FPGA chips which are cascaded with the FPGA chip describing the main body and are adjacent, the source direction of the read-write command is taken as the upper level according to the flow direction of the read-write command, and the flow direction of the read-write command is taken as the lower level. The upper control data transmission channel is used for transmitting read-write commands with the upper FPGA chip, and the lower control data transmission channel is used for transmitting read-write commands with the lower FPGA chip.

The transparent transmission of the read command and/or the write command refers to transmitting the read/write command from the upper-level FPGA chip to the lower-level FPGA chip without being executed by itself. The read command and the write command are also referred to as control data in the following.

The first serial interface is used for being connected with a corresponding serial interface of the upper FPGA chip to form an upper-level read-write data transmission channel; the second serial interface is used for being connected with a corresponding serial interface of the lower-level FPGA chip to form a lower-level read-write data transmission channel; and through the upper read-write data transmission channel and the lower read-write data transmission channel, the transparent transmission of read data and/or write data is realized. The upper read-write data transmission channel is used for transmitting read-write data with the upper FPGA chip, and the lower read-write data transmission channel is used for transmitting read-write data with the lower FPGA chip. The transparent transmission of the read data and/or the write data refers to transmitting the read data from the upper FPGA chip to the lower FPGA chip or transmitting the read data from the lower FPGA chip to the upper FPGA chip.

It should be noted that, the above description is based on the middle FPGA chip in the cascade relationship as the description main body, for example, in fig. 2, there are 3 FPGA chips including the FPGA chip 1, the FPGA chip 2 and the FPGA chip 3, and the 3 FPGA chips form a cascade connection, and the above description is based on the FPGA chip 2 as the description main body, and the upper FPGA chip and the lower FPGA chip are both relatively related to the FPGA chip describing the main body, that is, the FPGA chip 1 is the upper FPGA chip of the FPGA chip 2, and the FPGA chip 3 is the lower FPGA chip of the FPGA chip 2.

Taking the FPGA chip shown in fig. 1 as an example, the first control module is connected to the second control module through an AXI bus and an APB (Advanced Peripheral Bus ) bus, where the AXI bus is used to form an intermediate read/write data transmission channel, and the APB bus is used to form an intermediate control data transmission channel. The upper, middle and lower read-write data transmission channels constitute a complete read-write data transmission channel, and the upper, middle and lower control data transmission channels constitute a complete control data (i.e. read-write command) transmission channel.

The first control module is connected with the first serial interface through a DFI (Digital Facility Interface, digital equipment interface) bus and an APB bus, and performs clock synchronization, the second control module is connected with the second serial interface through the DFI bus and the APB bus, and performs clock synchronization, the first control module is connected with the upper FPGA chip through an I2C bus, and the second control module is connected with the lower FPGA chip through an I2C (Inter-Integrated Circuit, integrated circuit bus) bus.

The FPGA chip supporting transparent transmission in this embodiment is configured with two control modules and two serial interfaces in the FPGA chip, and connects the two control modules, so that connection and communication with two directions can be implemented, and transparent transmission of commands and data can be implemented while controlling its own memory.

On the basis of the above FPGA chip supporting transparent transmission provided in the present embodiment, this embodiment further provides a transparent transmission method, and the above FPGA chip supporting transparent transmission is used, as shown in fig. 3, where the method includes:

in step 201, the first control module obtains a Bank address carried in a read command or a write command according to the read command or the write command issued by the upper FPGA chip; wherein the read command includes a Bank address, a row address, and a column address, and the write command includes a Bank address, a row address, and a column address. The address rule of the memory generally includes a plurality of banks, each Bank corresponds to a Bank address, each Bank includes a plurality of rows and a plurality of columns, each row corresponds to a row address, and each column corresponds to a column address, so that a precise memory access position can be obtained according to the Bank address, the row address and the column address.

In step 202, a memory connected to the FPGA chip is addressed according to the Bank address, and if the addressing results in that the Bank address does not belong to the memory, the read command or the write command is transmitted to a second control module, and the second control module transparently transmits the read command or the write command to a subordinate FPGA chip through a downlink control data transmission channel. When the corresponding Bank address cannot be found in the memory corresponding to the read command or the write command is considered to be not used for the memory, and the read command or the write command is transmitted through.

In step 203, if the Bank address belongs to the memory, a target address corresponding to the memory is found according to a read command or a write command, and a read operation or a write operation is performed on the target address. When the corresponding Bank address is found in the corresponding memory, the read command or the write command is considered to be used for the memory.

After executing the read command, the read data is generally returned, and in combination with the embodiment of the present invention, as shown in fig. 4, the association steps in the embodiment are further integrated for presentation.

In step 204, the second serial interface receives the read data from the lower FPGA module through the lower read-write data transmission channel, and transmits the read data to the second control module, the second control module transmits the read data to the first control module, the first control module transmits the read data to the first serial interface, and the first serial interface transmits the read data to the upper FPGA chip through the upper read-write data transmission channel. Until the data reaches the top FPGA chip in the cascade relationship, the top FPGA chip processes the read data or forwards the read data to other modules, for example, in the content of the subsequent embodiment, the read data is sent to the upper computer through the top FPGA chip (i.e. the main FPGA chip in the subsequent embodiment), and the part will not be described in detail in the content of the subsequent embodiment.

In some embodiments, since the memories corresponding to different FPGA chips may have the same Bank address, when a plurality of FPGA chips are cascaded, the Bank address in the memories corresponding to different FPGA chips may be repeated, resulting in the disorder of addressing of the Bank address, so as to solve the problem, this embodiment provides a preferred embodiment, which specifically includes: presetting a chip mark number in an FPGA chip, wherein the chip mark number is carried in a Bank address of the read command or the write command; wherein, a plurality of FPGA chips in cascade connection have different chip mark numbers.

The addressing the memory according to the Bank address, as shown in fig. 5, specifically includes:

in step 301, it is determined whether the chip flag number carried in the read command or the write command is consistent with the chip flag number of the memory;

in step 302, if the addresses are consistent, addressing to obtain that the Bank address belongs to the memory;

in step 303, otherwise, addressing results in the Bank address not belonging to the memory. In some embodiments, the chip flag is determined by a GPIO (General-purpose input/output) that is idle on the FPGA and a pull-up or pull-down resistor that is externally connected, where the pull-up resistor is denoted as 1 to high level, the pull-down resistor is denoted as 0 to low level, and a series of 0 and 1 codes is formed and this code is the chip flag. When the FPGA is powered on, the high-low level state on the group of GPIOs can be automatically positioned, and an addressing command is waited for comparison. If 8 same GPIOs are reserved for each FPGA, GPIO1 of FPGA1 is connected with a pull-up resistor of 4.7K to a high level, GPIO2-8 are connected with a pull-down resistor to a low level, GPIO8:1 can form coding 00000001 as a chip mark number of FPGA 1. The tag number can be used for temporarily adjusting the transformation according to the requirement in the application.

According to the transparent transmission method, the first control module is used for carrying out transparent transmission logic judgment and self memory control, and the second control module is used for carrying out transmission of control data or read-write data to the lower-level FPGA chip, so that transparent transmission of data is achieved, a plurality of FPGAs are mutually cascaded, and operation of a plurality of memories under the same read-write logic is possible.

On the basis of providing an FPGA chip supporting transparent transmission and a transparent transmission method in the foregoing embodiments, this embodiment further provides a logic test module, as shown in fig. 6, including a master FPGA chip, a plurality of slave FPGA chips, and a plurality of memories, where the master FPGA chip and the plurality of slave FPGA chips are cascaded in turn, and each FPGA chip is connected with a corresponding memory. Based on the cascade connection, taking the slave FPGA chips positioned in the middle of the cascade connection as intermediate FPGA chips, wherein each intermediate FPGA chip is the FPGA chip supporting the transparent transmission, and each intermediate FPGA chip executes the transparent transmission method; the master FPGA chip is the uppermost FPGA chip in the cascade relationship, for example, in fig. 2, when there is an FPGA chip 1, an FPGA chip 2, and an FPGA chip 3 that are cascaded in sequence, the FPGA chip 1 is the master FPGA chip, and the FPGA chip 2 and the FPGA chip 3 are slave FPGA chips, where the FPGA chip 2 is located in the middle of the cascade relationship, so that the FPGA chip 2 is the middle FPGA chip.

The serial interface of the master FPGA chip is connected with the first serial interface of the first slave FPGA chip, and the control module of the master FPGA chip is connected with the first control module of the first slave FPGA chip; in each intermediate FPGA chip, a second serial interface of the upper-stage FPGA chip is connected with a first serial interface of the lower-stage FPGA chip, and a second control module of the upper-stage FPGA chip is connected with a first control module of the lower-stage FPGA chip; here, the upper-level FPGA chip and the lower-level FPGA chip are two FPGA chips, and taking fig. 2 as an example, for the FPGA chip 1 and the FPGA chip 2, the FPGA chip 1 is the upper-level FPGA chip of the FPGA chip 2, and the FPGA chip 2 is the lower-level FPGA chip of the FPGA chip 1.

The second serial interface of the last intermediate FPGA chip is connected with the serial interface of the last slave FPGA chip, and the second control module of the last intermediate FPGA chip is connected with the first control module of the last slave FPGA chip so as to provide a larger test vector storage space and increase the vector depth of the test vectors through memories of a plurality of FPGA chips. In an alternative embodiment, the control modules of adjacent FPGA chips are connected by an I2C bus.

The main FPGA chip comprises a PCIE interface, a control module and a serial interface; the control module is connected with the serial interface, and the PCIE interface is connected with the control module; the PCIE interface is used for being connected with the upper computer so as to receive a read command or a write command from the upper computer or return a test result to the upper computer; and the control module is used for carrying out read operation or write operation on the corresponding memory according to the read command or the write command, or transmitting the read command or the write command to the first slave FPGA chip.

In some embodiments, as shown in fig. 7, the main FPGA chip further includes a test logic circuit for implementing data sending logic, data parsing logic, timing generation logic, vector judgment logic, and result output logic, which will be described in detail in the following embodiment, and will not be described herein.

The logic test module in this embodiment is cascaded through a plurality of FPGA chips, and uses the FPGA chip supporting transparent transmission in the middle position of the cascade relationship, so as to implement the cascade relationship between a plurality of memories, so that the size of the required storage space can be flexibly adjusted through the number of cascaded FPGA chips under the same set of read-write logic, and even when the storage space changes, the read-write logic of the upper layer still does not need to be changed, thereby implementing flexible and adjustable storage space.

On the basis of providing a logic test module as described above, this embodiment also provides a logic test method, using the logic test module as described above, as shown in fig. 8, where the method includes:

in step 401, before performing a test, the main FPGA chip receives a write command from an upper computer;

in step 402, according to the write command, a write operation is performed on the memory of the master FPGA chip, or a write operation is performed on the memory of the corresponding slave FPGA chip, so that each test vector is written into the master FPGA chip or the slave FPGA chip, and a corresponding memory address is returned to the upper computer, so that when the upper computer is tested, a corresponding read command is generated according to each memory address;

in step 403, the main FPGA chip receives a read command from the host computer when performing the test;

in step 404, according to the read command, a corresponding test vector is read from the memory of the main FPGA chip or from the memory of the FPGA chip; and testing the chip to be tested according to the test vector to obtain a test result, and transmitting the test result to an upper computer.

In an optional embodiment, the testing of the chip to be tested according to the test vector, to obtain a test result, specifically includes:

Generating a test waveform and a judgment waveform according to the test vector, and sending the test waveform to a test vector input end of a chip to be tested;

receiving an output waveform from a chip to be tested, and comparing the output waveform with the judging waveform to obtain a test result; wherein data 0 and data 1 are converted into test waveforms; data 0 transitions to a low level and data 1 transitions to a high level; converting the data L, the data H and the data X into judging waveforms; the data L is switched to low level and the data H is switched to high level, the data X representing that the output waveforms are not compared.

For example, in fig. 9, a test waveform is obtained by converting data 0100010 in a test vector, a judging waveform is obtained by converting data LHXXHHLH in the test vector, wherein a position corresponding to X may be filled with a high level, a low level, or no output level, if the output waveform of the chip to be tested is as shown in fig. 9, the output waveform of the chip to be tested is available in comparison with the judging waveform, and other positions of the output waveform except for the position corresponding to the position of X of the judging waveform are consistent with the judging waveform, the test result is normal, otherwise, if the output waveform of the chip to be tested is inconsistent with the judging waveform when the position corresponding to the position of H of the judging waveform is low level, the output waveform of the chip to be tested is abnormal, wherein the output waveform of the chip to be tested corresponding to the position of the judging waveform X may be either high level or low level, and the test result of the chip to be tested is not affected because the comparison and judgment are not performed on the position.

When the upper computer writes test vectors into the memories of the FGPA chips, the upper computer stores corresponding storage addresses, and similarly, when the upper computer tests, the upper computer carries corresponding storage addresses (namely a Bank address, a row address and a column address) in the issued read command according to the test requirements and the storage addresses, so that the test vectors are obtained from the memories of the corresponding FPGA chips.

According to the embodiment, the logic test module is applied to the test scene of the chip, so that the vector depth of the test vector can be increased, a larger-scale circuit in the chip is covered, the aging coverage rate is improved, and the effectiveness of chip test is ensured.

In some embodiments, there may be a sequence requirement for testing the chip, where the corresponding test vector is required to be executed first and then executed, and in combination with this specific usage scenario, the present embodiment further provides the following preferred embodiments, including specifically:

and taking a plurality of test vectors which need to be sequentially executed as a test vector group, and continuously storing each test vector in the test vector group according to the execution sequence, for example, storing each test vector in a memory of a single FPGA chip according to the execution sequence or storing each test vector in a memory of an adjacent FPGA chip according to a cascade relation among the FPGA chips. In this embodiment, each FPGA chip is cascaded in a serial manner, and when the memory of the previous FPGA chip is full, the memory of the next FPGA chip is stored; for example, if there is one test vector group, the test vector group includes 5 test vectors A, B, C, D and E that need to be sequentially executed, i.e., group= { a, B, C, D, E }, if a and B are stored in DDR1 (i.e., from the memory of FPGA chip 1), C, D and E are stored in the memory DDR2 corresponding to FGPA chip 2 directly connected to FPGA chip 1 because the memory space of DDR1 is exhausted.

When the upper computer stores the corresponding storage address, the storage head address of the test vector group (namely the storage address of the first test vector in the test vector group) and the offset of the storage address of each test vector relative to the storage address of the last test vector are stored, wherein the offset is used for identifying the offset between the storage addresses of the test vectors in the storage, and the length of the last test vector is stored, and the length is used for identifying the size of the space occupied by the corresponding test vector; still taking the example of storing test vectors a and B in the same test vector set in DDR1, C, D and E in DDR2, then when storing the memory address of the test vector set, the following information may be stored: (p_a), (len_a), (len_b), (len_c) and (len_d, len_e), wherein p_a represents that a position where the p_a address is located stores a, B follows a storage of a, so that an offset of the storage address of B relative to p_a is len_a (i.e. the length of a), C is stored in DDR2, an offset relative to B is len_b (i.e. the length of B), and so on until E is the last test vector of the test vector set, and the length len_e thereof is stored.

It should be noted that, the basic offset value len_ A, len _c is used for descriptive convenience, and is not obtained by using the length of the test vector as an offset in actual use, but is obtained based on analysis of the storage structure characteristics of the memory.

When the test vectors are read, the upper computer only issues a read command once, the read command carries address information of all the test vectors of the test vector group, the follow-up operation is not required to be controlled, but all the FPGA chips continuously read, and the FPGA chips read the test vectors according to the chip offset and the basic offset of all the test vectors, and the method specifically comprises the following steps:

when the corresponding FPGA chip addresses to obtain that the first test vector of the test vector group is positioned in the memory of the corresponding FPGA chip, the first test vector is read from the memory of the corresponding FPGA chip, and sequentially and backwards offset is carried out, the test vector is read in the offset process until the offset reaches the storage position of the second test vector, the second test vector is read, and so on until the last test vector of the read test vector group is completed, or the end of the memory is read, and when the last test vector of the test vector group is still not read, the read command is issued to the next FPGA chip so as to facilitate the next FPGA chip to carry out subsequent reading.

Because a plurality of FPGA chips are cascaded in a serial connection mode, when the test vectors stored in the FPGA chips at the final stage are read, each slave FPGA chip in the middle is required to pass through, and because the transmission path is long and a plurality of interfaces are required to pass through, and the transmission between each interface and each interface has a certain delay, the data reading time in the DDR of the FPGA chips at the final stage is relatively long, namely in the cascade connection, the DDR data reading time of the FPGA chips at the upper stage is shorter, the DDR data reading time of the FPGA chips at the lower stage is shorter, the main FPGA chip reading time is shortest, and the reading time of the FPGA chips at the final stage is longest. In practical use, in order to test a large number of chips to be tested with different types, one logic test module may be multiplexed into the tests of multiple chips to be tested, and in order to be suitable for multiple chips to be tested, test vectors required by the various chips to be tested are often stored in the logic test module in advance, and corresponding test vectors are selectively read according to the types of the chips to be tested, so as to test the chips to be tested, in order to improve the test efficiency, in combination with the above embodiment, the embodiment further provides a preferred implementation manner, which specifically includes:

In the process of testing a large number of chips to be tested, the calling frequency (namely, the reading frequency) of each test vector is counted, each preset time period is set at intervals, according to the counting result of the calling frequency of each test vector, the test vector with high calling frequency is migrated to the upper-level FPGA chip, the test vector with low calling frequency is migrated to the lower-level FPGA chip, and the preset time period is obtained by analysis according to experience of a person skilled in the art, for example, one or more test periods of the chips to be tested are selected as the preset time period. And regarding the test vector group, taking the average value of the dispatching frequency of each vector in the test vector group as the dispatching frequency of the test vector group, and carrying out overall dispatching migration on the test vector group.

An optional test vector migration method is also provided herein, specifically including: a corresponding scheduling frequency range (including an upper scheduling frequency limit and a lower scheduling frequency limit) is preset for each FPGA chip, for example, when one master FPGA chip is connected in series with 4 slave FPGA chips, the corresponding upper scheduling frequency limit and lower scheduling frequency limit are preset as shown in the following table:

and taking the test vectors exceeding the corresponding dispatching frequency range in the memories corresponding to the corresponding FPGA chips as target test vectors, sequentially calculating the total volume of all target test vectors in the corresponding calling frequency range of each FPGA chip from the main FPGA chip, and judging whether the memories corresponding to the FPGA chips can store all the target test vectors in the corresponding dispatching frequency range according to the total volume.

If the target test vectors can be stored, all the target test vectors in the corresponding dispatching frequency range are directly migrated to a memory of the corresponding FPGA chip; if all the target test vectors in the corresponding dispatching frequency range cannot be stored, sorting the target test vectors in the dispatching frequency range according to the dispatching frequency, preferentially transferring the target test vector with high dispatching frequency to a memory corresponding to the FPGA chip, and transferring the rest target test vectors in the dispatching frequency range (namely, the target test vectors transferred to the memory corresponding to the FPGA chip) and the target test vectors in the next stage dispatching frequency range together participate in a transferring process of the target test vectors in the next stage dispatching frequency range, wherein when sorting is performed, the target test vectors which are not transferred in the previous stage are preferentially sorted.

For example, if 40 target test vectors are located in the [8, 20] scheduling frequency interval, the remaining space of the memory of the main FPGA chip cannot support and store all 40 test vectors, then the 30 test vectors with high scheduling frequency are preferentially stored in the memory of the main FPGA chip according to the order of the scheduling frequency from high to low, and the remaining 10 test vectors participate in migration together with the target test vectors in the (6, 18) scheduling frequency interval, if the target test vectors in the (6, 18) scheduling frequency interval share 15, but the memory of the slave FPGA1 chip cannot support all the stored (15 test vectors in the (6, 18) scheduling frequency interval and the remaining 10 target test vectors in the [8, 20] scheduling frequency interval, then the scheduling frequency of the remaining 10 target test vectors in the [8, 20] scheduling frequency interval is always higher than the 15 test vectors in the (6, 18) scheduling frequency interval during the order, so that the remaining 10 target test vectors in the slave FPGA1 chip memory of the [8, 20] scheduling frequency interval are preferentially stored, and the slave FPGA1 chip cannot participate in the migration frequency range corresponding to the target test vectors in the FPGA1 chip according to the scheduling frequency interval, and the migration frequency is not completed by the target test vectors.

In a preferred embodiment, since it takes a certain time to perform migration of the test vector, the progress of the chip test may be affected, and thus whether to perform migration of the test vector and the migration position of the test vector may be comprehensively determined according to the migration cost of the test vector (mainly represented as the time cost required for migration of the test vector in this embodiment), the call frequency of the test vector, the storage space size of each memory, and the call cost of the test vector, specifically including:

calculating total call cost after migration

Calculating the memory space size of the corresponding memory after migration>

Total migration cost consumed for computing migration +.>

The method comprises the steps of carrying out a first treatment on the surface of the Wherein M is the number of test vectors, i represents the ith test vector, N is the number of memories for storing test vectors, j represents the jth memory,>

representing the call cost corresponding when storing the test vector in the jth memory, the data read time of the jth memory can be used in actual use as +.>

，/>

Representing the call frequency of the ith test vector, < >>

Representing whether the ith test vector is stored in the jth memory after migration, wherein, when the ith test vector is stored in the jth memory after migration, the +_is >

Otherwise, let(s)>

。

Representing the size of the ith test vector, < >>

Representing the total memory space size occupied by the memory vector in the j-th memory after migration; />

For the migration cost of the ith test vector, if the ith test vector needs to be migrated, the method is +.>

Wherein, since the migration process is usually to read the test vector first and write the test vector then, the migration cost is the sum of the migration costs of the front and rear memories, +.>

For the migration cost of the memory of the ith test vector before migration, the data reading time of the memory before migration can be used for replacing +.>

The migration cost of the memory where the ith test vector is located after migration can be replaced by the data reading time of the memory where the ith test vector is located after migration in actual use; otherwise, go (L)>

0。/>

To be used for

As constraint function, in->

The minimum is a constraint function, a migration model is established, the migration model is solved, storage positions after migration of each test vector are obtained, and if the storage positions after migration are different from the current storage positions, migration of the test vectors is carried out; wherein (1)>

The amount of memory available for storing test vectors for the jth memory is G, which is a trade-off between migration and scheduling. The migration model may be a particle swarm algorithm PSO model, and k is a preset coefficient obtained by empirical analysis by a person skilled in the art.

Under the implementation mode, balance control of migration cost and calling cost can be realized, so that the calling efficiency of the test vector is improved under the condition of reducing the test vector migration time.

It should be noted that, in the foregoing embodiment, the read command does not represent a read command in a conventional sense, but refers to a generic term of a command for reading data, and the write command does not represent a write command in a conventional sense, but refers to a generic term of a command for writing data, in a conventional sense, a command for reading data or for writing data often includes two types, one type is a row activation, including a Bank address and a row address, and the other type is referred to as a read command or a write command, including a column address and a specific operation command, and in the subsequent embodiment, description of the subsequent embodiment will be made in terms of the read command and the write command in a conventional sense.

The implementation process in the characteristic scene of the present invention will be described below by combining specific application scenes based on the logic test module and the logic test method described in the above embodiments and by means of technical expressions in the relevant scenes.

Taking the GPU chip testing scenario shown in fig. 10 as an example, the GPU chip testing scenario includes a device workstation and a chip testing module connected to the device workstation, the logic testing module (i.e., the digital logic testing module in fig. 10) described in the above embodiment is applied to the device workstation, the control bus in fig. 10 is an APB bus, and the data bus is an AXI bus. The logic test module uses the logic test method described in the above embodiment, and as shown in fig. 7, the logic test module includes 1 master FPGA chip, several slave chips, and multiple DDR memories.

The multiple slave FPGA chips are used for expanding the capacity of the pattern (i.e. the test vector in the above embodiment), and cascade connection of SerDes interfaces between the FPGA chips is used as a chip (chip), so that the master FPGA chip can access any one DDR memory of the slave FPGA chip quickly in real time, and the pattern is stored in different DDR memories according to design continuity in advance, so that data in the DDR memory of the slave FPGA chip can be read into the master FPGA chip quickly for real-time test, and the problem of discontinuity of the pattern is avoided. The main FPGA chip also comprises data analysis logic, time sequence generation logic, data transmission logic, vector judgment logic and result output logic, and the logic is realized through corresponding circuits.

The data of the pattern is stored into the DDR memory, or the processor reads the data of the pattern from the DDR memory, which is realized based on the DDR addressing mode. To read the data of a particular cell, it is first determined which Bank is addressed, and then the addressing of the rows and columns is performed in this selected Bank. In actual operation, the Bank address and the corresponding row address are issued simultaneously, and this command is referred to as "row valid" or "row active". After this, a column address addressing command and a specific operation command (read or write) are sent, which are also sent simultaneously. The row and column addresses are multiplexed, typically the address lines A0-A15 of the DDR chip, and the low address lines are multiplexed by rows and columns.

Taking the DDR memory chip of K4B4G1646B 4Gbit 256MB x 16bit as an example, A0-A14 are used as row addresses, A0-A9 are used as column addresses, and the chip also contains B0-B2 for selecting the Bank. In actual operation, the Bank address and the corresponding Row address are issued simultaneously, and this command is called "Row Active" (Row Active). After this, a column address addressing command is sent along with a specific operation command (read or write), which are also issued simultaneously, so column addressing is generally indicated as "read/write command". The interval from row valid to read/write command issue is defined as tRCD, i.e., RAS to CAS Delay (RAS to CAS Delay, RAS being row address strobe, CAS being column address strobe), according to the relevant criteria, we can understand the row strobe period. tRCD is an important timing parameter of DDR, and a generalized tRCD is expressed in terms of the number of Clock cycles (tCK, clock Time), for example trcd=3, which represents a delay period of two Clock cycles, specifically to an exact Time, and DDR3-800, trcd=3, which represents a delay of 30ns, depending on the Clock frequency. The data transfer is then triggered after the associated column address is selected.

After the upper computer is started, the pattern data are sequentially sent to the main FPGA chip through the PCIE interface of the main FPGA chip and stored in the DDR address space of the main FPGA chip, or are transmitted to the DDR address space of the corresponding slave FPGA chip, and the upper computer records the DDR address stored in each row of pattern data. The DDR address occupies very little memory, we define the DDR address corresponding to each row pattern in the upper computer, and the DDR address is stored in the upper computer.

When the chip is subjected to burn-in test, matched burn-in software in the upper computer is operated, and in the burn-in software, hardware actions when the pattern to be tested is sent are defined as: the upper computer sends out a starting instruction- > starting each logic- > of the main FPGA, the upper computer starts DDR addressing- > reading corresponding pattern data, namely, the pattern data is obtained from the corresponding address of the corresponding DDR, and the pattern data is transmitted to the main FPGA chip. If the address 0x1 is addressed, data is acquired from the address 0x1 corresponding to the DDR and transmitted through an internal bus, wherein corresponding data in the data are selectively transmitted to a transmitting logic or a vector judging logic according to pattern data, wherein the data of 0 and 1 are transmitted to a data transmitting logic, the data transmitting logic automatically throws waveforms (namely test waveforms, 0 represents low level and 1 represents high level) corresponding to the 0 and 1 data to IO (namely ports connected with chips to be tested) when receiving the 0 and 1 data, and meanwhile, the defined waveforms are stored in a data analyzing logic and a time sequence generating logic when the transmitted and received waveforms store the data to the DDR at an upper computer; converting L, H and X data into judgment waveforms; the data L is converted into low level, the data H is converted into high level, and the data X represents that the output waveforms are not compared; the judging waveform is transmitted to the vector judging logic, which is simply a comparator, the signal sent by the chip to be tested to the main FPGA is used as the input of the comparison end, the input of the comparison end at the other end is the waveform of the current period (namely the judging waveform converted by L, H and X data) obtained from DDR addressing, the output of the comparator is given to the result judging logic to judge whether the signal received in the period is the expected signal or not, so that the test result is output, and all the logic related to the signal share one clock.

The processing rule of the pattern data can be stored in a specific address range through the upper computer when the pattern data is stored, so that the chip to be tested can be conveniently tested according to the processing rule when the test is carried out later.

In order to expand the memory size of the pattern, a master fpga+a core system of multiple slave FPGAs is designed. As shown in fig. 6, the pattern data in the main FPGA is routed to the AXI bus, the other control data is routed to the APB bus, a control module circuit (i.e., the above-mentioned logic test module) is built by designing a protocol of a custom chip, and a GTH high-speed interface of the FPGA itself is used as a high-speed data transmission interface between FPGAs for transmitting pattern data. The two FPGAs are connected through the I2C and used for interaction and negotiation and for transmission of control data, so that the upper computer can access the master FPGA through the PCIE and then indirectly access the slave FPGA through the I2C. The slave FPGA chip 2 and the slave FPGA chip 1 are connected in a multiplexing mode, namely the slave FPGA chip 1 and the master FPGA are sequentially cascaded with a plurality of FPGAs, so that the pattern data can be sequentially stored in the storage logic of the plurality of FPGAs and can be called in real time. It should be noted here that, for the sake of clarity of the drawings, the corresponding intermediate FPGA chips, such as the slave FPGA chip 2 and the slave FPGA chip 3, are not shown in fig. 6 and 7, but are replaced by ellipses, which do not represent the absence of these intermediate FPGA chips.

Before the aging test of the chip is carried out, the pattern file output by EDA software and the corresponding time sequence file are loaded into the main FPGA from the upper computer; the control logic of the main FPGA controls the data analysis logic to analyze the pattern file, 8 continuous waveforms are stored into the storage logic DDR0 in a mode of 1 Byte, and DDR storage addresses corresponding to each row of pattern are recorded; taking 128 channels as an example, DDR0 selects 32G capacity, and removes 8G required by the system and other logic modules, the size of pattern storable by DDR0 is (32-8) x 1024/128/8=24m; the part of the Pattern larger than 24M is controlled by the control logic of the upper computer, is transmitted to the SerDes interface through the internal data bus of the main FPGA, is input to the data bus of the slave FPGA chip 1 through the first group of SerDes interfaces (namely the first serial interfaces) of the slave FPGA chip 1, and is stored in the storage logic DDR1 to form a chiplet unit; the control logic required by each slave FPGA is directly generated by the master FPGA, other circuits are not needed, the storage logic DDR1 of the slave FPGA chip 1 only needs to provide 2G for the addressing logic of the slave FPGA chip 1, and the rest 30G can be used for storing patterns. The master FPGA together with the slave FPGA chip 1 can provide a total of 54M pattern capacity.

The second group of SerDes interfaces (namely the second serial interface) of the slave FPGA chip 1 is connected with the first group of SerDes interfaces (namely the first serial interface) of the slave FPGA chip 2, and the like, the first stage is connected downwards from stage to stage, so that multi-stage capacity expansion can be realized, each stage can provide 30M pattern capacity, the 6-stage capacity expansion can realize 204M pattern capacity, and the number of slave FPGA chips in specific cascade connection is obtained by analysis according to the test requirement of chips by a person skilled in the art.

When the chip test is carried out, the control logic of the upper computer reads the pattern data by storing DDR addresses corresponding to each row of pattern when the pattern is stored, reads the data according to the sequence of the pattern rows, stores the data into a buffer of the data sending logic and the vector judging logic, and automatically updates the data in the buffer by 1 row after the data sending logic finishes sending 1 row of pattern until all the patterns are sent out.

When all the patterns of the storage logic DDR0 of the main FPGA are read, and the buffer is waiting to be sent out, the control logic starts to access the storage logic DDR1 of the slave FPGA chip 1 according to the DDR address, and reads the data into the buffer of the main FPGA through the data bus and the chip; the data transmission logic of each subsequent cascade slave FPGA and the slave FPGA chip 1 are realized based on the same concept, and are not described here in detail.

Wherein, each DDR is designed as DDR4 3200M, and the maximum transmission bandwidth is 25.6GB/s; the SerDes interface of chiplet is designed to be 16 channels (Lane), each Lane is 16GT/s, the coding mode is 128b/130b, and the maximum throughput is 31.508GB/s; the throughput of the chiplet is larger than the maximum transmission bandwidth of the DDR, the external transmission rate of the pattern is 10Mbps, and the data can be transmitted from the FPGA to the data transmission logic of the main FPGA at the highest speed, so that the problem that the following pattern in the buffer is not connected after the pattern is already sent out is avoided.

It should be noted that, because the content of information interaction and execution process between modules and units in the above-mentioned device and system is based on the same concept as the processing method embodiment of the present invention, specific content may be referred to the description in the method embodiment of the present invention, and will not be repeated here.

Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the embodiments may be implemented by a program that instructs associated hardware, the program may be stored on a computer readable storage medium, the storage medium may include: read Only Memory (ROM), random access Memory (RAM, random Access Memory), magnetic or optical disk, and the like.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (10)

1. The FPGA chip supporting transparent transmission is characterized by comprising a first serial interface, a first control module, a second control module and a second serial interface;

the first serial interface is connected with the first control module, the first control module is connected with the second control module, and the second control module is connected with the second serial interface;

the first control module is used for being connected with a corresponding control module of the upper-level FPGA chip to form an uplink control data transmission channel; the second control module is used for being connected with a corresponding control module of the lower-level FPGA chip to form a downlink control data transmission channel; the transparent transmission of the read command and/or the write command is realized through the uplink control data transmission channel and the downlink control data transmission channel;

the first serial interface is used for being connected with a corresponding serial interface of the upper FPGA chip to form an upper-level read-write data transmission channel; the second serial interface is used for being connected with a corresponding serial interface of the lower-level FPGA chip to form a lower-level read-write data transmission channel; and through the upper read-write data transmission channel and the lower read-write data transmission channel, the transparent transmission of read data and/or write data is realized.

2. The FPGA chip supporting transparent transmission according to claim 1, wherein the first control module is connected to the second control module through an AXI bus and an APB bus, the AXI bus is used for forming an intermediate read/write data transmission channel, and the APB bus is used for forming an intermediate control data transmission channel.

3. A permeant method using the FPGA chip supporting permeant of claim 1 or claim 2, the method comprising:

the first control module acquires a Bank address carried in a read command or a write command according to the read command or the write command issued by the upper FPGA chip;

addressing a memory connected with the FPGA chip according to the Bank address, if the addressing results in that the Bank address does not belong to the memory, transmitting the read command or the write command to a second control module, and transmitting the read command or the write command to a subordinate FPGA chip through a downlink control data transmission channel by the second control module;

if the addressing results in that the Bank address belongs to the memory, finding out a corresponding target address in the memory according to the read command or the write command, and performing read operation or write operation on the target address.

4. A permeance method according to claim 3, further comprising:

the second serial interface receives the read data from the lower FPGA chip through the lower read-write data transmission channel, the read data is transmitted to the second control module, the second control module transmits the read data to the first control module, the first control module transmits the read data to the first serial interface, and the first serial interface transmits the read data to the upper FPGA chip through the upper read-write data transmission channel.

5. The transparent transmission method according to claim 3, wherein a chip mark number is preset in an FPGA chip, and the chip mark number is carried in a Bank address of the read command or the write command;

addressing the memory connected with the FPGA chip according to the Bank address includes:

judging whether the chip mark number carried in the read command or the write command is consistent with the chip mark number of the memory, if so, addressing to obtain the Bank address belongs to the memory, otherwise, addressing to obtain the Bank address does not belong to the memory.

6. The transparent transmission method according to any one of claims 3 to 5, wherein the read command includes a Bank address, a row address, and a column address, and the write command includes a Bank address, a row address, and a column address.

7. A logic test module, comprising a master FPGA chip, a plurality of slave FPGA chips and a plurality of memories, wherein the master FPGA chip and the plurality of slave FPGA chips are sequentially cascaded, each FPGA chip is connected with a corresponding memory, the slave FPGA chips positioned in the middle of the cascade relationship are used as intermediate FPGA chips based on the cascade relationship, each intermediate FPGA chip is the FPGA chip supporting transparent transmission according to claim 1 or 2, and each intermediate FPGA chip performs the transparent transmission method according to any one of claims 3 to 6;

the serial interface of the master FPGA chip is connected with the first serial interface of the first slave FPGA chip, and the control module of the master FPGA chip is connected with the first control module of the first slave FPGA chip;

in each intermediate FPGA chip, a second serial interface of the upper-stage FPGA chip is connected with a first serial interface of the lower-stage FPGA chip, and a second control module of the upper-stage FPGA chip is connected with a first control module of the lower-stage FPGA chip;

the second serial interface of the last intermediate FPGA chip is connected with the serial interface of the last slave FPGA chip, and the second control module of the last intermediate FPGA chip is connected with the first control module of the last slave FPGA chip.

8. The logic test module of claim 7, wherein the main FPGA chip comprises a PCIE interface, a control module, and a serial interface;

the control module is connected with the serial interface, and the PCIE interface is connected with the control module;

the PCIE interface is used for being connected with the upper computer so as to receive a read command or a write command from the upper computer or return a test result to the upper computer;

and the control module is used for carrying out read operation or write operation on the corresponding memory according to the read command or the write command, or transmitting the read command or the write command to the first slave FPGA chip.

9. A logic test method, characterized in that the logic test module according to claim 7 or 8 is used, the method comprising:

before testing, the main FPGA chip receives a write command from an upper computer, and performs write operation on a memory of the main FPGA chip or performs write operation on a memory of a corresponding slave FPGA chip according to the write command so as to write each test vector into the main FPGA chip or the slave FPGA chip, and returns a corresponding memory address to the upper computer, so that the upper computer can generate a corresponding read command according to each memory address during testing;

When testing is carried out, the main FPGA chip receives a read command from an upper computer, and corresponding test vectors are read from a memory of the main FPGA chip or a memory of the FPGA chip according to the read command; and testing the chip to be tested according to the test vector to obtain a test result, and transmitting the test result to an upper computer.

10. The logic testing method according to claim 9, wherein the testing the chip under test according to the test vector, to obtain a test result comprises:

generating a test waveform and a judgment waveform according to the test vector, and sending the test waveform to a test vector input end of a chip to be tested;

receiving an output waveform from a chip to be tested, and comparing the output waveform with the judging waveform to obtain a test result; wherein data 0 and data 1 are converted into test waveforms; data 0 transitions to a low level and data 1 transitions to a high level; converting the data L, the data H and the data X into judging waveforms; the data L is switched to low level and the data H is switched to high level, the data X representing that the output waveforms are not compared.

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