CN202034899U - Double-pipe parallel connection power factor correction (PFC) circuit - Google Patents
Double-pipe parallel connection power factor correction (PFC) circuit Download PDFInfo
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- CN202034899U CN202034899U CN2011200596331U CN201120059633U CN202034899U CN 202034899 U CN202034899 U CN 202034899U CN 2011200596331 U CN2011200596331 U CN 2011200596331U CN 201120059633 U CN201120059633 U CN 201120059633U CN 202034899 U CN202034899 U CN 202034899U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model relates to the field of a power supply, in particular to a double-pipe parallel connection power factor correction (PFC) circuit, which comprises a control chip, a first switch tube, a second switch tube, a first N-channel metal oxide semiconductor (NMOS) tube, a second NMOS tube and two diodes in reverse parallel connection, the first switch tube and the second switch tube are connected with the control chip and outputs square wave signals to grid electrodes of first NMOS tube and the second NMOS tube under the control of the control chip, grid electrodes of the first NMOS tube and the second NMOS tube are connected through the two diodes in reverse parallel connection, source electrodes of the first NMOS tube and the second NMOS tube are grounded, and drain electrodes of the first NMOS tube and the second NMOS tube are used as circuit output ends. When the grid electrode and the source electrode of the first NMOS tube are in a short circuit state or when the grid electrode and the source electrode of the second NMOS tube are in a short circuit state, the other NMOS tube is always conducted and can not normally work because of the position clamping of the two diodes in reverse parallel connection, and the problem of too high work temperature of the single tube is solved.
Description
Technical field
The utility model relates to field of power supplies, particularly a kind of two-tube parallel PFC circuit.
Background technology
At present, in high-power PFC (Power Factor Control, the power factor controlling) circuit that television set uses, the PFC of the single MOSFET driving power that boosts is limited, can't satisfy powerful demand, and this just need drive with two MOSFET, the raising power output.
As shown in Figure 1, be the pfc circuit figure that the two metal-oxide-semiconductors of prior art drive.This pfc circuit comprises power end Vcc, PNP triode Q1 ', NPN triode Q2 ' and two metal-oxide-semiconductor W1 and W2.The collector electrode of NPN triode Q2 ' is connected to power end Vcc, and base stage is connected to the control pin of external chip, receives the control signal of external chip, and emitter connects the emitter of PNP triode Q1 ' and the G utmost point of metal-oxide-semiconductor W1 and W2 respectively; The base stage of the base stage of PNP triode Q1 ' and NPN triode Q2 ' is connected to the control pin of same external control chip, thereby receives identical control signal simultaneously with NPN triode Q2 ', the grounded collector of PNP triode Q1 '.Like this, PNP triode Q1 ', NPN triode Q2 ' externally is in the alternate conduction state under the chip controls, thus output drives square wave to metal-oxide-semiconductor W1 and W2, drives two metal-oxide-semiconductors and is in conducting and cut-off state simultaneously.
When the pfc circuit that utilizes above-mentioned pair of metal-oxide-semiconductor to drive is done the short trouble experiment, with the G utmost point among metal-oxide-semiconductor W1 or the metal-oxide-semiconductor W2 and S utmost point short circuit, make single metal-oxide-semiconductor lose driving force, and another metal-oxide-semiconductor operate as normal still, this pfc circuit then provides the entire circuit power demand by a metal-oxide-semiconductor, this just causes single metal-oxide-semiconductor temperature of work too high, burns entire circuit easily, can't satisfy the safety requirement.
Summary of the invention
The purpose of this utility model is to provide a kind of two-tube parallel PFC circuit, is intended to solve when single metal-oxide-semiconductor is worked in the prior art, and temperature is too high, burns the problem of entire circuit easily.
The present invention realizes like this, a kind of two-tube parallel PFC circuit, this circuit comprises control chip, first switching tube, the second switch pipe, NMOS pipe, two diodes of the 2nd NMOS pipe and reverse parallel connection, first switching tube links to each other with control chip with the second switch pipe, the grid of output square-wave signal to the NMOS pipe and the 2nd NMOS pipe under control chip control; The grid of the one NMOS pipe and the 2nd NMOS pipe links to each other by two diodes of reverse parallel connection; The source ground of the one NMOS pipe and the 2nd NMOS pipe; The drain electrode of the one NMOS pipe and the 2nd NMOS pipe is as circuit output end.
Two diodes of this reverse parallel connection comprise first diode and second diode, and first diode cathode is connected to second diode cathode; First diode cathode is connected to second diode cathode.
This circuit also comprises the 3rd resistance, and the source electrode of NMOS pipe and the 2nd NMOS pipe is by the 3rd grounding through resistance.
In this circuit, first switching tube is the PNP triode, and this second switch pipe is the NPN triode.
This pfc circuit also comprises power end, and this control chip comprises the control pin of exporting control signal, and this control pin is connected to the base stage of this PNP triode and this NPN triode; The collector electrode of this NPN triode is connected to power end, and its emitter links to each other with the emitter of this PNP triode; The grounded collector of this PNP triode.
This circuit also comprises first resistance and second resistance, and the collector electrode of this NPN triode is connected to power end by first resistance; This control pin is connected to the base stage of this PNP triode and this NPN triode by this second resistance.
This circuit also comprises the 6th resistance, the 7th resistance and the 3rd diode, the emitter that the grid of the one NMOS pipe is connected to this PNP triode and this NPN triode through the 7th resistance and the 6th resistance of series connection successively, the 7th resistance is in parallel with the 3rd diode, and the 3rd diode cathode links to each other with a NMOS tube grid.
This circuit also comprises the 4th resistance, the 5th resistance and the 4th diode, the emitter that the grid of the 2nd NMOS pipe is connected to this PNP triode and this NPN triode through the 5th resistance and the 4th resistance of series connection successively; The 5th resistance is in parallel with the 4th diode, and the 4th diode cathode links to each other with the 2nd NMOS tube grid.
When the grid of short circuit the one NMOS pipe and source electrode or when the grid of short circuit the 2nd NMOS pipe and source electrode, another NMOS pipe is by the clamper of the first diode D1 and the 4th diode D2, the too high problem of easily burning circuit of single tube working temperature has been avoided in conducting always and can't operate as normal.
Description of drawings
Fig. 1 is the pfc circuit figure that the two metal-oxide-semiconductors of prior art drive;
Fig. 2 is the circuit diagram of the two-tube parallel PFC circuit of the utility model.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
As shown in Figure 2, be the circuit diagram of the two-tube parallel PFC circuit of the utility model.This circuit comprises power end PFC_Vcc, control chip U1, first resistance R 5, second resistance R, 6, the three resistance R, 10, the four resistance R 8, the 5th resistance R 9, the six resistance R 11, the seven resistance R 12, the first triode Q1, the second triode Q2, the first diode D1, the second diode D2, the 3rd diode D3 and the 4th diode D4, a NMOS manages QW1, and the 2nd NMOS manages QW2; Wherein, this first triode Q1 is the PNP triode; The second triode Q2 is the NPN triode.
Control chip U1 comprises a control pin DRV, and this control pin DRV is connected to the base stage of this first triode Q1 and the second triode Q2 by this second resistance R 6, exports control signal to this first triode Q1 and the second triode Q2; The collector electrode of the second triode Q2 is connected to power end PFC_Vcc by this first resistance R 5, and its emitter links to each other with the emitter of this first triode Q1; The grounded collector of this first triode Q1.
The emitter that the grid of the one NMOS pipe QW1 is connected to the second triode Q2 and this first triode Q1 through the 7th resistance R 12 and the 6th resistance R 11 of series connection successively; Wherein, the 7th resistance R 12 is in parallel with the 3rd diode D3, and the 3rd diode D3 positive pole links to each other with NMOS pipe QW1 grid; The source electrode of the one NMOS pipe QW1 is through the 3rd resistance R 10 ground connection, and drain electrode is as output.
The emitter that the grid of the 2nd NMOS pipe QW2 is connected to the second triode Q2 and this first triode Q1 through the 5th resistance R 9 and the 4th resistance R 8 of series connection successively; Wherein, the 5th resistance R 9 is in parallel with the 4th diode D4, and the 4th diode D4 positive pole links to each other with the 2nd NMOS pipe QW2 grid; The source electrode of the 2nd NMOS pipe QW2 is through the 3rd resistance R 10 ground connection, and drain electrode is as output.
This first diode D1 is connected with the second diode D2 reverse parallel connection, and promptly this first diode D1 is anodal links to each other with the second diode D2 negative pole, and this first diode D1 negative pole links to each other with the second diode D2 is anodal.
The grid of the grid of the one NMOS pipe QW1 and the 2nd NMOS pipe QW2 links to each other with the second diode D2 by the first diode D1 of reverse parallel connection.
When control chip U1 exports high-level control signal to this first triode Q1 and this second triode Q2 by control pin DRV, the second triode Q2 conducting, and the first triode Q1 ends, and power end PFC-Vcc manages the grid of QW1 and the grid of the 2nd NMOS pipe QW2 by this second triode Q2 output high level to a NMOS; When control chip U1 controls signal to the second triode Q2 and this first triode Q1 by control pin DRV output low level, the second triode Q2 ends, and the first triode Q1 conducting, the emitter output low level of the second triode Q2 and this first triode Q1 is to the grid of NMOS pipe QW1 and the grid of the 2nd NMOS pipe QW2.Like this, the grid of the second triode Q2 and this first triode Q1 output square wave to the NMOS pipe QW1 under control chip U1 control and the grid of the 2nd NMOS pipe QW2.Under the high level situation, NMOS pipe QW1 and the 2nd NMOS pipe QW2 by; Under the low level situation, NMOS pipe QW1 and the 2nd NMOS pipe QW2 conducting, thus finish power factor controlling.
When doing the short trouble experiment, grid and the source electrode of short circuit the one NMOS pipe QW1, though the 2nd NMOS pipe QW2 is driven by control pin DRV output control by control chip, but clamper by the first diode D1 and the second diode D2, make the grid voltage of the 2nd NMOS pipe QW2 be lower than 0.6V, thus, the 2nd NMOS pipe QW2 is in conducting state always, thereby the driving force of losing can't operate as normal.Like this, avoided among NMOS pipe QW1 or the 2nd NMOS pipe QW2 one when grid and the source electrode short circuit, another NMOS pipe works independently and makes the too high problem of burning circuit easily of temperature, has guaranteed the fail safe of entire circuit.
In addition, in this two-tube parallel PFC circuit, the first triode Q1 is not limited only to adopt the PNP triode, second triode is not limited to adopt the NPN triode, adopt other switch elements,, for example utilize the NMOS pipe to replace the first triode Q1 as long as externally exporting square wave under the chip controls, utilize the PMOS pipe to replace the second triode Q2, can reach same purpose.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (8)
1. two-tube parallel PFC circuit, it is characterized in that, this circuit comprises control chip, first switching tube, the second switch pipe, NMOS pipe, two diodes of the 2nd NMOS pipe and reverse parallel connection, first switching tube links to each other with control chip with the second switch pipe, the grid of output square-wave signal to the NMOS pipe and the 2nd NMOS pipe under control chip control; The grid of the one NMOS pipe and the 2nd NMOS pipe links to each other by two diodes of reverse parallel connection; The source ground of the one NMOS pipe and the 2nd NMOS pipe; The drain electrode of the one NMOS pipe and the 2nd NMOS pipe is as circuit output end.
2. two-tube parallel PFC circuit according to claim 1 is characterized in that, two diodes of reverse parallel connection comprise first diode and second diode, and first diode cathode is connected to second diode cathode; First diode cathode is connected to second diode cathode.
3. two-tube parallel PFC circuit according to claim 1 is characterized in that this circuit comprises the 3rd resistance, and the source electrode of NMOS pipe and the 2nd NMOS pipe is by the 3rd grounding through resistance.
4. two-tube parallel PFC circuit according to claim 1 is characterized in that this first switching tube is the PNP triode, and this second switch pipe is the NPN triode.
5. two-tube parallel PFC circuit according to claim 4 is characterized in that this pfc circuit also comprises power end, and this control chip comprises the control pin of exporting control signal, and this control pin is connected to the base stage of this PNP triode and this NPN triode; The collector electrode of this NPN triode is connected to power end, and its emitter links to each other with the emitter of this PNP triode; The grounded collector of this PNP triode.
6. two-tube parallel PFC circuit according to claim 5 is characterized in that this circuit comprises first resistance and second resistance, and the collector electrode of this NPN triode is connected to power end by first resistance; This control pin is connected to the base stage of this PNP triode and this NPN triode by this second resistance.
7. two-tube parallel PFC circuit according to claim 6, it is characterized in that, this circuit comprises the 6th resistance, the 7th resistance and the 3rd diode, the emitter that the grid of the one NMOS pipe is connected to this PNP triode and this NPN triode through the 7th resistance and the 6th resistance of series connection successively, the 7th resistance is in parallel with the 3rd diode, and the 3rd diode cathode links to each other with a NMOS tube grid.
8. two-tube parallel PFC circuit according to claim 6, it is characterized in that, this circuit comprises the 4th resistance, the 5th resistance and the 4th diode, the emitter that the grid of the 2nd NMOS pipe is connected to this PNP triode and this NPN triode through the 5th resistance and the 4th resistance of series connection successively; The 5th resistance is in parallel with the 4th diode, and the 4th diode cathode links to each other with the 2nd NMOS tube grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200596331U CN202034899U (en) | 2011-03-09 | 2011-03-09 | Double-pipe parallel connection power factor correction (PFC) circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200596331U CN202034899U (en) | 2011-03-09 | 2011-03-09 | Double-pipe parallel connection power factor correction (PFC) circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202034899U true CN202034899U (en) | 2011-11-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011200596331U Expired - Lifetime CN202034899U (en) | 2011-03-09 | 2011-03-09 | Double-pipe parallel connection power factor correction (PFC) circuit |
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| CN (1) | CN202034899U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103687259B (en) * | 2012-09-07 | 2015-12-30 | 神讯电脑(昆山)有限公司 | The protection circuit of inverter that fluorescent tube comes off |
-
2011
- 2011-03-09 CN CN2011200596331U patent/CN202034899U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103687259B (en) * | 2012-09-07 | 2015-12-30 | 神讯电脑(昆山)有限公司 | The protection circuit of inverter that fluorescent tube comes off |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20111109 |