CN202014319U - Rear grade chattering-free correcting device of DVI/HDMI/DP/VGA signal - Google Patents

Abstract

The utility model discloses a rear grade chattering-free correcting device of a DVI/HDMI/DP/VGA signal. The device is characterized in that a signal acquisition unit is connected with a core processing unit I via a data line; a clock simulation unit is connected with the core processing unit I via the data line; the core processing unit I is connected with an external storage unit via the data line; the core processing unit I is connected with a core processing unit II via an external data line; the core processing unit II is connected with the external storage unit via the data line; the core processing unit II is connected with a signal output unit so as to send a standard excitation clock CLKPLL, a line signal H2, a field signal V2, and RGB data read from the external storage unit to the signal output unit, and then the signal output unit processes and outputs the above data to an external device. The system can eliminate the unfavorable effects, such as a black screen or a colored screen caused by signal switching, thus making the playing more fluent.

Description

A kind of back level nothing of DVI/HDMI/DP/VGA signal is trembled means for correcting

Technical field

The utility model relates to a kind of back level nothing of DVI/HDMI/DP/VGA signal and trembles means for correcting.

Background technology

In recent years, along with the continuous development of digital video technology, DVI (Digital Video Interface) vision signal and HDMI (High Definition Multimedia Interface) the occupied in actual applications ratio of vision signal also continues to increase.The DVI/HDMI signal belongs to digital video signal, but because it does not have the SAV (initial signal) and the EAV (end signal) of strict similar sdi signal, so can't detect losing or interrupting of signal by the data analysis means are instantaneous as the SDI digital signal, and DVI/HDMI signal image transmitted resolution height, transmission rate uses traditional video processing technique to carry out accurately handling in real time to it up to 1.65Gbps even 2.25Gbps.Therefore more thorny always at the DVI/HDMI Signal Processing, wherein the nothing of DVI/HDMI signal is trembled and is switched a difficult problem that needs to be resolved hurrily in the industry especially.In the actual environment for use, when being switched, the DVI/HDMI/DP/VGA signal can cause 2-10 blank screen or the blue screen of second, have a strong impact on viewing effect, especially in extensive surveillance that needs such as large-screen, multi-screen frequently switch signal or video conference, more make the people be difficult to stand.

Summary of the invention

The utility model is at the proposition of above problem, and the back level of developing a kind of DVI/HDMI/DP/VGA signal does not have and trembles means for correcting.The technological means that the utility model adopts is as follows:

A kind of back level nothing of DVI/HDMI/DP/VGA signal is trembled means for correcting, it is characterized in that comprising: signal gathering unit, core processing unit I, clock analogue unit, external memory unit, core processing unit II and signal output unit; Described signal gathering unit is connected with core processing unit I by data wire, signal gathering unit will collect the DVI/HDMI signal or the VGA signal processing after send among the core processing unit I, described clock analogue unit is connected with core processing unit I by data wire, and described core processing unit I is connected with the external memory unit by data wire; Described core processing unit I is connected by the external data line with core processing unit II, described core processing unit II is connected with the external memory unit by data wire, described core processing unit II is connected with signal output unit, capable signal H2 and field signal V2 that pattern field clock CLKPLL, the core processing unit I that the external data line is received generates, and the RGB data that read from the external memory unit send to the signal output unit, and described signal output unit is exported to external equipment after to above-mentioned data processing.

Described external memory unit is divided into two zones, and described core processing unit I is connected with two zones of external memory unit respectively by data wire; Described core processing unit II also is connected with two zones of external memory unit respectively by data wire.

Described signal gathering unit can be made of chip SIL1161 or TDA19977, TDA19978, AD998x, ADV7441 chip; Described clock analogue unit can be made of the PLL602 chip; Described external memory unit is by DDRIII, and DDRII, SDRAM or AL460 chip constitute; The master chip of described core processing unit I and core processing unit II is made of cycloneII or EasyPath-6FPGA chip.Comprise that also MCU becomes core processing unit I to be connected with the fpga chip of core processing unit II by the data wire isomorphism.

Core processing unit I described in the utility model inside comprises the signal format of 800x600 to the multiple resolution of 1920x1200, can accurately judge the resolution standard of input signal, and be used for generating the excitation clock according to corresponding with it H1 pulse of corresponding resolution standard oneself generation and V1 pulse signal.Simulate the excitation clock of signal at the clock analogue unit after, core processing unit I can generate a H2/V2 signal according to signal excitation clock that simulates and the standard signal that collects, when input signal was lost, core processing unit I can export the H2/V2 signal equally continuously.Also can adjust and revise the output picture according to the H2/V2 signal in core processing unit II, can add captions or other sign as required in display frame, make the mode of operation of this system simpler, operating process is more blunt to be understood.On the basis of this method, multichannel DVI/HDMI or VGA input module are being set, and, then can making the utility model independently finish handoff functionality, and realizing that nothing trembles the switching effect at the integrated handover module of level thereafter.

The beneficial effects of the utility model are: can DVI/HDMI digital video signal and VGA signal not had the hand-off process of trembling, when switching with conversion process to DVI/HDMI signal or VGA signal, ill effects such as blank screen that the erasure signal switching produces or Hua Ping, it is smooth more that it is broadcasted.When dropout, also can allow terminal show a picture with information content, rather than skimble-skamble blank screen or blue screen, the time of having eliminated display terminal identification simultaneously and having recovered image.

Description of drawings

Fig. 1 is an apparatus structure block diagram of the present utility model;

Fig. 2 uses the designed example structure block diagram of the utility model.

Embodiment

The back level nothing of a kind of DVI/HDMI/DP/VGA signal is as depicted in figs. 1 and 2 trembled means for correcting and is comprised: signal gathering unit, core processing unit I, clock analogue unit, external memory unit, core processing unit II and signal output unit; Described signal gathering unit is connected with core processing unit I by data wire, signal gathering unit will collect the DVI/HDMI signal or the VGA signal processing (promptly and the line output rgb signal, signal excitation clock CLK, row signal H and field signal V) after send among the core processing unit I, described clock analogue unit is connected with core processing unit I by data wire, and (core processing unit I is according to the signal excitation clock CLK that collects, row signal H and field signal V judge the resolution of input signal, generate the capable signal H1 and the field signal V1 of a same frequency then, output to the clock analogue unit), described core processing unit I by data wire with external memory unit be connected (core processing unit I writes rgb signal according to the outside memory cell of signal excitation clock CLK); Described core processing unit I and core processing unit II are by external data line be connected (and by external channel directly be sent in core processing unit II capable signal H2 and the field signal V2 that the pattern field clock CLKPLL and the core processing unit I of clock analogue unit output produces), described core processing unit II is connected with the external memory unit by data wire, described core processing unit II is connected with signal output unit, the pattern field clock CLKPLL that the external data line is received, capable signal H2 and field signal V2 that core processing unit I generates, and the RGB data that read from the external memory unit send to the signal output unit, and described signal output unit is exported to external equipment after to above-mentioned data processing.Described external memory unit is divided into two zones, and described core processing unit I is connected with two zones of external memory unit respectively by data wire; Described core processing unit II also is connected with two zones of external memory unit respectively by data wire.

Signal gathering unit can be made of chip SIL1161 or TDA19977, TDA19978, chips such as AD998x, ADV7441 as shown in Figure 2; The clock analogue unit can be made of the PLL602 family chip; The external memory unit can be by DDRIII, and chips such as DDRII, SDRAM or AL460 constitute; The master chip of core processing unit I and core processing unit II can be made of the cycloneII of ALTERA company or the EasyPath-6FPGA family chip FPGA1 and the FPGA2 of XIlinx company; In addition, also comprise the MCU that cooperates FPGA1 and FPGA2 to carry out work, the DVI/HDMI signal that analyzes input or the resolution format of VGA signal have been finished, so that FPGA1 makes the capable signal H1 and the field signal V1 of a same frequency according to this resolution, FPGA2 can judge the degree of depth of memory space in the storage area according to the relevant parameter of the resolution format of signal, MCU is according to the relevant information of the resolution format that reads, analyzing concrete resolution format is what, and the pattern field clock CLKPLL that control clock analog chip is exported this resolution format signal delivers to FPGA1, and obtain core processing unit I judge input signal whether occur interrupt and wrong result gives core processing unit II (core processing unit II can select read the memory space of external memory unit by the result of determination of core processing unit I), to realize the function of aforesaid core processing unit I and core processing unit II; Can certainly finish by two independent CPUs.Present embodiment adopts FPGA and MCU fit structure, and wherein MCU also is used to the resolution format that analyzes the front and back level chip of system is carried out the initialization setting.What other peripheral chip such as FLASH used is the SST39VF1601 chip, and signal output unit can be that SIL162, SIL164, TDA998X, AD9889 chip constitute by chip.Wherein MCU changes the display effect that core processing unit II goes up monitor portion, can be by RS232 and the interconnected debugging of PC.

The above; it only is the preferable embodiment of the utility model; but protection range of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; be equal to replacement or change according to the technical solution of the utility model and inventive concept thereof, all should be encompassed within the protection range of the present utility model.

Claims (4)

1. the back level nothing of a DVI/HDMI/DP/VGA signal is trembled means for correcting, it is characterized in that comprising: signal gathering unit, core processing unit I, clock analogue unit, external memory unit, core processing unit II and signal output unit; Described signal gathering unit is connected with core processing unit I by data wire, signal gathering unit will collect the DVI/HDMI signal or the VGA signal processing after send among the core processing unit I, described clock analogue unit is connected with core processing unit I by data wire, and described core processing unit I is connected with the external memory unit by data wire; Described core processing unit I is connected by the external data line with core processing unit II, described core processing unit II is connected with the external memory unit by data wire, described core processing unit II is connected with signal output unit, capable signal H2 and field signal V2 that pattern field clock CLKPLL, the core processing unit I that the external data line is received generates, and the RGB data that read from the external memory unit send to the signal output unit, and described signal output unit is exported to external equipment after to above-mentioned data processing.

2. the back level nothing of a kind of DVI/HDMI/DP/VGA signal according to claim 1 is trembled means for correcting, it is characterized in that described external memory unit is divided into two zones, described core processing unit I is connected with two zones of external memory unit respectively by data wire; Described core processing unit II also is connected with two zones of external memory unit respectively by data wire.

3. the back level of a kind of DVI/HDMI/DP/VGA signal according to claim 1 does not have and trembles means for correcting, it is characterized in that described signal gathering unit can be made of chip SIL1161 or TDA19977, TDA19978, AD998x, ADV7441 chip; Described clock analogue unit can be made of the PLL602 chip; Described external memory unit is by DDRIII, and DDRII, SDRAM or AL460 chip constitute; The master chip of described core processing unit I and core processing unit II is made of cycloneII or EasyPath-6FPGA chip.

4. the back level nothing of a kind of DVI/HDMI/DP/VGA signal according to claim 3 is trembled means for correcting, it is characterized in that also comprising that MCU becomes core processing unit I to be connected with the fpga chip of core processing unit II by the data wire isomorphism.

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