CN201965239U - Overlay switch circuit of high-resolution petroleum seismic exploration system - Google Patents
Overlay switch circuit of high-resolution petroleum seismic exploration system Download PDFInfo
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- CN201965239U CN201965239U CN2010206695444U CN201020669544U CN201965239U CN 201965239 U CN201965239 U CN 201965239U CN 2010206695444 U CN2010206695444 U CN 2010206695444U CN 201020669544 U CN201020669544 U CN 201020669544U CN 201965239 U CN201965239 U CN 201965239U
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Abstract
The utility model belongs to a petroleum seismic exploration instrument, in particular relates to an overlay switch circuit of a high-resolution petroleum seismic exploration system, which is characterized in that the overlay switch circuit adopts ADG (advanced data guarding) 734 to form a switch array, the chip selection end of each ADG734 in the array is electrically connected with a computer bus, eight ADG734 are fixed on a data acquisition board, a processor is used for selecting level at the chip selection ends of the eight ADG734 according to the command of a PC104 plus embedded industrial personal computer, and a selected seismic detector is connected to a corresponding front amplifying circuit; and the detector converts a vibration signal into an analog electric signal, and is connected with the input end of the overlay switch circuit by a jug line. The utility model provides an overlay switch circuit of the high-resolution petroleum seismic exploration system, which has multiple channels, high resolution, low power consumption, high reliability and is provided with a built-in electronic overlay switch.
Description
Technical field
The utility model belongs to the oil seismic exploration instrument, the covering on-off circuit of particularly a kind of high resolving power oil seismic exploration system.
Background technology
The seismic prospecting instrument be in the seismic prospecting with secondary reflection or with other vibroseis earthquake-wave-excitings, and write down the instrument of the vibration displacement that it causes on ground.By analyzing the propagation law of seismic event in rock, determine the depth of burial and the shape of seismic interface, the basic task of seismic prospecting instrument is the collection and the record of open-air geological data.Gas prospecting field seismic prospecting at oil is the major technique means.At present seismic prospecting instrument is in aspect existence problems in various degree such as precision, resolution, dynamic range, power consumption, sensitive high, anti-interference, extendibility, light portables.Provide the oil seismic exploration instrument below both at home and abroad with quasi-instrument index contrast table, therefrom some problems as can be seen.From the table can recognize existing oil seismic exploration instrument from 8 A/D to 24 A/D transition, to obtain higher resolution, and its switching frequency makes it can detect more hyperchannel simultaneously also to higher development, to obtain more auspicious real experimental data for software analysis.
As everyone knows, resolution, port number are determining whether oil seismic exploration equipment can realize higher performance, and its use software whether powerful really outside the design own, with above-mentioned hardware whether can provide can be how information-related.
Contrast with the quasi-instrument index both at home and abroad
The utility model content
The purpose of this utility model provides the covering on-off circuit that a kind of hyperchannel, high resolving power, low-power consumption, high reliability, built-in electronics cover a kind of high resolving power oil seismic exploration system of switch.
The purpose of this utility model is to realize like this, the covering on-off circuit of a kind of high resolving power oil seismic exploration system, it is characterized in that: cover on-off circuit and adopt ADG734 to constitute switch arrays, the sheet choosing end of each ADG734 in the array is electrically connected with computer bus, 8 ADG734 are fixed on the data collection plate 16, by the sheet choosing end level of processor, the seismoreceiver of selecting is connected to corresponding pre-amplification circuit according to 8 ADG734 of command selection of PC104+ built-in industrial control machine; Wave detector converts vibration signal to analog electrical signal, is connected to the input end that covers on-off circuit by big line.
Described covering switch electricity can be selected 48-96 wave detector, after covering the wave detector connection of on-off circuit selection, wave detector output signal positive and negative terminal will be connected to the INA+ and the INA-end of corresponding pre-amplification circuit, GAIN0, GAIN1, GAIN2, PWND, LPWP are electrically connected with the I/O port of processor by computer bus, and instruction is controlled according to PC104+ built-in industrial control machine (host computer); The output terminal OUTF+ of pre-amplification circuit, OUTF-difference enter the input end of analog to digital converter, carry out analog to digital conversion by analog to digital converter, the output of analog to digital converter is electrically connected by interface circuit with processor, and processor converts serial bit to byte and deposits in the storer.
Described data acquisition board comprises: pre-amplification circuit, analog to digital converter, storer, processor and average address assignment are given the covering on-off circuit of each blocks of data collection plate, the covering on-off circuit of distributing to each blocks of data collection plate is made of 8 ADG734, but a blocks of data collection plate difference inserts 32 wave detectors, two passage conductings of ADG734 make a wave detector difference be linked into a pre-amplification circuit, one blocks of data collection plate has 16 pre-amplification circuits, the output of pre-amplification circuit is electrically connected with the input of analog to digital converter, one blocks of data collection plate has 2 analog to digital converters, every analog to digital converter can connect the input of 8 tunnel simulating signals simultaneously, can insert the input of 16 tunnel simulating signals altogether, analog to digital converter is 24 analog to digital converters.All control signal ends of analog to digital converter are electrically connected with the I/O interface of processor by computer bus, by processor control analog to digital converter gain and passage.The converting digital output of analog to digital converter is electrically connected by serial ports with processor, by processor data is handled, and the byte data after will being handled by processor at last is stored in the storer.Processor and storer are electrically connected by computer bus.
Each road analog signals line in the described data acquisition board is clamped in circuit board in the PCB levels ground wire, and circuit board adopts the multilayer board structure.
Described signal generating circuit produces reference signal, the output of reference signal analog detector, and the output of signal generating circuit 3 is connected with INB-end differential electrical with the INB+ of pre-amplification circuit.
Described memory circuit adopts 3 high capacity IDT72V2111 as metadata cache, IDT72V2111 is temporary as the A/D data converted, receive the translation data of AD converter by the SPI interface by slave computer MCU, write among the FIFO successively, after collection is finished, gather completion status by MCU to the host computer report, read data among the FIFO by the FIFO another port by host computer.
The high-performance single-chip microcomputer C8051F130 that described processor adopting U.S. Cygnal company releases is that the low port of C8051F (P0, P1, P2, P3) is electrically connected control signal; High port (P4, P5, P6, P7) is electrically connected with data, the address bus of modules such as display module, storer.
Described power circuit has adopted three grades of voltage stabilizings, battery 11 is carried out first order voltage stabilizing through the power panel voltage-stabilizing device, export analog power and digital power respectively, analog power and digital power export data acquisition board to, power supply stabipack by data acquisition board carries out second level voltage stabilizing again, second level voltage stabilizing produces required multilevel voltage, wherein one group is that analog to digital converter is exported a way word voltage, the reference voltage mu balanced circuit that digital voltage is formed to analog to digital converter through third level voltage stabilizing again.
Advantage of the present utility model can clearly demonstrate by table 2:
Description of drawings
The utility model is described in further detail below in conjunction with the embodiment accompanying drawing:
Fig. 1 is the utility model embodiment circuit block diagram;
Fig. 2 is data acquisition board 16 embodiment circuit block diagrams among Fig. 1;
Fig. 3 is the pin definitions figure that the utility model covers on-off circuit 2ADG734;
Fig. 4 is the utility model pre-amplification circuit schematic diagram;
Fig. 5 is an analog-digital converter circuit pin distribution plan;
Fig. 6 is the utility model storage circuit pin distribution plan;
Fig. 7 is the utility model embodiment power circuit embodiment circuit block diagram.
Among the figure, 1, wave detector; 2, cover on-off circuit; 3, signal generating circuit; 4, pci interface plate; 5, PC104+ built-in industrial control machine; 6, pre-amplification circuit; 7, analog to digital converter; 8, storer; 9, processor; 10, computer bus; 11, battery; 12, power circuit; 13, signal wire; 14, PCB levels ground wire; 15, signal input port; 16, data acquisition board.
Embodiment
As shown in Figure 1, a kind of high resolving power oil seismic exploration system, it comprises: which comprises at least: cover on-off circuit 2, pci interface plate 4, PC104+ built-in industrial control machine 5, signal generating circuit 3, data acquisition board 16, computer bus 10 and power circuit, data acquisition board 16 has 6, data acquisition board 16 is electrically connected with PC104+ built-in industrial control machine 5 by the pci interface plate, by pci interface and PC104+ built-in industrial control machine 5 communication loops, carry out data by the PC104+ built-in industrial control machine, control signal, the distribution of address signal, the signal input port 15 of data acquisition board 16 is electrically connected with the output terminal that covers on-off circuit, wherein be electrically connected with the signal end of signal generating circuit 3, be used for detecting at a data collection plate 16, the duty of correction data acquisition plate 16, precision; Covering on-off circuit 2 and pre-amplification circuit 6 is controlled by processor 9 by computer bus 10 respectively, the address end that covers on-off circuit 2 is chosen the address by processor 9 according to the order of PC104+ built-in industrial control machine 5, and the seismoreceiver of selecting is connected to corresponding pre-amplification circuit; Wave detector 1 converts vibration signal to analog electrical signal, be connected to covering on-off circuit 2 by big line, covering on-off circuit 2 is provided with by the effective passage of processor 9 gatings according to host computer (PC104+ built-in industrial control machine 5) collection, cover the corresponding position conducting of on-off circuit 2, make the signal connection of wave detector 1 be delivered to data acquisition board 16, by data acquisition board 16 amplifications, analog to digital conversion, data-storing, carry out data presentation by PC104+ built-in industrial control machine 5.
As shown in Figure 2, provide the block diagram of data acquisition board 16, data acquisition board 16 comprises: pre-amplification circuit 6, analog to digital converter 7, storer 8, processor 9 and average address assignment are given the covering on-off circuit of each blocks of data collection plate 16, the covering on-off circuit of distributing to each blocks of data collection plate 16 is made of 8 ADG734, but a blocks of data collection plate 16 difference insert 32 wave detectors 1, two passage conductings of ADG734 make wave detector 1 difference be linked into a pre-amplification circuit 6, one blocks of data collection plate 16 has 16 pre-amplification circuits 6, the output of pre-amplification circuit is electrically connected with the input of analog to digital converter 7, one blocks of data collection plate 16 has 2 analog to digital converters 7, every analog to digital converter 7 can connect the input of 8 tunnel simulating signals simultaneously, can insert the input of 16 tunnel simulating signals altogether, analog to digital converter 7 is 24 analog to digital converters.All control signal ends of analog to digital converter 7 are electrically connected with the I/O interface of processor 9 by computer bus 10, by processor 9 control analog to digital converters 7 gain and passages.The output of the converting digital of analog to digital converter 7 and processor 9 are electrically connected by serial ports, are handled by 9 pairs of data of processor, and the byte data after will being handled by processor 9 at last is stored in the storer 8; Processor 9 and storer 8 are electrically connected by computer bus 10.
Each road analog signals line 13 in the data acquisition board 16 is clamped in circuit board in the PCB levels ground wire 14, and circuit board adopts the multilayer board structure.
Power supply in the data acquisition board 16 adopts powered battery, and battery is through the three stage power source voltage stabilizing and manage pre-amplification circuit 6, analog to digital converter 7 power ends of receiving in the data acquisition board 16.
As shown in Figure 3, covering on-off circuit 2 adopts the ADG734 of U.S. ANALOG DEVICE company to constitute switch arrays, ADG734 is a low voltage CMOS device, built-in four optional single-pole double-throw (SPDT)s of independence (SPDT) switch, A1, A2, B1, B2, C1, C2, D1, D2 are signal input part among the ADG734, A, B, C, D are signal output part, A1 and A2 corresponding A, the corresponding B of B1 and B2,, C1 and the corresponding C of C2, the corresponding D of D1 and D2, ADG734 is enabled by CE, when CE is 1 level, and A1, B1, C1 and D1 conducting, when CE is 0 level, A2, B2, C2 and D2 conducting.
Covering on-off circuit 2 can be with reference to Fig. 2 and Fig. 3, covering on-off circuit 2 in the utility model finishes selecting the access of wave detector 1, cover on-off circuit 2 and can select 48-96 wave detector 1, as number 1 wave detector 1 big line plug and be connected to the 1st electronic switch A1, B1 end, the big line plug of wave detector of numbering 2 is connected to the 1st electronic switch C1, D1 end, when the control end (CE) of the 1st electronic switch was 1, the big line plug of wave detector of the big line plug of wave detector of numbering 1 and numbering 2 was directly by two pre-amplification circuits of the 1st electronic switch to the rear end.As number 3 the big line plug of wave detector and be connected to the 1st electronic switch A2, the B2 end, the big line plug of wave detector of numbering 4 is connected to the 1st electronic switch C2, the D2 end, when the control end of the 1st electronic switch is 0, the big line plug of wave detector of the big line plug of wave detector of numbering 3 and numbering 4 is directly by two pre-amplification circuits of the 1st electronic switch to the rear end, these two pre-amplification circuits and numbering 1 and numbering 2 shared two pre-amplification circuits of wave detector, its differentiation are to determine it is the signal of wave detector of what numbering 4 by the coding of 9 couples of control end CE of processor.An ADG734 can insert 4 wave detectors, and No. 48 wave detectors need 12 ADG734 to form array, and its address is DA0 to DA11, is controlled by 12 I/O mouths that processor 9 provides.When address DA0 to DA11 is 0, there are 24 wave detectors to be switched on simultaneously, when address DA0 to DA11 was 1, back 24 wave detectors were switched on.
ADG734 employing+1.8V is fit to battery powered portable apparatus to+5.5V single supply work and uses very much.All passages all adopt break-before-make formula switch, and instantaneous short-circuit takes place when preventing the switch passage.Electronic switch has ultralow conducting resistance, less than 0.4 Ω, makes it be fit to very much require the application of minimum switch distortion in whole temperature range.
As shown in Figure 4, provide pre-amplification circuit 6 circuit theory diagrams, the CS3301 prime amplifier that pre-amplification circuit 6 adopts U.S. CirrusLogic company to produce,
After covering wave detector 1 connection of on-off circuit 2 selections, wave detector 1 output signal positive and negative terminal will be connected to the INA+ and the INA-end of corresponding pre-amplification circuit 6, GAIN0, GAIN1, GAIN2 are used for preamplification gain and select, and can select to be provided with 0,6,12,18,24,30, the preamplification gain of 36dB.PWND, LPWP are that mode of operation is selected, and can be arranged to park mode, low-speed mode, reduce system power dissipation during non-collection.GAIN0, GAIN1, GAIN2, PWND, LPWP are electrically connected with the I/O port of processor 9 by computer bus 10, and instruction is controlled according to PC104+ built-in industrial control machine 5 (host computer); The output terminal OUTF+ of pre-amplification circuit 6, OUTF-difference enter the input end of analog to digital converter 7, carry out analog to digital conversion by analog to digital converter 7, the output of analog to digital converter 7 and processor 9 are electrically connected by interface circuit, and processor 9 converts serial bit to byte and deposits in the storer 8.
In the utility model, signal generating circuit 3 produces required reference signal, but the output of reference signal analog detector 1, the output of signal generating circuit 3 is connected with INB-end differential electrical with the INB+ of pre-amplification circuit 6, output OUTR+, the OUTR-of pre-amplification circuit 6 also difference enters the input end of analog to digital converter 7, carry out analog to digital conversion by analog to digital converter 7, the output of analog to digital converter 7 and processor 9 are electrically connected by interface circuit, and processor 9 converts serial bit to byte.
The INA+ of pre-amplification circuit 6 and INA-end and INB+ and INB-select by the control of MUX0, MUX1 end, and MUX0, MUX1 are electrically connected with the I/O port of processor 9 by computer bus 10, are controlled by processor 9.
But because the output that signal generating circuit 3 produces required reference signal number analog detector 1, signal is consistent with wave detector 1 dynamic range from low to high, all passes through identical circuit, and the problem that system is existed can conveniently be understood like this.
The output signal of pre-amplification circuit 6 is adjusted to the centered level that AD needs through level adjusting circuit with signal center's level, is connected to corresponding A D converter input end.By clamping in the PCB levels ground wire 14, circuit board adopts the multilayer board structure to the input and output analog signals line 13 of pre-amplification circuit 6, makes signal reach shielding, not disturbed by outer signals in circuit board.
As shown in Figure 5, analog to digital converter 7 is 24 analog to digital converters, and analog to digital converter 7 can be realized 8 passage synchronized samplings.Analog to digital converter 7 has good AC and DC characteristic, and sampling rate is the highest can to reach 128Ks/s, and signal to noise ratio (snr) can reach 111dB during the 62kHz bandwidth, and offset drift is 0.8 μ V/ ℃.
The Input1 to Input8 of analog to digital converter 7 is connected to the output terminal of pre-amplification circuit, its data output DOUT is connected to the SPI serial port of processor, the mode that processor interrupts with SPI receives the data after the AD conversion, and data are deposited in the circuit based on dual port FIFO storer.ADS1278 can select mode of operation by corresponding I/O pin is set, and by the CLK end sample frequency is set, and processor sends enabling signal and enter acquisition state at first CLK in the clock period to the SYNC port.
The data output interface of analog to digital converter 7 is based on SPI and two kinds of agreements of Frame one Sync, by control FORMAT[2:0] pin comes the configuration data output mode.This system design is by SPI port and the A/D converter data transmission of MCU.By with FORMAT[2:0] 3 pins put lowly, and data-interface are configured to the TDM pattern of SPI agreement.Analog to digital converter 7 transfers data to MCU by the SPI serial ports and carries out data processing.
Institute is shown in Figure 6, fifo memory circuit is an important step in the data acquisition, and the utility model adopts 3 high capacity IDT72V2111 as metadata cache, because No. 48 wave detectors are gathered, the data of gathering are stored, and therefore need logarithm quick storage and transmission now factually.
The IDT72V2111 chip is the storage buffer chip of a dual-port, it is simple in structure, be convenient to operation, and have control end, flag terminal, expansion end and internal RAM array, inner reading and writing pointer can carry out writing automatically and reading of data on the basis of first in first out.After data that processor reads by the SPI serial port are processed into byte data, in that (D0～D8) deposits the data-in port of IDT72V2111 chip in, and the control end W by IDT72V2111 when depositing in writing of control data by FPDP.In order to prevent that writing of data from overflowing, available flag end full FF, half-full HF indicate the situation that writes of data.Write fashionable position of arranging it to write by inner write pointer.Because the particular design of internal RAM array, the data that deposit in earlier will be read earlier.Data are read outward if desired, then can be come the situation of reading of control data by control end R.W, R provide pulse by outside industrial computer or MCU.Data-out port Q0～Q8 is ternary, is high-impedance state when no read signal." empty EF " sign is used for preventing that the sky of data from reading; If needing that internal data is read available control end RT again realizes.Input data bit D0～D8 and outputs data bits Q0～Q8 provide 9 input and output positions, can be wherein one as controlling or User Defined.Expansion end XI, XO, FT are used for carrying out the expansion of the dark and word length of word, so that being used in combination of a plurality of chips.RS is a reset terminal.It should be noted that: owing to be asynchronous input and output, so W, R can not be simultaneously effectively.
IDT72V2111 is in that to require data to transmit when very fast the most suitable, therefore, it is temporary as the A/D data converted to choose IDT72V2111 in the design, receive the translation data of AD converter by the SPI interface by slave computer MCU, write among the FIFO successively, after collection is finished, gather completion status to the host computer report, read data among the FIFO by the FIFO another port by host computer by MCU.
The high-performance single-chip microcomputer C8051F130 that processor 9 adopts U.S. Cygnal company to release is, single-chip microcomputer is keeping under the constant situation of CISC structure and order set, can carry out line production to instruction operation, average each clock period can be carried out 1 one-cycle instruction, thereby improved instruction operation speed greatly, chip internal the is integrated FLASH program storage of 64KB, comparator module, SPI and 12C interface etc.In the sheet JTAG debug circuit allow to use the product MCU that is installed on the final application system carry out non-intrusion type, at full speed, in system debug.The successive approximation register type ADC of inner integrated 12 bit resolutions, integrated track and hold circuit among the ADC, the speed height, slewing rate can reach 100ksps, satisfies measuring accuracy and speed needs fully.
C8051F has realized that at first the 3V that simulates in the sheet with digital circuit powers (voltage range 2.7-3.6V), greatly reduces system power dissipation; Perfect clock system can guarantee that system satisfying under the response speed requirement, makes the average clock frequency of system minimum; Numerous reset source makes system under power-down mode, can arbitrarily wake up, thereby can realize the zero-power system design neatly.Therefore, C8051F has splendid minimum power consumption system design environment.
The low port of C8051F in the utility model (P0, P1, P2, P3) both can be by bit addressing, but also byte addressing, so the required control signal of system all designs in the low port part; And high port (P4, P5, P6, P7) can only byte addressing, C8051F all designs in the high port part with data modules such as display module, storer, address bus; The port resource that C8051F130 is abundant and the dirigibility of distribution thereof realize by using right of priority cross bar switch code translator; And all pins all adopt 3.3V voltage. and can be configured to open-drain or recommend the way of output and weak on draw.
As shown in Figure 7,24 high-speed A/D converters of TI company, the stability of the reference voltage of AD (reference voltage), accuracy are extremely important to hyperchannel AD acquisition system.Power circuit 12 has adopted three grades of voltage stabilizing measures, the 12V voltage that battery 11 (storage battery) is provided, carry out first order voltage stabilizing through the power panel voltage-stabilizing device earlier, voltage-stabilizing device adopts U.S. VICOR power module, export analog power (using) and digital power (using) respectively for digital circuit for mimic channel, analog power (using for mimic channel) and digital power export data acquisition board 16 to, power supply stabipack by data acquisition board 16 carries out second level voltage stabilizing again, voltage-stabilizing device produces required voltage respectively, wherein one group is analog to digital converter 7 outputs one way word voltages, the reference voltage mu balanced circuit that digital voltage is formed to analog to digital converter 7 through third level voltage stabilizing again.Third level voltage-stabilizing device adopts the REF5025 of TI company and the reference voltage mu balanced circuit that OPA350 forms.AD reference voltage and analog power, other digital powers are isolated, and reduce voltage disturbance.
Claims (7)
1. the covering on-off circuit of a high resolving power oil seismic exploration system, it is characterized in that: cover on-off circuit and adopt ADG734 to constitute switch arrays, the sheet choosing end of each ADG734 in the array is electrically connected with computer bus, 8 ADG734 are fixed on the data collection plate (16), by the sheet choosing end level of processor, the seismoreceiver of selecting is connected to corresponding pre-amplification circuit according to 8 ADG734 of command selection of PC104+ built-in industrial control machine; Wave detector converts vibration signal to analog electrical signal, is connected to the input end that covers on-off circuit by big line.
2. the covering on-off circuit of a kind of high resolving power oil seismic exploration according to claim 1 system, it is characterized in that: described data acquisition board (16) comprising: pre-amplification circuit (6), analog to digital converter (7), storer (8), processor (9) and average address assignment are given the covering on-off circuit of each blocks of data collection plate (16), the covering on-off circuit of distributing to each blocks of data collection plate (16) is made of 8 ADG734, one blocks of data collection plate (16) but difference inserts 32 wave detectors (1), two passage conductings of ADG734 make a wave detector (1) difference be linked into a pre-amplification circuit (6), one blocks of data collection plate (16) has 16 pre-amplification circuits (6), the output of pre-amplification circuit is electrically connected with the input of analog to digital converter (7), one blocks of data collection plate (16) has 2 analog to digital converters (7), every analog to digital converter (7) can connect the input of 8 tunnel simulating signals simultaneously, can insert the input of 16 tunnel simulating signals altogether, analog to digital converter (7) is 24 analog to digital converters; All control signal ends of analog to digital converter (7) are electrically connected with the I/O interface of processor (9) by computer bus (10), by processor (9) control analog to digital converter (7) gain and passage; The converting digital output of analog to digital converter (7) is electrically connected by serial ports with processor (9), by processor (9) data is handled, and the byte data after will being handled by processor (9) at last is stored in the storer (8); Processor (9) and storer (8) are electrically connected by computer bus (10).
3. the covering on-off circuit of a kind of high resolving power oil seismic exploration according to claim 1 system, it is characterized in that: each the road analog signals line (13) in the described data acquisition board (16) is clamped in circuit board in the PCB levels ground wire (14), and circuit board adopts the multilayer board structure.
4. the covering on-off circuit of a kind of high resolving power oil seismic exploration according to claim 2 system, it is characterized in that: described signal generating circuit (3) produces reference signal, the output of reference signal analog detector (1), the output of signal generating circuit (3) is connected with INB-end differential electrical with the INB+ of pre-amplification circuit (6).
5. the covering on-off circuit of a kind of high resolving power oil seismic exploration according to claim 2 system, it is characterized in that: described memory circuit adopts (3) sheet high capacity IDT72V2111 as metadata cache, IDT72V2111 is temporary as the A/D data converted, receive the translation data of AD converter by the SPI interface by host computer MCU, write among the FIFO successively, after collection is finished, gather completion status by processor to the host computer report, read data among the FIFO by the FIFO another port by host computer.
6. the covering on-off circuit of a kind of high resolving power oil seismic exploration according to claim 2 system, it is characterized in that: the high-performance single-chip microcomputer C8051F130 that described processor adopting U.S. Cygnal company releases is that the low port P0 of C8051F, P1, P2, P3 are electrically connected control signal; High port P4, P5, P6, P7 are electrically connected with data, the address bus of modules such as display module, storer.
7. the covering on-off circuit of a kind of high resolving power oil seismic exploration according to claim 2 system, it is characterized in that: described power circuit has adopted three grades of voltage stabilizings, battery (11) is carried out first order voltage stabilizing through the power panel voltage-stabilizing device, export analog power and digital power respectively, analog power and digital power export data acquisition board (16) to, power supply stabipack by data acquisition board (16) carries out second level voltage stabilizing again, second level voltage stabilizing produces required multilevel voltage, wherein one group is analog to digital converter (7) output one way word voltage, the reference voltage mu balanced circuit that digital voltage is formed to analog to digital converter (7) through third level voltage stabilizing again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206695444U CN201965239U (en) | 2010-12-20 | 2010-12-20 | Overlay switch circuit of high-resolution petroleum seismic exploration system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206695444U CN201965239U (en) | 2010-12-20 | 2010-12-20 | Overlay switch circuit of high-resolution petroleum seismic exploration system |
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| Publication Number | Publication Date |
|---|---|
| CN201965239U true CN201965239U (en) | 2011-09-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206695444U Expired - Fee Related CN201965239U (en) | 2010-12-20 | 2010-12-20 | Overlay switch circuit of high-resolution petroleum seismic exploration system |
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| Country | Link |
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| CN (1) | CN201965239U (en) |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110907 Termination date: 20151220 |
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| EXPY | Termination of patent right or utility model |