CN102540244B - Design method for power circuit of high-resolution petroleum seismic prospecting instrument - Google Patents

Design method for power circuit of high-resolution petroleum seismic prospecting instrument Download PDF

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CN102540244B
CN102540244B CN201010596595.3A CN201010596595A CN102540244B CN 102540244 B CN102540244 B CN 102540244B CN 201010596595 A CN201010596595 A CN 201010596595A CN 102540244 B CN102540244 B CN 102540244B
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circuit
analog
voltage
power
output
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CN102540244A (en
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杨光
李凯
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XI'AN HWALAND GE0-TECH CO LTD
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XI'AN HWALAND GE0-TECH CO LTD
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Abstract

The invention belongs to a petroleum seismic prospecting instrument, and particularly relates to a design method for a power circuit of a high-resolution petroleum seismic prospecting instrument. The design method for the power circuit of the high-resolution petroleum seismic prospecting instrument is characterized by at least adopting the high-resolution petroleum seismic prospecting instrument and the power circuit, the power circuit realizes three-level voltage stabilization, and voltage of a three-level voltage stabilization output is electrically connected with a data acquisition plate and a display; the three-level voltage stabilization includes that 12V voltage provided by a battery is stabilized primarily via a power plate voltage stabilizing device, then analog +/-5V power, digital 5V power and 28V power are respectively outputted, and the 28V power is used for an LED display; voltage of the analog +/-5V power and voltage of the digital 5V power are stabilized secondarily, and the analog +/-5V power generates and outputs +2.5V voltage and +3.3V voltage via a voltage stabilizing device. The high-resolution petroleum seismic prospecting instrument has multiple channels, and is high in resolution, low in power consumption and high in reliability.

Description

A kind of design method for power circuit of high-resolution petroleum seismic prospecting instrument
Technical field
The invention belongs to oil seismic exploration instrument, particularly a kind of design method for power circuit of high-resolution petroleum seismic prospecting instrument.
Background technology
Seismic prospecting instrument is with secondary reflection or shake ripple ﹐ with exciting with other vibroseiss and record the instrument of the vibration displacement that it causes on ground in seismic prospecting.Broadcast by the analytically biography of seismic wave in rock depth of burial and the shape that rule rule ﹐ determines seismic interface, the basic task of seismic prospecting instrument is collection and the record of field geological data.Technical way in the gas prospecting field seismic prospecting of oil.Problem is in various degree there is in current seismic prospecting instrument in precision, resolution, dynamic range, power consumption, sensitive height, anti-interference, extendibility, light portable etc.Provide oil seismic exploration instrument below both at home and abroad with quasi-instrument index contrast table, therefrom can find out some problems.Existing oil seismic exploration instrument can be recognized from 8 A/D to 24 A/D transition from table, to obtain higher resolution, and its switching frequency is also to higher development, make it can detect more hyperchannel, to obtain more auspicious real experimental data for software analysis simultaneously.
As everyone knows, whether resolution, port number decide oil seismic exploration equipment can realize higher performance, and it uses outside software whether really powerful design own, and whether can provide with above-mentioned hardware can how information-related.
Contrast with quasi-instrument index both at home and abroad
Summary of the invention
The object of this invention is to provide a kind of design method for power circuit of high-resolution petroleum seismic prospecting instrument of a kind of hyperchannel, high resolving power, low-power consumption, high reliability.
The object of the present invention is achieved like this, a kind of design method for power circuit of high-resolution petroleum seismic prospecting instrument, it is characterized in that: at least comprise a kind of high-resolution petroleum seismic prospecting instrument and power circuit, power circuit is three grades of voltage stabilizings, and the voltage of three grades of voltage stabilizing outputs is electrically connected with data acquisition board and display.
Three grades of described voltage stabilizings are the 12V voltage provided by battery, first carry out first order voltage stabilizing through power panel voltage-stabilizing device, and export simulation ± 5V power supply, digital 5V power supply and 28V power supply respectively, wherein 28V power supply is for light-emitting diode display; Simulation ± 5V power supply and digital 5V power supply carry out second level voltage stabilizing, simulation ± 5V power supply produces the voltage of output positive 2.5V output by voltage-stabilizing device and produces the voltage exporting positive 3.3V output, numeral 5V power supply carries out second level voltage stabilizing, and digital 5V produces the voltage of output positive 3.3V output by voltage-stabilizing device and produces the voltage exporting positive 1.8V output; Third level voltage stabilizing is the 3.3V voltage stabilizing one-tenth ± 2.5V exported through second level voltage stabilizing by digital 5V.
Described a kind of high-resolution petroleum seismic prospecting instrument which comprises at least: overlay switch circuit, pci interface plate, PC104+ built-in industrial control machine, signal generating circuit, data acquisition board and computer bus, data acquisition board has 6 pieces, data acquisition board is electrically connected with PC104+ built-in industrial control machine by pci interface plate, by pci interface and PC104+ built-in industrial control machine communication loop, data are carried out by PC104+ built-in industrial control machine, control signal, the distribution of address signal, the signal input port of data acquisition board is electrically connected with the output terminal of overlay switch circuit, wherein be electrically connected with the signal end of signal generating circuit a data acquisition board, for detecting, the duty of correction data acquisition plate, precision, overlay switch circuit and pre-amplification circuit are controlled by processor respectively by computer bus, the address end of overlay switch circuit chooses address by processor according to the order of PC104+ built-in industrial control machine 5, the seismoreceiver of selection is connected to corresponding pre-amplification circuit, wave detector converts vibration signal to analog electrical signal, overlay switch circuit is connected to by large line, overlay switch circuit passes through the effective passage of processor gating according to host computer (PC104+ built-in industrial control machine) capture setting, the corresponding position conducting of overlay switch circuit, the signal of wave detector 1 is connected and is delivered to data acquisition board, by data acquisition board amplification, analog to digital conversion, data-storing, carry out data display by PC104+ built-in industrial control machine.
Described data acquisition board comprises: pre-amplification circuit, analog to digital converter, storer, processor and average address assignment give the overlay switch circuit of each blocks of data collection plate, the overlay switch circuit distributing to each blocks of data collection plate 16 is made up of 8 ADG734, one blocks of data collection plate difference can access 32 wave detectors, two channel conductive of ADG734 make wave detector 1 difference be linked into a pre-amplification circuit, one blocks of data collection plate has 16 pre-amplification circuits, the output of pre-amplification circuit is electrically connected with the input of analog to digital converter, one blocks of data collection plate has 2 analog to digital converters, every analog to digital converter can connect 8 tunnel simulating signal inputs simultaneously, accessible 16 tunnel simulating signal inputs altogether, analog to digital converter is 24 analog to digital converters.All control signal ends of analog to digital converter are electrically connected with the I/O interface of processor by computer bus, control analog to digital converter gain and passage by processor; The converting digital of analog to digital converter is exported and is connected by serial port power with processor, is processed data by processor, finally the byte data after process is stored in memory by processor; Processor and storer are electrically connected by computer bus.
Each road analog signals line in described data acquisition board is clamped in PCB levels ground wire in the circuit board, and circuit board adopts Multilayer Structure.
Described overlay switch circuit has 48-96 wave detector input end interface, after the wave detector that overlay switch circuit is selected is connected, geophone output signal positive and negative terminal will be connected to INA+ and the INA-end of corresponding pre-amplification circuit 6, GAIN0, GAIN1, GAIN2 are used for preamplification gain and select, can select to arrange 0,6,12,18,24,30, the preamplification gain of 36dB; PWND, LPWP are that mode of operation is selected, and can be arranged to park mode, low-speed mode, during non-acquired, reduce system power dissipation; GAIN0, GAIN1, GAIN2, PWND, LPWP are electrically connected with the I/O port of processor by computer bus, control according to PC104+ built-in industrial control machine (host computer) instruction; Output terminal OUTF+, OUTF-difference of pre-amplification circuit enters the input end of analog to digital converter, analog to digital conversion is carried out by analog to digital converter, the output of analog to digital converter is electrically connected by interface circuit with processor, and serial bit is converted to byte stored in storer by processor.
Output OUTR+, OUTR-difference of described pre-amplification circuit enters the input end of analog to digital converter, carries out analog to digital conversion by analog to digital converter, and the output of analog to digital converter is electrically connected by interface circuit with processor, and processor converts serial bit to byte; INA+ and the INA-end of pre-amplification circuit and INB+ and INB-control to select by MUX0, MUX1 end, and MUX0, MUX1 are electrically connected with the I/O port of processor by computer bus, are controlled by processor; Signal center's level, through level adjusting circuit, is adjusted to the centered level that AD needs, is connected to corresponding A D switch input by the output signal of pre-amplification circuit; The input and output analog signals line of described pre-amplification circuit is in the circuit board by clamping in PCB levels ground wire.
Described analog to digital converter is 24 analog to digital converters, the Input1 to Input8 of 24 analog to digital converters is connected to the output terminal of pre-amplification circuit, its data export the SPI serial port that DOUT is connected to processor, processor receives the data after AD conversion in the mode that SPI interrupts, and by data stored in circuit based on dual port FIFO storer.
Described memory circuit adopts 3 Large Copacity IDT72V2111 as data buffer storage, the data temporary storage that IDT72V2111 changes as A/D, by the translation data of slave computer MCU by SPI interface AD converter, write successively in FIFO, after collection completes, gather completion status by MCU to host computer report, read data in FIFO by host computer by FIFO another port.
The High Performance SCM C8051F130 that described processor adopts Cygnal company of the U.S. to release is that the low port (P0, P1, P2, P3) of C8051F is electrically connected control signal; Data, the address bus of high port (P4, P5, P6, P7) and the module such as display module, storer are electrically connected.
Advantage of the present invention can be clearly demonstrated by table 2:
Accompanying drawing explanation
Below in conjunction with embodiment accompanying drawing, the invention will be further described:
Fig. 1 is embodiment of the present invention circuit block diagram;
Fig. 2 is data acquisition board 16 embodiment circuit block diagram in Fig. 1;
Fig. 3 is the pin definitions figure of overlay switch circuit 2ADG734 of the present invention;
Fig. 4 is pre-amplification circuit schematic diagram of the present invention;
Fig. 5 is analog-digital converter circuit pin distribution plan;
Fig. 6 is storage circuit pin distribution plan of the present invention;
Fig. 7 is embodiment of the present invention power circuit embodiment circuit block diagram;
Fig. 8 is the physical circuit refinement block diagram of Fig. 7.
In figure, 1, wave detector; 2, overlay switch circuit; 3, signal generating circuit; 4, pci interface plate; 5, PC104+ built-in industrial control machine; 6, pre-amplification circuit; 7, analog to digital converter; 8, storer; 9, processor; 10, computer bus; 11, battery; 12, power circuit; 13, signal wire; 14, PCB levels ground wire; 15, signal input port; 16, data acquisition board.
Embodiment
As shown in Figure 1, a kind of design method for power circuit of high-resolution petroleum seismic prospecting instrument, it comprises: which comprises at least: overlay switch circuit 2, pci interface plate 4, PC104+ built-in industrial control machine 5, signal generating circuit 3, data acquisition board 16 and computer bus 10, data acquisition board 16 has 6 pieces, data acquisition board 16 is electrically connected with PC104+ built-in industrial control machine 5 by pci interface plate, by pci interface and PC104+ built-in industrial control machine 5 communication loop, data are carried out by PC104+ built-in industrial control machine, control signal, the distribution of address signal, the signal input port 15 of data acquisition board 16 is electrically connected with the output terminal of overlay switch circuit, wherein be electrically connected with the signal end of signal generating circuit 3 a data acquisition board 16, for detecting, the duty of correction data acquisition plate 16, precision, overlay switch circuit 2 and pre-amplification circuit 6 are controlled by processor 9 respectively by computer bus 10, the address end of overlay switch circuit 2 chooses address by processor 9 according to the order of PC104+ built-in industrial control machine 5, the seismoreceiver of selection is connected to corresponding pre-amplification circuit, wave detector 1 converts vibration signal to analog electrical signal, overlay switch circuit 2 is connected to by large line, overlay switch circuit 2 passes through the effective passage of processor 9 gating according to host computer (PC104+ built-in industrial control machine 5) capture setting, the corresponding position conducting of overlay switch circuit 2, the signal of wave detector 1 is connected and is delivered to data acquisition board 16, amplified by data acquisition board 16, analog to digital conversion, data-storing, carry out data display by PC104+ built-in industrial control machine 5.
As shown in Figure 2, provide the block diagram of data acquisition board 16, data acquisition board 16 comprises: pre-amplification circuit 6, analog to digital converter 7, storer 8, processor 9 and average address assignment give the overlay switch circuit of each blocks of data collection plate 16, one blocks of data collection plate 16 difference can access 32 wave detectors 1, two channel conductive of ADG734 make wave detector 1 difference be linked into a pre-amplification circuit 6, one blocks of data collection plate 16 has 16 pre-amplification circuits 6, the output of pre-amplification circuit is electrically connected with the input of analog to digital converter 7, one blocks of data collection plate 16 has 2 analog to digital converters 7, every analog to digital converter 7 can connect 8 tunnel simulating signal inputs simultaneously, accessible 16 tunnel simulating signal inputs altogether, analog to digital converter 7 is 24 analog to digital converters.All control signal ends of analog to digital converter 7 are electrically connected with the I/O interface of processor 9 by computer bus 10, control analog to digital converter 7 gain and passage by processor 9.The converting digital of analog to digital converter 7 is exported and is connected by serial port power with processor 9, is processed by processor 9 pairs of data, finally the byte data after process is stored in the memory 8 by processor 9.Processor 9 and storer 8 are electrically connected by computer bus 10.
Each road analog signals line 13 in data acquisition board 16 is clamped in PCB levels ground wire 14 in the circuit board, and circuit board adopts Multilayer Structure.
Power acquisition powered battery in data acquisition board 16, battery is through three stage power source voltage stabilizing and manage pre-amplification circuit 6, analog to digital converter 7 power end received in data acquisition board 16.
As shown in Figure 3, overlay switch circuit 2 adopts the ADG734 of ANALOG DEVICE company of the U.S. to form switch arrays, ADG734 is a low voltage CMOS device, single-pole double-throw (SPDT) (SPDT) switch of built-in four separate alternative, A1 in ADG734, A2, B1, B2, C1, C2, D1, D2 is signal input part, A, B, C, D is signal output part, A1 and A2 corresponding A, the corresponding B of B1 and B2, , the corresponding C of C1 and C2, the corresponding D of D1 and D2, ADG734 is enable by CE, when CE is 1 level, A1, B1, C1 and D1 conducting, when CE is 0 level, A2, B2, C2 and D2 conducting.
Overlay switch circuit 2 can refer to Fig. 2 and Fig. 3, in the present invention, overlay switch circuit 2 completes the access to selected wave detector 1, overlay switch circuit 2 can select 48-96 wave detector 1, the large line plug of wave detector 1 as numbering 1 is connected to the 1st electronic switch A1, B1 end, the large line plug of wave detector of numbering 2 is connected to the 1st electronic switch C1, D1 end, when the control end (CE) of the 1st electronic switch is 1, the wave detector large line plug of numbering 1 and the large line plug of wave detector of numbering 2 are directly by two pre-amplification circuits of the 1st electronic switch to rear end.The large line plug of wave detector as numbering 3 is connected to the 1st electronic switch A2, B2 holds, the large line plug of wave detector of numbering 4 is connected to the 1st electronic switch C2, D2 holds, when the control end of the 1st electronic switch is 0, the wave detector large line plug of numbering 3 and the large line plug of wave detector of numbering 4 are directly by two pre-amplification circuits of the 1st electronic switch to rear end, the wave detector of these two pre-amplification circuits and numbering 1 and numbering 2 shares two pre-amplification circuits, its differentiation is the signal being determined the wave detector being what numbering 4 by the coding of processor 9 couples of control end CE.Accessible 4 wave detectors of ADG734, No. 48 wave detectors need 12 ADG734 to form array, and its address is DA0 to DA11, and 12 the I/O mouths provided by processor 9 control.When address DA0 to DA11 is 0, have 24 wave detectors to be switched on, when address DA0 to DA11 is 1, rear 24 wave detectors are switched on simultaneously.
ADG734 adopts+1.8V to be applicable to very much the application of battery powered portable apparatus to+5.5 V single supply work.All passages all adopt break-before-make formula switch, prevent from, during switching channels, instantaneous short-circuit occurs.Electronic switch has ultralow conducting resistance, is less than 0.4 Ω in whole temperature range, makes it be applicable to very much requiring the application of minimum switch distortion.
As shown in Figure 4, pre-amplification circuit 6 circuit theory diagrams are provided.
After the wave detector 1 that overlay switch circuit 2 is selected is connected, wave detector 1 outputs signal positive and negative terminal will be connected to INA+ and the INA-end of corresponding pre-amplification circuit 6, GAIN0, GAIN1, GAIN2 are used for preamplification gain and select, can select to arrange 0,6,12,18,24,30, the preamplification gain of 36dB.PWND, LPWP are that mode of operation is selected, and can be arranged to park mode, low-speed mode, during non-acquired, reduce system power dissipation.GAIN0, GAIN1, GAIN2, PWND, LPWP are electrically connected with the I/O port of processor 9 by computer bus 10, control according to PC104+ built-in industrial control machine 5 (host computer) instruction; Output terminal OUTF+, OUTF-difference of pre-amplification circuit 6 enters the input end of analog to digital converter 7, analog to digital conversion is carried out by analog to digital converter 7, the output of analog to digital converter 7 is electrically connected by interface circuit with processor 9, and serial bit is converted to byte stored in storer 8 by processor 9.
In the present invention, signal generating circuit 3 produces required reference signal, reference signal can the output of analog detector 1, the output of signal generating circuit 3 holds differential electrical to be connected with INB+ and INB-of pre-amplification circuit 6, output OUTR+, OUTR-of pre-amplification circuit 6 also difference enter the input end of analog to digital converter 7, carry out analog to digital conversion by analog to digital converter 7, the output of analog to digital converter 7 is electrically connected by interface circuit with processor 9, and processor 9 converts serial bit to byte.
INA+ and the INA-end of pre-amplification circuit 6 and INB+ and INB-control to select by MUX0, MUX1 end, and MUX0, MUX1 are electrically connected with the I/O port of processor 9 by computer bus 10, are controlled by processor 9.
Due to signal generating circuit 3 produces required reference signal number can the output of analog detector 1, signal is consistent with wave detector 1 dynamic range from low to high, all through identical circuit, can conveniently understand like this to system Problems existing.
Signal center's level, through level adjusting circuit, is adjusted to the centered level that AD needs, is connected to corresponding A D switch input by the output signal of pre-amplification circuit 6.
The input and output analog signals line 13 of pre-amplification circuit 6 is in the circuit board by clamping in PCB levels ground wire 14, and circuit board adopts Multilayer Structure, makes signal reach shielding, does not disturb by outer signals.
As shown in Figure 5, analog to digital converter 7 is 24 analog to digital converters, analog to digital converter 7 inside is integrated with multiple independently high-order chopped wave stabilizing modulator and Finite Impulse Response filter, 8 Channel Synchronous samplings can be realized, support high speed, high precision, low-power consumption, low speed 4 kinds of mode of operations, analog to digital converter 7 has excellent AC and DC characteristic, and sampling rate is the highest can reach 128 Ks/s, during 62kHz bandwidth, signal to noise ratio (S/N ratio) (SNR) can reach 111 dB, and offset drift is 0.8 μ V/ DEG C.
The Input1 to Input8 of analog to digital converter 7 is connected to the output terminal of pre-amplification circuit, its data export the SPI serial port that DOUT is connected to processor, processor receives the data after AD conversion in the mode that SPI interrupts, and by data stored in circuit based on dual port FIFO storer.Analog to digital converter 7 selects mode of operation by arranging corresponding I/O pin, arranges sample frequency, enter acquisition state after processor sends enabling signal to SYNC port within first CLK clock period by CLK end.
Analog to digital converter 7 can provide high speed, high resolving power, low-power consumption and low speed 4 kinds of operator schemes to select for user, also controls by configuration MODE [1:0] leg signal implementation pattern.General purpose I/0 end the pin that the mode selection pin MODE [1:0] of analog to digital converter 7 is connected to processor is selected 4 kinds of patterns.At data acquisition system (DAS) initial phase, processor is made to export corresponding mode select signal from I/O by arranging, thus the controllability that implementation pattern is selected.Meanwhile, by the timer of processor to analog to digital converter 7 output clock, thus control the synchronized sampling frequency of 8 passages more accurately.
The data output interface of analog to digital converter 7, based on SPI and Frame mono-Sync two kinds of agreements, carrys out configuration data output mode by control FORMAT [2:0] pin.This system is transmitted by the SPI port of MCU and A/D converter data.By being set low by FORMAT [2:0] 3 pins, and data-interface is configured to the TDM pattern of SPI protocol.
Shown in institute Fig. 6, fifo memory circuit is an important step in data acquisition, and the present invention adopts 3 Large Copacity IDT72V2111 as data buffer storage, owing to gathering No. 48 wave detectors, the data gathered are stored, and therefore need logarithm now quick storage and transmission factually.
IDT72V2111 chip is the storage buffer chip of a dual-port, its structure is simple, convenient operation, and there is control end, flag terminal, expansion end and internal RAM array, inner reading and writing pointer can carry out the automatic writing and reading of data on the basis of first in first out.After the data read by SPI serial port when processor carry out being processed into byte data, by the data-in port of FPDP (D0 ~ D8) stored in IDT72V2111 chip, stored in time carry out writing of control data by the control end W of IDT72V2111.In order to prevent the Writing overflow of data, available flag end full FF, half-full HF indicate the write situation of data.The position arranging it to write by inner write pointer during write.Due to the particular design of internal RAM array, first stored in data will first be read.If need to read outside data, then can be carried out the reading situation of control data by control end R.W, R provide pulse by outside industrial computer or MCU.Data-out port Q0 ~ Q8 is tri-state, without during read signal being high-impedance state." empty EF " mark is used for preventing the sky of data from reading; Can realize with control end RT if internal data need be read again.Input data bit D0 ~ D8 and outputs data bits Q0 ~ Q8 9 bit input and output positions are provided, can will wherein one be used as control or User Defined.Expansion end XI, XO, FT are used for carrying out the expansion of the dark and word length of word, so that the combinationally using of multiple chip.RS is reset terminal.It is to be noted that owing to being asynchronous input and output, therefore W, R can not effectively simultaneously.
IDT72V2111 is the most applicable when requiring data to transmit very fast, therefore, the data temporary storage that IDT72V2111 changes as A/D is chosen in the design, by the translation data of slave computer MCU by SPI interface AD converter, write successively in FIFO, after collection completes, gather completion status by MCU to host computer report, read data in FIFO by host computer by FIFO another port.
The High Performance SCM C8051F130 that processor 9 adopts Cygnal company of the U.S. to release is, single-chip microcomputer C8051F130 is when keeping CISC structure and order set is constant, line production can be carried out to instruction operation, average each clock period can perform 1 one-cycle instruction, thus substantially increase instruction operation speed, chip internal is integrated with the FLASH program storage of 64KB, comparator module, SPI and I2C interface etc.In sheet JTAG debug circuit allow use the product MCU be arranged in final application system carry out non-intrusion type, at full speed, in system debug.The successive approximation register type ADC of inner 12-Bit resolution, be integrated with track and hold circuit in ADC, speed is high, and slewing rate can reach 100ksps, meets measuring accuracy and speed needs completely.
First C8051F achieves the 3V of analogue and digital circuit in sheet to power (voltage range 2.7-3.6 V), greatly reduces system power dissipation; Perfect clock system can ensure that system is meeting under response speed requirement, makes the average clock frequency of system minimum; Numerous reset source makes system under power-down mode, can arbitrarily wake up, thus can realize Zero power consumption system design neatly.Therefore, C8051F has splendid minimum power consumption system design environment.
In the present invention, the low port (P0, P1, P2, P3) of C8051F both can by bit addressing, also can byte addressing, so the control signal needed for system all designs in low port part; And high port (P4, P5, P6, P7) can only byte addressing, C8051F all designs in high port part with the data of the module such as display module, storer, address bus; The dirigibility of the port resource that C8051F130 enriches and distribution thereof realizes by using priority crossbar decoder; And all pins all adopt 3.3V voltage. and open-drain can be configured to or recommend the way of output and weak pull-up.
As shown in Figure 7, the stability of the reference voltage (reference voltage) of analog to digital converter 7, accuracy are extremely important to hyperchannel AD acquisition system.Power circuit 12 have employed three grades of voltage stabilizing measures, by the 12V voltage that battery 11 (storage battery) provides, first carry out first order voltage stabilizing through power panel voltage-stabilizing device, voltage-stabilizing device exports analog power (for mimic channel) and digital power (for digital circuit) respectively, analog power (for mimic channel) and digital power export data acquisition board 16 to, second level voltage stabilizing is carried out again by the power supply stabipack of data acquisition board 16, wherein one group is that analog to digital converter 7 exports a railway digital voltage, digital voltage is again through reference voltage mu balanced circuit that third level voltage stabilizing forms to analog to digital converter 7.
As shown in Figure 8, three grades of voltage stabilizing measures of power circuit 12 are: the 12V voltage provided by battery 11 (storage battery), first carry out first order voltage stabilizing through power panel voltage-stabilizing device, voltage-stabilizing device adopts U.S. VICOR power module, export simulation ± 5V power supply and (for mimic channel) and digital 5V power supply (for digital circuit) and 28V power supply respectively, wherein 28V power supply is for light-emitting diode display.Simulation ± 5V power supply and digital 5V power supply carry out second level voltage stabilizing, and simulation ± 5V power supply produces the voltage of output positive 2.5V output by voltage-stabilizing device and produces the voltage exporting positive 3.3V output; Numeral 5V power supply carries out second level voltage stabilizing, and digital 5V produces the voltage of output positive 3.3V output by voltage-stabilizing device and produces the voltage exporting positive 1.8V output.Third level voltage stabilizing is that the 3.3V that digital 5V exports through second level voltage stabilizing is exported voltage stabilizing one-tenth ± 2.5V.

Claims (6)

1. a power circuit of high-resolution petroleum seismic prospecting instrument, it is characterized in that: at least comprise high-resolution petroleum seismic prospecting instrument and power circuit (12), power circuit (12) is three grades of mu balanced circuits, and the voltage of three grades of mu balanced circuit outputs is electrically connected with high-resolution petroleum seismic prospecting instrument;
Described high-resolution petroleum seismic prospecting instrument which comprises at least: overlay switch circuit (2), pci interface plate (4), host computer, signal generating circuit (3), data acquisition board (16) and computer bus (10), data acquisition board (16) has 6 pieces, data acquisition board (16) is electrically connected with host computer by pci interface plate, by pci interface and host computer communication loop, data are carried out by host computer, control signal, the distribution of address signal, the signal input port (15) of data acquisition board (16) is electrically connected with the output terminal of overlay switch circuit, wherein be electrically connected with the signal end of signal generating circuit (3) a data acquisition board (16), for detecting, the duty of correction data acquisition plate (16), precision, overlay switch circuit (2) and pre-amplification circuit (6) are controlled by processor (9) respectively by computer bus (10), the address end of overlay switch circuit (2) chooses address by processor (9) according to the order of host computer, the seismoreceiver of selection is connected to corresponding pre-amplification circuit, wave detector (1) converts vibration signal to analog electrical signal, overlay switch circuit (2) is connected to by large line, overlay switch circuit (2) passes through the effective passage of processor (9) gating according to host computer capture setting, the corresponding position conducting of overlay switch circuit (2), the signal of wave detector (1) is connected and is delivered to data acquisition board (16), by data acquisition board (16) amplification, analog to digital conversion, data-storing, carry out data display by host computer,
Three grades of described mu balanced circuits are the 12V voltage provided by battery (11), first carry out first order voltage stabilizing through power panel voltage-stabilizing device, and export simulation ± 5V power supply, digital 5V power supply and 28V power supply respectively, wherein 28V power supply is for light-emitting diode display; Simulation ± 5V power supply and digital 5V power supply carry out second level voltage stabilizing, simulation ± 5V power supply produces the voltage of output positive 2.5V output by voltage-stabilizing device and produces the voltage exporting positive 3.3V output, numeral 5V power supply carries out second level voltage stabilizing, and digital 5V produces the voltage of output positive 3.3V output by voltage-stabilizing device and produces the voltage exporting positive 1.8V output; Third level voltage stabilizing is the 3.3V voltage stabilizing one-tenth ± 2.5V exported through second level voltage stabilizing by digital 5V.
2. a kind of power circuit of high-resolution petroleum seismic prospecting instrument according to claim 1, it is characterized in that: each road analog signals line (13) in described data acquisition board (16) is clamped in PCB levels ground wire (14) in the circuit board, circuit board adopts Multilayer Structure.
3. a kind of power circuit of high-resolution petroleum seismic prospecting instrument according to claim 1, it is characterized in that: described overlay switch circuit (2) adopts the ADG734 of ANALOG DEVICE company of the U.S. to form switch arrays, overlay switch circuit (2) can select 48-96 wave detector (1), after the wave detector (1) that overlay switch circuit (2) is selected is connected, wave detector (1) output signal positive and negative terminal will be connected to INA+ and the INA-end of corresponding pre-amplification circuit (6), GAIN0, GAIN1, GAIN2 is used for preamplification gain and selects, can select to arrange 0, 6, 12, 18, 24, 30, the preamplification gain of 36dB, PWND, LPWP are that mode of operation is selected, and can be arranged to park mode, low-speed mode, during non-acquired, reduce system power dissipation, GAIN0, GAIN1, GAIN2, PWND, LPWP are electrically connected with the I/O port of processor (9) by computer bus (10), control according to host computer instruction, output terminal OUTF+, OUTF-difference of pre-amplification circuit (6) enters the input end of analog to digital converter (7), analog to digital conversion is carried out by analog to digital converter (7), the output of analog to digital converter (7) is electrically connected by interface circuit with processor (9), and serial bit is converted to byte stored in storer (8) by processor (9).
4. a kind of power circuit of high-resolution petroleum seismic prospecting instrument according to claim 1, it is characterized in that: described signal generating circuit (3) produces reference signal, the output of reference signal analog detector (1), the output of signal generating circuit (3) holds differential electrical to be connected with INB+ and INB-of pre-amplification circuit (6).
5. a kind of power circuit of high-resolution petroleum seismic prospecting instrument according to claim 1, it is characterized in that: output OUTR+, OUTR-difference of described pre-amplification circuit (6) enters the input end of analog to digital converter (7), analog to digital conversion is carried out by analog to digital converter (7), the output of analog to digital converter (7) is electrically connected by interface circuit with processor (9), and processor (9) converts serial bit to byte; INA+ and the INA-end of pre-amplification circuit (6) and INB+ and INB-control to select by MUX0, MUX1 end, MUX0, MUX1 are electrically connected with the I/O port of processor (9) by computer bus (10), are controlled by processor (9); Signal center's level, through level adjusting circuit, is adjusted to the centered level that AD needs, is connected to corresponding A D switch input by the output signal of described pre-amplification circuit (6); The input and output analog signals line (13) of described pre-amplification circuit (6) is in the circuit board by clamping in PCB levels ground wire (14).
6. a kind of power circuit of high-resolution petroleum seismic prospecting instrument according to claim 3, it is characterized in that: the Input1 to Input8 of described analog to digital converter (7) is connected to the output terminal of pre-amplification circuit, its data export the SPI serial port that DOUT is connected to processor, processor receives the data after AD conversion in the mode that SPI interrupts, and by data stored in circuit based on dual port FIFO storer.
CN201010596595.3A 2010-12-20 2010-12-20 Design method for power circuit of high-resolution petroleum seismic prospecting instrument Expired - Fee Related CN102540244B (en)

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