CN201955619U - Layout structure of photoetching alignment graph in semiconductor manufacture - Google Patents
Layout structure of photoetching alignment graph in semiconductor manufacture Download PDFInfo
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- CN201955619U CN201955619U CN2010206297930U CN201020629793U CN201955619U CN 201955619 U CN201955619 U CN 201955619U CN 2010206297930 U CN2010206297930 U CN 2010206297930U CN 201020629793 U CN201020629793 U CN 201020629793U CN 201955619 U CN201955619 U CN 201955619U
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- photoetching
- scribe line
- photoetching alignment
- alignment
- alignment graph
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Abstract
The utility model discloses a layout structure of a photoetching alignment graph in semiconductor manufacture. The photoetching alignment graph is vertically placed in a cross area of an edge scribing groove and an internal scribing groove, and the lower part of the photoetching alignment graph is tightly adjoined to the lower part of the edge scribing groove. By means of the layout structure, the placing problem of the photoetching alignment graph in the narrowed scribing grooves is solved.
Description
Technical field
The present invention relates to the domain structure in a kind of semiconductor fabrication process, particularly the domain structure of the photoetching alignment figure of scribe line area.
Background technology
The layout design of chip is used for chip manufacturing.Before the chip layout data are used for manufacturing, will repeat to arrange according to this chip size size according to the exposure range in manufacturing.Be scribe line area between chip area and chip area, this zone need be placed the required figure of using in lithography alignment figure (Alignment Mark) and the photoetching alignment measurement pattern manufacture processes such as (Overlay Mark see Fig. 1) usually.The layout design of scribe line area can be referred to as framed structure (Frame) design.The scribe line figure is arranged together with the arrangement (Array) of chip layout and has been formed effective exposure data on the final lay photoetching mask plate.
According to the measurement demand of photoetching process, the minimum active graphical width of photoetching alignment measurement pattern is 40 μ m * 40 μ m, and must all be placed on the scribe line of edge.Common scribe line width is in 80 μ m and above Frame design, and it is no problem that photoetching alignment measurement markers can be placed on arbitrarily on the edge scribe line (half width of having only inner scribe line).But along with dwindling of chip size, the scribe line width has more significantly influence for whole chip area, and the scribe line width can wish to narrow down to 50 μ m or 60 μ m.The scribe line effective width at edge has only 25 μ m or 30 μ m.
Therefore, originally the photoetching overlay mark is placed on the laying method of edge scribe line arbitrarily, and will causes photoetching alignment figure to exceed the scribe line area (see figure 2), and caused figure to lose efficacy.Therefore, realize the structural design of little scribe line, the essential placement problem that solves photo-etching mark.
Summary of the invention
The technical problem to be solved in the present invention provide a kind of in semiconductor fabrication process the domain structure of scribe line area, it has solved the placement problem of edge photo-etching mark.
For solving the problems of the technologies described above, the domain structure of photoetching in semiconductor manufacture alignment figure of the present invention, wherein photoetching alignment figure vertically is placed on the intersection region of described edge scribe line and inner scribe line, and the bottom of described photoetching alignment figure is near the bottom of described edge scribe line.
The domain structure of photoetching alignment figure of the present utility model, by the photoetching overlay mark being positioned over respectively on the position that edge scribe line and middle scribe line intersect, solve the problems referred to above, realized dwindling the Frame design of scribe line, adapted to the application of dwindling of chip area.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the synoptic diagram of photoetching alignment figure;
Fig. 2 is that original photoetching overlay mark is placed synoptic diagram;
Fig. 3 is a photoetching overlay mark domain synoptic diagram of the present utility model.
Embodiment
The domain structure of photoetching alignment figure in semiconductor fabrication process, for photoetching alignment figure being vertically set on the intersection region of edge scribe line and inner scribe line, and the bottom of photoetching alignment figure is near the below of edge scribe line.Above-mentioned photoetching alignment figure comprises the graphics field and the photoetching overlay mark zone (see figure 3) of sign photoetching alignment level, and for example " A " among Fig. 3 is to " D " expression photoetching alignment level.
In concrete enforcement, the minimum active graphical of photoetching alignment figure is 40 μ m * 40 μ m, and the width of scribe line is 50 μ m or 60um, and the width of edge scribe line is 25 μ m or 30um.
Domain structure of the present utility model can generate in software automatically.In the rule file in the structural design of scribing sheet groove structures and automatic placement indexing unit, in the placement priority of mark kind, transfer to the priority level of photoetching alignment figure the highest, simultaneously the distance of the placement between the photoetching alignment figure is provided with a bigger numerical (can be the distance that a chip adds an inner scribe line), and the modes of emplacement of photoetching alignment figure is arranged to inner, thereby realizes that each photoetching alignment figure can be positioned over after having moved formulation (Frame) fill order in the zone that edge scribe line and inner scribe line intersect automatically.
Claims (3)
1. the domain structure of a photoetching in semiconductor manufacture alignment figure, it is characterized in that: photoetching alignment figure vertically is placed on the intersection region of described edge scribe line and inner scribe line, and the below of described photoetching alignment figure is near the below of described edge scribe line.
2. according to the described domain structure of claim 1, it is characterized in that: described photoetching alignment figure comprises the graphics field and the photoetching overlay mark zone of sign photoetching alignment level.
3. according to claim 1 or 2 described domain structures, it is characterized in that: the minimum active graphical of described photoetching alignment figure is 40 μ m * 40 μ m, and the width of described scribe line is 50 μ m or 60um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206297930U CN201955619U (en) | 2010-11-29 | 2010-11-29 | Layout structure of photoetching alignment graph in semiconductor manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206297930U CN201955619U (en) | 2010-11-29 | 2010-11-29 | Layout structure of photoetching alignment graph in semiconductor manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201955619U true CN201955619U (en) | 2011-08-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206297930U Expired - Fee Related CN201955619U (en) | 2010-11-29 | 2010-11-29 | Layout structure of photoetching alignment graph in semiconductor manufacture |
Country Status (1)
| Country | Link |
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| CN (1) | CN201955619U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436151A (en) * | 2011-12-22 | 2012-05-02 | 上海宏力半导体制造有限公司 | Forming method of photoetching layout |
| CN103324037A (en) * | 2013-07-04 | 2013-09-25 | 北京京东方光电科技有限公司 | Exposure device and method |
| CN113515018A (en) * | 2021-04-13 | 2021-10-19 | 西安卫光科技有限公司 | Alignment mark design method of 60-micrometer scribing groove |
-
2010
- 2010-11-29 CN CN2010206297930U patent/CN201955619U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436151A (en) * | 2011-12-22 | 2012-05-02 | 上海宏力半导体制造有限公司 | Forming method of photoetching layout |
| CN102436151B (en) * | 2011-12-22 | 2015-02-25 | 上海华虹宏力半导体制造有限公司 | Forming method of photoetching layout |
| CN103324037A (en) * | 2013-07-04 | 2013-09-25 | 北京京东方光电科技有限公司 | Exposure device and method |
| CN103324037B (en) * | 2013-07-04 | 2015-01-07 | 北京京东方光电科技有限公司 | Exposure device and method |
| CN113515018A (en) * | 2021-04-13 | 2021-10-19 | 西安卫光科技有限公司 | Alignment mark design method of 60-micrometer scribing groove |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131220 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20131220 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110831 Termination date: 20151129 |