CN201909924U - TFT (thin film transistor) array baseplate - Google Patents
TFT (thin film transistor) array baseplate Download PDFInfo
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- CN201909924U CN201909924U CN2011200011101U CN201120001110U CN201909924U CN 201909924 U CN201909924 U CN 201909924U CN 2011200011101 U CN2011200011101 U CN 2011200011101U CN 201120001110 U CN201120001110 U CN 201120001110U CN 201909924 U CN201909924 U CN 201909924U
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Abstract
An embodiment of the utility model discloses a TFT (thin film transistor) array baseplate, relating to the technical field of display equipment. The problem that the charging of a liquid crystal capacitor and a storage capacitor is insufficient is solved. According to the TFT array baseplate, every row of pixel units of the TFT array baseplate further comprises at least one group of voltage storage circuits; every group of voltage storage circuits comprises a pre-storage capacitor and a first switch thin film transistor; a gate electrode and a source electrode of the first switch thin film transistor are connected with corresponding gate electrode scanning lines of an upper row of pixel units; a drain electrode of the first switch thin film transistor is connected with a first electrode of the pre-storage capacitor; every pixel unit further comprises a second switch thin film transistor; a gate electrode of the second switch thin film transistor is connected with a gate electrode scanning line corresponding to a pixel unit where the second switch thin film transistor is positioned; a source electrode of the second switch thin film transistor is connected with a first electrode of the pre-storage capacitor in the same row; and a drain electrode of the second switch thin film transistor is connected with a pixel electrode of the pixel unit where the second switch thin film transistor is positioned. The TFT array baseplate is mainly used for the display equipment and the manufacturing process of the display equipment, such as the TFT array baseplate and the manufacturing process the of TFT array baseplate.
Description
Technical field
The utility model relates to the display device technical field, relates in particular to TFT (Thin Film Transistor, Thin Film Transistor (TFT)) array base palte.
Background technology
At TFT LCD (Liquid Crystal Display, LCD) in, must during the selection of controlling grid scan line, import from the voltage data signal that the data scanning line is imported, the transistorized source of TFT/drain electrode is conducting during the selection of controlling grid scan line, so that the voltage data signal on the data scanning line is loaded into and the pixel electrode that drains and link to each other.
The process that voltage data signal is loaded into pixel electrode comprises: gate enable signal (generally adopting high level) is imported each controlling grid scan line in a certain order successively, after having imported gate enable signal on certain delegation's controlling grid scan line, this gate enable signal spare is input to the grid of the thin film transistor (TFT) that this row controlling grid scan line connected, thereby make the source electrode and the drain electrode conducting of corresponding thin film transistor (TFT), voltage data signal on the data scanning line is loaded into and the pixel electrode that drains and link to each other at this moment, realization is to the charging of liquid crystal capacitance and memory capacitance, wherein liquid crystal capacitance is the electric capacity that forms between the public electrode on pixel electrode and the color membrane substrates, and memory capacitance is the electric capacity that forms between the public electrode on pixel electrode and the tft array substrate.
When gate enable signal is input to the next line controlling grid scan line, the controlling grid scan line of previous row correspondingly cuts off gate enable signal, thereby disconnect thin film transistor (TFT) source electrode and drain electrode that the previous row controlling grid scan line is connected, and according to above-mentioned identical process voltage data signal is loaded on the pixel electrode of current controlling grid scan line correspondence, so that realize when the liquid crystal capacitance of previous row controlling grid scan line respective pixel and the charging of memory capacitance.
Because the gate enable signal that is input on the grid needs the regular hour to cut off, so there is time-delay in grid when cutting off gate enable signal, can make like this on the liquid crystal capacitance and memory capacitance that are carried in lastrow TFT of voltage data signal mistake of next line TFT, cause data load mistake and display abnormality phenomenon.In order to prevent the generation of this phenomenon, in the prior art when the grid of regulation lastrow TFT in the sequential control negative edge at gate enable signal with regard to early cut-off, so since the negative edge of gate enable signal before grid movable signal rising edge, thereby guaranteed to have cut off the gate enable signal of the grid of lastrow TFT before next line TFT grid input gate enable signal.
In the scheme process that adopts above-mentioned loading data signal voltage, the inventor finds that there are the following problems at least in the prior art:
Though the early cut-off gate enable signal can guarantee the normal load data, but the duration of grid enabling signal will shorten, cause the duration of charging of corresponding liquid crystal capacitance of every capable pixel and memory capacitance also to reduce thereupon, cause liquid crystal capacitance and memory capacitance charging insufficient, cause the generation of horizontal faint bright line, make picture quality descend.
The utility model content
Embodiment of the present utility model provides a kind of tft array substrate, makes liquid crystal capacitance and memory capacitance can access charging more fully.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
A kind of tft array substrate, comprise controlling grid scan line, data scanning line, described controlling grid scan line and data scanning line intersection define pixel cell, and comprise pixel electrode and pixel thin film transistor in each pixel cell, the grid of described pixel thin film transistor links to each other with controlling grid scan line, source electrode links to each other with the data scanning line, drain electrode links to each other with pixel electrode;
Every capable pixel cell also comprises at least one group of potential storage circuit, and every group of potential storage circuit comprises the pre-stored electric capacity and first switching thin-film transistor; The grid of described first switching thin-film transistor, source electrode link to each other with the corresponding controlling grid scan line of lastrow pixel cell, drain electrode links to each other with first electrode of described pre-stored electric capacity;
Described each pixel cell also comprises the second switch thin film transistor (TFT), and the grid of the described second switch thin film transistor (TFT) controlling grid scan line corresponding with its place pixel cell links to each other, source electrode links to each other with described pre-stored electric capacity first electrode with delegation, draining links to each other with the pixel electrode of its place pixel cell.
The tft array substrate that the utility model embodiment provides has increased at least one group first switching thin-film transistor and pre-stored electric capacity in every capable pixel cell, and has increased second switch thin film transistor (TFT) and pre-stored electric capacity in each pixel cell; Because the grid of first switching thin-film transistor has been connected to the grid of lastrow pixel cell correspondence, the source electrode sweep trace, so when gate enable signal is input to the controlling grid scan line of lastrow pixel cell correspondence, the source electrode of first switching thin-film transistor and drain electrode are conductings, first source electrode that closes thin film transistor (TFT) has been connected to controlling grid scan line simultaneously, drain electrode has been connected to pre-stored electric capacity, so, when the lastrow pixel cell shows, signal voltage on the controlling grid scan line can be loaded into pre-stored electric capacity equally, makes to store certain voltage on the pre-stored electric capacity.
Because the grid of second switch thin film transistor (TFT) has been connected to the controlling grid scan line of current line, when being input to the controlling grid scan line of current line when the gate enable signal on the controlling grid scan line that cuts off lastrow and with gate enable signal, the source electrode of first switching thin-film transistor and drain electrode are conductings; Because the source electrode of second switch thin film transistor (TFT) links to each other with the positive pole of described pre-stored electric capacity, draining links to each other with the pixel electrode of its place pixel cell, so, when gate enable signal is input to the controlling grid scan line of current line, voltage data signal on the data scanning line can be to the pixel electrode charging, and institute's stored voltage also can be charged to pixel electrode in the pre-stored electric capacity among the utility model embodiment.
So, adopting after the utility model embodiment, pixel electrode can be finished charging apace, even the duration of charging is shortened, can guarantee that still the charging of liquid crystal capacitance and memory capacitance is enough abundant, reduce the generation of horizontal faint bright line, improve quality of display pictures.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the schematic diagram of a kind of tft array substrate among the utility model embodiment 1;
Fig. 2 is the schematic diagram of another kind of tft array substrate among the utility model embodiment 1;
Fig. 3 is the partial top view of tft array substrate among the utility model embodiment 2;
Fig. 4 a is first process of tft array substrate manufacture method among the utility model embodiment 2;
Fig. 4 b is second process of tft array substrate manufacture method among the utility model embodiment 2;
Fig. 4 c is the 3rd process of tft array substrate manufacture method among the utility model embodiment 2;
Fig. 4 d is the 4th process of tft array substrate manufacture method among the utility model embodiment 2;
Fig. 4 e is the 5th process of tft array substrate manufacture method among the utility model embodiment 2;
Fig. 4 f is the 6th process of tft array substrate manufacture method among the utility model embodiment 2;
Fig. 5 is the cut-open view of another kind of FT array base palte among the utility model embodiment 2.
Embodiment
The utility model embodiment provides a kind of tft array substrate and manufacture method thereof, by in every capable pixel cell, having increased at least one group first switching thin-film transistor and pre-stored electric capacity, and second switch thin film transistor (TFT) and pre-stored electric capacity in each pixel cell, have been increased; Wherein, the grid of described first switching thin-film transistor and the corresponding grid of lastrow pixel cell, source electrode sweep trace link to each other, drain electrode links to each other with first electrode of described pre-stored electric capacity; The grid of the described second switch thin film transistor (TFT) controlling grid scan line corresponding with its place pixel cell links to each other, source electrode links to each other with described pre-stored electric capacity first electrode with delegation, draining links to each other with the pixel electrode of its place pixel cell.
After adopting such scheme, can be when the lastrow pixel shows at pre-stored capacitance stores voltage, and when the current line pixel shows, can charge to the pixel electrode of current line by the voltage of pre-stored capacitance stores, guarantee that the charging of liquid crystal capacitance and memory capacitance is enough abundant.
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
Embodiment 1:
All to make a second switch thin film transistor (TFT) in one group of first switching thin-film transistor and pre-stored electric capacity and each pixel be that example describes to present embodiment all to make in each pixel.
Fig. 1 is the partial schematic diagram in the utility model embodiment tft array substrate, two pixel cells of adjacent two row of expression among the figure, and delegation is the capable pixel of N above supposing, the following capable pixel of a behavior N+1; Comprise a pixel thin film transistor TFT in the capable pixel cell of N+1 among Fig. 1, the grid of this TFT is connected to that the capable controlling grid scan line of N+1, source electrode are connected to the data scanning line, drain electrode is connected to pixel electrode.
Also comprise the first switching thin-film transistor TFT1, second switch thin film transistor (TFT) TFT2 and pre-stored capacitor C in the pixel cell that N+1 is capable among Fig. 1
AAs shown in Figure 1, the grid of TFT1, source electrode are connected to drain electrode and the C of the capable controlling grid scan line of N, TFT1
ALink to each other; Simultaneously, the grid of TFT2 is connected to the capable controlling grid scan line of N+1, the source electrode of TFT2 and C
ALink to each other, the drain electrode of TFT2 is connected to liquid crystal capacitance C simultaneously
1cWith memory capacitance C
StBecause C
LcBe the electric capacity that forms between the public electrode on pixel electrode and the color membrane substrates, and C
STBe the electric capacity that forms between the public electrode on pixel electrode and the tft array substrate, so when practice, the drain electrode of TFT2 is connected to pixel electrode and gets final product.
The principle of work of tft array substrate is among Fig. 1:
When the capable pixel unit of scanning display panel N, when the grid enabling signal is input to the capable controlling grid scan line of N, in source electrode and the drain electrode while of conducting pixel thin film transistor (TFT) TFT, also conducting source electrode and the drain electrode of TFT1, voltage data signal on this moment data scanning line in liquid crystal capacitance capable and memory capacitance charging to N, the signal voltage on the controlling grid scan line also by TFT1 to C
ACharge.The pre-stored capacitor C
AThe setting of appearance value size and refreshing frequency, source signal line are relevant to the charge efficiency of memory capacitance.
When the grid enabling signal is input to the capable controlling grid scan line of N+1, in source electrode and the drain electrode while of conducting pixel thin film transistor (TFT) TFT, also conducting source electrode and the drain electrode of TFT2, so, voltage data signal on the data scanning line the liquid crystal capacitance capable to N+1 by pixel TFT and memory capacitance are charged, C
AIn stored voltage also can charge to N+1 capable liquid crystal capacitance and memory capacitance by TFT2, thereby accelerate speed that the capable liquid crystal capacitance of N+1 and memory capacitance are carried out charge charging.So, even the duration of charging is shortened, can guarantee still after the scheme of employing the utility model embodiment that the charging of liquid crystal capacitance and memory capacitance is enough abundant, reduce the generation of horizontal faint bright line, improve quality of display pictures.
By in each dot structure, said structure being set, just can repeating the above-mentioned course of work and make whole liquid crystal panel to charge to pixel electrode quickly.
Can when making pixel thin film transistor TFT, produce TFT1 and TFT2 among the utility model embodiment; TFT1, TFT2 are identical with principle of work and the implementation method of pixel thin film transistor TFT, that is to say, TFT1, TFT2 and pixel thin film transistor TFT can make by identical MASK (mask plate) technology and step, can simplify manufacture craft like this, guarantee under existing technology, to realize the function that the utility model is newly-increased.Particularly, situation about being produced on one deck includes but not limited to following sight:
The first, the grid of described first switching thin-film transistor and the grid and the described controlling grid scan line of described second switch thin film transistor (TFT) form on one deck, and form on one deck with pixel thin film transistor TFT grid.During concrete enforcement, after forming the grid metal level, etch pixel thin film transistor TFT grid, TFT1 grid, TFT2 grid and controlling grid scan line by same MASK technology.
The second, the source electrode of the source electrode of described first switching thin-film transistor and drain electrode and described second switch thin film transistor (TFT) and drain electrode and described data scanning line form on one deck, and form on one deck with pixel thin film transistor TFT source electrode and drain electrode.During concrete enforcement, behind formation source/leakage metal level, etch pixel thin film transistor TFT source electrode and drain electrode, TFT1 source electrode and drain electrode, TFT2 source electrode and drain electrode and data scanning line by same MASK technology.And the source electrode of described first switching thin-film transistor links to each other with the corresponding controlling grid scan line of lastrow pixel cell by via hole.
Three, link to each other with TFT1, TFT2 for the ease of pre-stored electric capacity, the utility model embodiment can also form first electrode of described pre-stored electric capacity and the drain electrode of described first switching thin-film transistor on one deck; Second electrode of described pre-stored electric capacity and the public electrode of image element circuit form on one deck, and second electrode of described pre-stored electric capacity links to each other with the public electrode of image element circuit.
Scheme among above-mentioned Fig. 1 is one group of described potential storage circuit of each pixel cell in every capable pixel cell, and the source electrode of the second switch thin film transistor (TFT) in described each pixel cell links to each other with pre-stored electric capacity first electrode of potential storage circuit in its place pixel cell; When practice, also can public same TFT1 of a plurality of pixel cells and pre-stored electric capacity, specifically referring to Fig. 2, that is: corresponding one group of described potential storage circuit (comprising TFT1 and pre-stored electric capacity) of at least two pixel cells in every capable pixel cell, and the source electrode of the second switch thin film transistor (TFT) in described at least two pixel cells links to each other with pre-stored electric capacity first electrode in the corresponding voltage memory circuit, and promptly the TFT3 among Fig. 2 is connected to C
A, so that C
ACan the pixel electrode of TFT3 place pixel cell be charged.
Clearly do not express TFT2 and pixel electrode ways of connecting in the above-mentioned scheme illustrated in figures 1 and 2, when specific implementation, the utility model embodiment provides but is not limited to following two kinds of connected modes:
1, the drain electrode of described second switch thin film transistor (TFT) TFT2 links to each other by the pixel electrode of contact hole with its place pixel cell, pixel electrode is equivalent on the passivation film above the TFT2 drain electrode, etch contact hole, so that can be connected to the TFT2 drain electrode by this contact hole; This connected mode does not need to increase MASK technology, as long as the contact hole above can TFT etching the TFT2 drain electrode in the contact hole above the drain electrode, and contacts by contact hole, can guarantee that TFT2 drains to be connected better with pixel electrode.
2, the drain electrode of described second switch thin film transistor (TFT) TFT2 is by the drain electrode of described pixel thin film transistor TFT, link to each other with the pixel electrode of its place pixel cell, this connected mode, can be less in the etching contact hole can contact hole, and do not need to change the mask plate that is adopted in the MASK technology.
Embodiment 2:
The utility model embodiment provides a kind of manufacture method of tft array substrate, when making pixel thin film transistor, form at least one group of potential storage circuit at every capable pixel cell, form the second switch thin film transistor (TFT) in controlling grid scan line and data scanning line intersect the pixel cell that defines, described every group of potential storage circuit comprises the pre-stored electric capacity and first switching thin-film transistor.
And the grid of first switching thin-film transistor of above-mentioned making, source electrode link to each other with the corresponding controlling grid scan line of lastrow pixel cell, drain electrode links to each other with first electrode of described pre-stored electric capacity.The grid of the second switch thin film transistor (TFT) of the above-mentioned making controlling grid scan line corresponding with its place pixel cell links to each other, source electrode links to each other with described pre-stored electric capacity first electrode with delegation, draining links to each other with the pixel electrode of its place pixel cell.
Be that example describes all to be manufactured with one group of potential storage circuit in each pixel cell below, as shown in Figure 3, partial top view for tft array substrate among the utility model embodiment, there is shown the approximate location of each thin film transistor (TFT) in pixel cell, during practice, the position of each thin film transistor (TFT) can be adjusted as required, as long as annexation satisfies requirement of the present utility model.Specifically referring to 4a to Fig. 4 e, Fig. 4 a to Fig. 4 e be in each manufacturing process along A-A among Fig. 3 to cut-open view, the manufacture method of tft array substrate comprises among the utility model embodiment:
1) substrate that adopts among the utility model embodiment is a glass substrate, shown in Fig. 4 a, and deposition grid metal level 41 on substrate 40.
2) described grid metal level 41 is carried out etching, thereby on substrate 40, form gate pattern and second electrode 52 that is positioned at the pre-stored electric capacity 50 of each pixel cell, specifically referring to Fig. 4 b.This gate pattern that forms in this process comprises the grid 61 of controlling grid scan line 42 (see figure 3)s, pixel thin film transistor 60, the grid 71 of first switching thin-film transistor 70, the grid 81 of second switch thin film transistor (TFT) 80.
The controlling grid scan line that the grid 61 of above-mentioned pixel thin film transistor 60 is corresponding with its place pixel cell links to each other, the grid 71 of first switching thin-film transistor 70 links to each other with the corresponding controlling grid scan line of lastrow pixel cell, and the controlling grid scan line that the grid 81 of second switch thin film transistor (TFT) 80 is corresponding with its place pixel cell links to each other.
3) shown in Fig. 4 c, on described substrate 40 with gate pattern, deposit grid insulating film 43, active film 44 successively.
4) described active film 44 is carried out etching and form active Thinfilm pattern with gate overlap, shown in Fig. 4 d, the active Thinfilm pattern that forms in this process comprise the active layer 62 overlapping with the grid 61 of pixel thin film transistor 60, with overlapping active layer 72 of the grid 71 of first switching thin-film transistor 70 and the active layer 82 overlapping with the grid 81 of second switch thin film transistor (TFT) 80.
5) shown in Fig. 4 d, the position corresponding to first switching thin-film transistor, 70 source electrodes 73 to be formed on the grid insulating film on the controlling grid scan line 42 of lastrow pixel cell forms via hole 76, and this via hole exposes described controlling grid scan line.
5) shown in Fig. 4 e, sedimentary origin on substrate 40/leakage metal level with active Thinfilm pattern, and etching forms source/leakage pattern, data scanning line 45 and first electrode 51 overlapping with second electrode 52 of described pre-stored electric capacity 50.The source that forms in this process/leakage pattern comprises: the source electrode 73 of source electrode of pixel thin film transistor 60 63 and drain electrode 64, first switching thin-film transistor 70 and drain 74, the source electrode 83 of second switch thin film transistor (TFT) 80 and drain 84; And the source electrode 63 of pixel thin film transistor 60 links to each other with data scanning line 45, the source electrode 73 of first switching thin-film transistor 70 by described via hole 76 controlling grid scan line corresponding with the lastrow pixel cell link to each other, drain electrode 73 links to each other with first electrode 51 of described pre-stored electric capacity 50, the source electrode 83 of second switch thin film transistor (TFT) 80 and first electrode 51 of described pre-stored electric capacity 50 link to each other, drain and 84 link to each other with the pixel electrode of its place pixel cell.
After adopting the manufacture method of the tft array substrate that the utility model embodiment provides, when the lastrow pixel cell showed, the voltage signal of controlling grid scan line can be loaded into pre-stored electric capacity equally, made to store certain voltage on the pre-stored electric capacity.Because the grid of second switch thin film transistor (TFT) has been connected to the controlling grid scan line of current line, when being input to the controlling grid scan line of current line when the gate enable signal on the controlling grid scan line that cuts off lastrow and with gate enable signal, the source electrode of first switching thin-film transistor and drain electrode are conductings; Because the source electrode of second switch thin film transistor (TFT) links to each other with the positive pole of described pre-stored electric capacity, draining links to each other with the pixel electrode of its place pixel cell, so, when gate enable signal is input to the controlling grid scan line of current line, voltage data signal on the data scanning line can be to the pixel electrode charging, and institute's stored voltage also can be charged to pixel electrode in the pre-stored electric capacity among the utility model embodiment.
So, adopting after the utility model embodiment, pixel electrode can be finished charging apace, even the duration of charging is shortened, can guarantee that still the charging of liquid crystal capacitance and memory capacitance is enough abundant, reduce the generation of horizontal faint bright line, improve quality of display pictures.
For the second switch thin film transistor (TFT) specific implementation that drain electrode links to each other with the pixel electrode of its place pixel cell is provided, shown in Fig. 4 e to Fig. 4 f, Fig. 4 f be in this manufacturing process along A-A among Fig. 3 to cut-open view, the manufacture method of the tft array substrate of the utility model embodiment also comprises:
6) deposition passivation film 46 on the substrate of formation source/leakage pattern, and on described passivation film 46, form contact hole 47, shown in Fig. 4 e, this contact hole 47 exposes the drain electrode 64 of pixel thin film transistor 60.
7) shown in Fig. 4 f, on described passivation film 46 with contact hole 47, form pixel electrode 48, described pixel electrode 48 is connected to the drain electrode 64 of pixel thin film transistor 60 through described contact hole 47, the drain electrode 84 of described second switch thin film transistor (TFT) 80 links to each other with the pixel electrode 48 of its place pixel cell by the drain electrode 64 of described pixel thin film transistor 60.
Except the scheme by Fig. 4 e and Fig. 4 f correspondence realizes being connected of the drain electrode of second switch thin film transistor (TFT) and pixel electrode, the other scheme of also providing the utility model embodiment realizes being connected of the drain electrode of second switch thin film transistor (TFT) and pixel electrode, specifically includes but not limited to following scheme:
At first, when making the drain electrode of drain electrode of second switch thin film transistor (TFT) and described pixel thin film transistor, both are disconnected.
Secondly, behind the deposition passivation film, have the passivation film of two contact holes in passivation film forms each pixel cell, one of them contact hole exposes the drain electrode of pixel thin film transistor, and another contact hole exposes the drain electrode of second switch thin film transistor (TFT).
At last, have at described each pixel cell on the passivation film of two contact holes and form pixel electrode, described pixel electrode is connected respectively to the drain electrode of pixel thin film transistor, the drain electrode of second switch thin film transistor (TFT) through described two contact holes.
Adopt aforesaid way can produce the realization sight that all comprises one group of potential storage circuit in each pixel cell, but during practice, in order to improve aperture ratio of pixels, need reduce the quantity of potential storage circuit as far as possible, so, the utility model embodiment also provides the scheme of the shared one group of potential storage circuit of a plurality of pixel cells, and the difference of the scheme of its specific implementation and Fig. 4 a to 4g is mainly as follows:
1, when the grid metal level on the substrate is carried out etching, need to form pre-stored electric capacity second electrode in gate pattern and every group of potential storage circuit corresponding, be equivalent to corresponding one group of potential storage circuit of at least two pixel cells with delegation with at least two pixel cells; This gate pattern comprises the grid of first switching thin-film transistor in the grid of grid, second switch thin film transistor (TFT) of controlling grid scan line, pixel thin film transistor and the described every group of potential storage circuit; And the controlling grid scan line that the grid of pixel thin film transistor is corresponding with its place pixel cell links to each other, the grid of first switching thin-film transistor links to each other with the corresponding controlling grid scan line of lastrow pixel cell, and the controlling grid scan line that the grid of second switch thin film transistor (TFT) is corresponding with its place pixel cell links to each other.
2, on grid insulating film, form in the active Thinfilm pattern, form with the active layer of the gate overlap of pixel thin film transistor, with the active layer of the gate overlap of first switching thin-film transistor and with the active layer of the gate overlap of second switch thin film transistor (TFT), wherein the active layer of the gate overlap of first switching thin-film transistor only is to need to make in the common one group of corresponding potential storage circuit of at least two pixel cells.
During 3, at formation source/leakage pattern, data scanning line and with first electrode of the overlapping pre-stored electric capacity of second electrode of described pre-stored electric capacity, the source electrode of first switching thin-film transistor and drain electrode only need be made in the common one group of corresponding potential storage circuit of at least two pixel cells.And the source electrode of pixel thin film transistor links to each other with the data scanning line, and the first switching thin-film transistor source electrode links to each other with the data scanning line in every group of potential storage circuit, drain electrode links to each other with first electrode of pre-stored electric capacity in the described potential storage circuit on the same group; Pre-stored electric capacity first electrode that second switch thin film transistor (TFT) source electrode is corresponding with the place pixel cell links to each other, drain electrode links to each other with the pixel electrode of its place pixel cell.
Make the tft array substrate that the utility model embodiment provides no matter adopt above-mentioned which kind of scheme, the drain electrode of first electrode of pre-stored electric capacity and described first switching thin-film transistor can be same conductor pole plate among the utility model embodiment, and second electrode of described pre-stored electric capacity and the drain electrode of described first switching thin-film transistor also can overlaids.
Way of realization for pre-stored electric capacity, the utility model embodiment can also adopt following scheme: as shown in Figure 5, in Fig. 5, when the source electrode 83 of second switch thin film transistor (TFT) 80 links to each other with first electrode 51 of described pre-stored electric capacity 50, the connecting line that is adopted also can be made into the metal level of broad, make this connecting line also can cross a part as first electrode 51, and be made into second electrode, 52 area coverages of pre-stored electric capacity 50 corresponding with first electrode, 51 areas, so that improve the capacity of pre-stored electric capacity, further accelerate the charging rate of next line pixel electrode.
The utility model embodiment mainly is used in display device and manufacturing process thereof, especially is used in tft array substrate and the manufacture process thereof.
The above; it only is embodiment of the present utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion by described protection domain with claim.
Claims (6)
1. tft array substrate, comprise controlling grid scan line, data scanning line, described controlling grid scan line and data scanning line intersection define pixel cell, and comprise pixel electrode and pixel thin film transistor in each pixel cell, the grid of described pixel thin film transistor links to each other with controlling grid scan line, source electrode links to each other with the data scanning line, drain electrode links to each other with pixel electrode; It is characterized in that:
Every capable pixel cell also comprises at least one group of potential storage circuit, and every group of potential storage circuit comprises the pre-stored electric capacity and first switching thin-film transistor; The grid of described first switching thin-film transistor, source electrode link to each other with the corresponding controlling grid scan line of lastrow pixel cell, drain electrode links to each other with first electrode of described pre-stored electric capacity;
Described each pixel cell also comprises the second switch thin film transistor (TFT), and the grid of the described second switch thin film transistor (TFT) controlling grid scan line corresponding with its place pixel cell links to each other, source electrode links to each other with described pre-stored electric capacity first electrode with delegation, draining links to each other with the pixel electrode of its place pixel cell.
2. tft array substrate according to claim 1 is characterized in that, the drain electrode of described second switch thin film transistor (TFT) links to each other with the pixel electrode of its place pixel cell by the drain electrode of described pixel thin film transistor; The drain electrode of perhaps described second switch thin film transistor (TFT) links to each other by the pixel electrode of contact hole with its place pixel cell.
3. tft array substrate according to claim 1 is characterized in that:
Corresponding one group of described potential storage circuit of at least two pixel cells in described every capable pixel cell, and the source electrode of the second switch thin film transistor (TFT) in described at least two pixel cells links to each other with pre-stored electric capacity first electrode in the corresponding voltage memory circuit; Perhaps
One group of described potential storage circuit of each pixel cell in described every capable pixel cell, and the source electrode of the second switch thin film transistor (TFT) in described each pixel cell links to each other with pre-stored electric capacity first electrode of potential storage circuit in its place pixel cell.
4. according to claim 1,2 or 3 described tft array substrates, it is characterized in that the grid and the described controlling grid scan line of the grid of described first switching thin-film transistor and described second switch thin film transistor (TFT) form on one deck.
5. according to claim 1,2 or 3 described tft array substrates, it is characterized in that the source electrode of the source electrode of described first switching thin-film transistor and drain electrode and described second switch thin film transistor (TFT) and drain electrode and described data scanning line form on one deck; And the source electrode of described first switching thin-film transistor links to each other with the corresponding controlling grid scan line of lastrow pixel cell by via hole.
6. according to claim 1,2 or 3 described tft array substrates, it is characterized in that first electrode of described pre-stored electric capacity and the drain electrode of described first switching thin-film transistor form on one deck; Second electrode of described pre-stored electric capacity and the public electrode of image element circuit form on one deck, and second electrode of described pre-stored electric capacity links to each other with the public electrode of image element circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011200011101U CN201909924U (en) | 2011-01-04 | 2011-01-04 | TFT (thin film transistor) array baseplate |
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| CN2011200011101U CN201909924U (en) | 2011-01-04 | 2011-01-04 | TFT (thin film transistor) array baseplate |
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| CN2011200011101U Expired - Lifetime CN201909924U (en) | 2011-01-04 | 2011-01-04 | TFT (thin film transistor) array baseplate |
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| Country | Link |
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| CN (1) | CN201909924U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102810304A (en) * | 2012-08-09 | 2012-12-05 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
| WO2019127665A1 (en) * | 2017-12-29 | 2019-07-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN107068690B (en) * | 2017-03-10 | 2020-02-21 | 京东方科技集团股份有限公司 | Array substrate, pixel electrode charging method of array substrate and display device |
| CN114974161A (en) * | 2022-06-16 | 2022-08-30 | 武汉华星光电技术有限公司 | Pixel driving circuit and display panel |
-
2011
- 2011-01-04 CN CN2011200011101U patent/CN201909924U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102810304A (en) * | 2012-08-09 | 2012-12-05 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
| CN102810304B (en) * | 2012-08-09 | 2015-02-18 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
| CN107068690B (en) * | 2017-03-10 | 2020-02-21 | 京东方科技集团股份有限公司 | Array substrate, pixel electrode charging method of array substrate and display device |
| WO2019127665A1 (en) * | 2017-12-29 | 2019-07-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114974161A (en) * | 2022-06-16 | 2022-08-30 | 武汉华星光电技术有限公司 | Pixel driving circuit and display panel |
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