CN201846483U - Underwater wireless sensor network (UWSN) node master control circuit based on DDS (Direct Digital Synthesis) technology - Google Patents
Underwater wireless sensor network (UWSN) node master control circuit based on DDS (Direct Digital Synthesis) technology Download PDFInfo
- Publication number
- CN201846483U CN201846483U CN2010206100763U CN201020610076U CN201846483U CN 201846483 U CN201846483 U CN 201846483U CN 2010206100763 U CN2010206100763 U CN 2010206100763U CN 201020610076 U CN201020610076 U CN 201020610076U CN 201846483 U CN201846483 U CN 201846483U
- Authority
- CN
- China
- Prior art keywords
- circuit
- dds
- master controller
- power supply
- sensor network
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Transducers For Ultrasonic Waves (AREA)
Abstract
The utility model relates to the technical field of wireless sensors, in particular to an underwater wireless sensor network (UWSN) node master control circuit based on DDS (Direct Digital Synthesis) technology. The UWSN node master control circuit comprises a power supply and power supply management circuit, a master controller and storage circuit, a clock circuit, a DDS waveform generation circuit, wherein the power supply and power supply management circuit is connected with the master controller and storage circuit; the clock circuit is connected with the master controller and storage circuit by a corresponding interface; and the DDS waveform generation circuit is connected with the master controller and storage circuit by a parallel interface PORTC. The UWSN node master control circuit is provided with an excellent power supply system is beneficial to normal work of the master control circuit, even a whole system; and the (UWSN) node master control circuit has the advantages of being capable of accurately and fast processing frequency and phases under the control of a digital processor, being good in the resolution ratio on the frequency and the phases, and being capable of realizing fast signal conversion.
Description
Technical field
The utility model relates to technical field of wireless, relates in particular to a kind of underwater wireless sensor network node governor circuit based on the DDS technology.
Background technology
Along with the develop rapidly of global land wireless sensor network, be that the underwater sensor network of transmission medium has obtained increasing attention and fund input gradually with the underwater ultrasound.(underwater acoustic sensor networks UWASN) has boundless application prospect to underwater sensor network, is applied in multiple Underwater Engineering and research field widely.Yet existing underwater sensor network and governor circuit thereof exist following shortcoming:
(1) underwater acoustic channel poor transmission: problems such as multipath, decay and Doppler frequency shift make the temporary disruption of error rate height, link of subsurface communication happen occasionally, and this is one of important difference of underwater sensor network and land on-air radio sensor network.
(2) battery is limited in one's ability: the network node of underwater sensor governor circuit carries the very limited battery of energy usually.Because underwater sensor node governor circuit distribution water surface zone is wide, and the underwater environment complexity, the network node governor circuit is not recovered usually, so the node governor circuit is unpractical by changing battery to replenish the energy.
(3) communication capacity is limited: underwater acoustic communication mainly is subjected to path loss, multipath, many ways, noise, Doppler frequency shift, propagation delay length and the variable influence of time-delay.
Above-mentioned these shortcomings are unfavorable for effective transmission of data, can't realize point-to-point reliably real time communication under water, thereby have reduced the practicality of distributed underwater wireless sensor network.
The utility model content
Technical problem at above-mentioned existence, the purpose of this utility model provides a kind of underwater wireless sensor network node governor circuit based on the DDS technology, overcome the governor circuit underwater acoustic channel poor transmission of existing underwater wireless sensor network, battery is limited in one's ability, the limited deficiency that waits of communication capacity.
For achieving the above object, the utility model adopts following technical scheme:
Power supply and electric power management circuit, master controller and memory circuit, clock circuit, DDS wave generator circuit;
Described power supply and electric power management circuit are connected with master controller and memory circuit; Described clock circuit is connected with master controller and memory circuit by the corresponding interface; Described DDS wave generator circuit is connected with master controller and memory circuit by parallel interface PORTC.
Described power supply and electric power management circuit have two kinds of pressurizers of LM2596-5V, TPS70351.
Described master controller and memory circuit have adopted the S3C2410 microprocessor of the ARM9 series of Samsung company.
Described clock circuit adopts special-purpose real-time calendar clock chip PCF8563.
The utlity model has following advantage and good effect:
1) the utlity model has good power-supply system, help the operate as normal of governor circuit and even whole system;
2) S3C2410 of the present utility model provides the ancillary equipment of the more complete general-purpose system of a cover, and it is minimum to make that whole system consumes, and has removed the trouble of adding the configuration optional equipment from;
3) the utility model is on this underwater wireless sensor network node governor circuit, the bank0 of S3C2410 has distributed to Norflash, bank3 has distributed to ethernet controller equipment, bank6 has distributed to SDRAM, other space is unallocated, expands external equipment to the user and leaves very big leeway;
4) the utility model K9F1208 is the bigger Flash chip of capacity, can provide to widely apply the software support;
5) the utility model has increased the real-time calendar clock chip of a special use, and it has low-down power consumption, even system's power down also can work under correct calendar time, thereby can not cause losing of system time;
6) the utility model DDS technology has the advantage that can accurately and apace handle frequency and phase place under the control of digital processing unit, and frequency and phase resolution are fairly good, can carry out signal transformation fast, DDS module of the present utility model can produce all stable ultrasonic signal of frequency plot, satisfies the requirement of high speed switching signal frequency.
Description of drawings
Fig. 1 is a network node schematic block circuit diagram of the present utility model.
Fig. 2 is power supply of the present utility model and electric power management circuit figure.
Fig. 3 is a SDRAM circuit diagram of the present utility model.
Fig. 4 is a SD card module circuit diagram of the present utility model.
Fig. 5 is PCF8563 real-time clock of the present utility model and cpu i/f schematic diagram.
Fig. 6 is the DDS module circuit diagram of AD9850 of the present utility model.
Embodiment
The utility model adopts digital form to carry out the generation of signal, with DDS(Direct Digital Synthesis, Direct Digital is synthetic) as underwater ultrasound communication signal source, produce all stable ultrasonic signal of frequency plot to reach, and can satisfy the requirement of high speed switching signal frequency, can make more energy be placed on to received signal processing aspect by the expense of simplifying signal generation aspect, have advantages such as low error rate, low energy consumption, high communication success rate and simplification channel overhead, simultaneously, for expanding external equipment, the user leaves very big leeway.
The utility model is described in further detail in conjunction with the accompanying drawings with specific embodiment below:
The underwater wireless sensor network node governor circuit that the utility model proposes based on the DDS technology, specifically adopted following technical scheme, referring to Fig. 1, this governor circuit is by power supply and electric power management circuit, master controller and memory circuit, clock circuit and DDS wave generator circuit.
Wherein, power supply and electric power management circuit are connected with master controller and memory circuit; Clock circuit is connected with master controller and memory circuit by the corresponding interface; The DDS wave generator circuit is connected with master controller and memory circuit by parallel interface PORTC.
The network node circuit board is the multi-layer sheet cascade structure: comprise network node base version and digital processing plate.Wherein the network node substrate is mainly used to realize transmitting-receiving, the forwarding of data of ultrasonic signal, the functions such as management of power supply; The digital processing plate is mainly used to carry out the realization of storage and procotol.
Power supply in the utility model and electric power management circuit, its concrete scheme be referring to Fig. 2, and the numerical portion of node has and adopts 3 kinds of voltages to exist, and 5V, 3.3V, DC power supply are l.8V arranged.This circuit has two kinds of pressurizers of LM2596-5V, TPS70351.LM2596-5V is the supply power voltage to DDS chip AD9850, and it is the needed voltage of S3C2410 master controller that TPS70351 provides 3.3V and 1.8V.And RTC (real-time clock) works on after considering the development board outage, so adopt the power supply separately of lithium battery decompression back.Power supply and electric power management circuit are connected with master controller and memory circuit.
Master controller in the utility model and memory circuit, the S3C2410 microprocessor of ARM9 series that has adopted Samsung company is as core processor, it is the five-stage pipeline structure, and the performance of 1.1MIPS/MHz is provided, and is the hard macrocell of high-performance and low-power consumption.ARM920T has MMU, instruction and data Cache and the high speed AMBA bus interface of full performance.The S3C2410 processor can carry out addressing to 9 bank, and every bank maximum space is 128M; For processor is not disturbed mutually to the visit of each equipment, can be in different bank with inhomogeneous device map.On this network node of underwater sensor governor circuit, the S3C2410 microprocessor is except having distributed to Norflash with bank0, and bank3 has distributed to ethernet controller equipment, and bank6 has distributed to SDRAM, other space is unallocated, expands external equipment to the user and leaves very big leeway.Core processor is mainly used to realize the coding and the conversion of signal, and the control of DDS module receives Signal Processing and decoding, the configuration of power output and multiplication factor etc.
Master controller in the utility model and memory circuit, the HY57V561620 chip that has adopted Hynix is as the SDRM memory access.The S3C2410 core board comprises 64MB SDRAM, is used for the setting program storehouse and deposits purposes such as various variablees.SDRAM memory parallel connection by two 16 bit data width is the SDRAM storage system of 32 bit data width, and is mapped to S3C2410 BANK6, and address realm is 0x3000-0000～0x33FF-FFFF.The HY57V561620 chip that is adopted is to have 268,435, and the synchronous dram chip of the cmos circuit of 456bit capacity is mainly used in the system environments of high power capacity and big data bandwidth, sees Fig. 3, and its inside is by 44,194, and the unit of 304 * 16bit constitutes.The Burst read-write operation of this chip support 1,2,4,8 or whole page or leaf, its input and output level is with LVTTL level compatibility.The SDRM memory access is connected with the S3C2410 microprocessor by the corresponding interface.
Master controller in the utility model and memory circuit, the K9F1208 that has adopted the production of Samsung company is as the Flash memory access.S3C2410 the is built-in interface of NandFlash, itself is also supported to power on and is directly started from NandFlash simultaneously.K9F1208 is big capacity, the highly reliable Flash memory that adopts the Nand technology, can be the user support of extensive application software is provided.This device stores capacity is 64M * 8, in addition also has the free storage of 2048K * 8.It is 200 μ s to the write operation required time representative value of 528 byte one pages, and the erase operation typical case of one of 16K byte is only needed 2ms.8 I/O ports adopt address, data and the multiplexing method of order.In addition, this a Flash data are the longest can preserve 10 years.The Flash memory access is connected with the S3C2410 microprocessor by the corresponding interface.
Master controller in the utility model and memory circuit have adopted the SD card to do to be mass storage, use the file format of FAT16.Thereby satisfy storage administration requirement, see Fig. 4 heap file.The SD card module is connected with the S3C2410 microprocessor by the corresponding interface.
Clock circuit in the utility model has adopted the real-time calendar clock of chip PCF8563 as a special use.It has low-down power consumption, keeps only 0.luA of electric current, and common button cell just can be kept its clock operation at least one year.Power at system board, when the program kernel starts, the time that it allows CPU read PCF8563 is then with the time deinitialization clock that reads.Like this, whole system just can work under correct calendar time, thereby can not cause losing of system time, sees Fig. 5.Clock circuit is connected with master controller and memory circuit by the corresponding interface.
DDS wave generator circuit in the utility model, adopted AD9850 as supersonic signal generator, control the analogue transmission that AD9850 carries out ultrasonic signal by S3C2410, to reach the requirement that produces all stable ultrasonic signal of frequency plot and satisfy high speed switching signal frequency.AD9850 is a high integration DDS frequency synthesizer, and his inside comprises DDS able to programme system, high-performance DAC and tells comparator, can realize the frequency synthesizer and the clock generator of digital programming Control.Connect the precision interval clock source, AD9850 can produce that frequency spectrum is pure, frequency and all analog sine output of control able to programme of phase place.This sine wave can directly be used as frequency signal source or convert square wave to and export as clock.The control of AD9850 interface is simple, and performance is higher, and power consumption is few.AD9850 adopts 32 phase accumulators, blocks into 14, the input sine look up table, and question blank output is blocked into 10, is input to DAC.Analog current is starved in two complementations of DAC output, receives on the filter.Regulate DAC full scale output current, need an external resistance R set, it regulates relational expression Iset=32 (1.248V/Rset), and the full scale electric current is 10 ~ 20mA, sees Fig. 6.The DDS wave generator circuit is mainly used to realize the generation of signal, produce the sine wave of corresponding frequencies, and the offset of sinusoidal ripple adds up accordingly, filtering, obtains required ultrasonic primary signal.DDS is connected with master controller and memory circuit by parallel interface PORTC.
Above embodiment is only for the usefulness that the utility model is described; but not to restriction of the present utility model; person skilled in the relevant technique; under the situation that does not break away from spirit and scope of the present utility model; can also make various conversion or modification; therefore all technical schemes that are equal to all fall into protection range of the present utility model.
Claims (5)
1. underwater wireless sensor network node governor circuit based on the DDS technology is characterized in that comprising:
Power supply and electric power management circuit, master controller and memory circuit, clock circuit, DDS wave generator circuit;
Described power supply and electric power management circuit are connected with master controller and memory circuit; Described clock circuit is connected with master controller and memory circuit by the corresponding interface; Described DDS wave generator circuit is connected with master controller and memory circuit by parallel interface PORTC.
2. the underwater wireless sensor network node governor circuit based on the DDS technology according to claim 1 is characterized in that:
Described power supply and electric power management circuit have two kinds of pressurizers of LM2596-5V, TPS70351.
3. the underwater wireless sensor network node governor circuit based on the DDS technology according to claim 1 is characterized in that:
Described master controller and memory circuit have adopted the S3C2410 microprocessor of the ARM9 series of Samsung company.
4. the underwater wireless sensor network node governor circuit based on the DDS technology according to claim 1 is characterized in that:
Described clock circuit adopts special-purpose real-time calendar clock chip PCF8563.
5. the underwater wireless sensor network node governor circuit based on the DDS technology according to claim 1 is characterized in that:
Described DDS wave generator circuit adopts AD9850 as supersonic signal generator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206100763U CN201846483U (en) | 2010-11-17 | 2010-11-17 | Underwater wireless sensor network (UWSN) node master control circuit based on DDS (Direct Digital Synthesis) technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206100763U CN201846483U (en) | 2010-11-17 | 2010-11-17 | Underwater wireless sensor network (UWSN) node master control circuit based on DDS (Direct Digital Synthesis) technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201846483U true CN201846483U (en) | 2011-05-25 |
Family
ID=44041356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206100763U Expired - Fee Related CN201846483U (en) | 2010-11-17 | 2010-11-17 | Underwater wireless sensor network (UWSN) node master control circuit based on DDS (Direct Digital Synthesis) technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201846483U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386891A (en) * | 2011-07-06 | 2012-03-21 | 河海大学常州校区 | Handheld low-power-consumption broadband DDS (Direct Digital Synthesizer) signal source |
| CN103148846A (en) * | 2013-02-25 | 2013-06-12 | 哈尔滨工业大学 | Micromechanical gyroscope driving device based on arbitrary waveform of DDS (Direct Digital Frequency Synthesizer) |
-
2010
- 2010-11-17 CN CN2010206100763U patent/CN201846483U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386891A (en) * | 2011-07-06 | 2012-03-21 | 河海大学常州校区 | Handheld low-power-consumption broadband DDS (Direct Digital Synthesizer) signal source |
| CN102386891B (en) * | 2011-07-06 | 2014-01-15 | 河海大学常州校区 | Handheld low-power-consumption broadband DDS (Direct Digital Synthesizer) signal source |
| CN103148846A (en) * | 2013-02-25 | 2013-06-12 | 哈尔滨工业大学 | Micromechanical gyroscope driving device based on arbitrary waveform of DDS (Direct Digital Frequency Synthesizer) |
| CN103148846B (en) * | 2013-02-25 | 2015-03-18 | 哈尔滨工业大学 | Micromechanical gyroscope driving device based on arbitrary waveform of DDS (Direct Digital Frequency Synthesizer) |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201708773U (en) | Arbitrarywaveform generator | |
| CN202453864U (en) | Large-capacity asynchronous first in first out (FIFO) buffer memory based on field programmable gate array (FPGA) and double data rate (DDR) 2 synchronous dynamic random access memory (SDRAM) | |
| CN102801593B (en) | Field programmable gate array (FPGA) and advanced RISC machine (ARM)-based data transmission method and system | |
| CN103810126A (en) | Mixed DRAM storage and method of reducing refresh power consumption of DRAM storage | |
| CN201846483U (en) | Underwater wireless sensor network (UWSN) node master control circuit based on DDS (Direct Digital Synthesis) technology | |
| CN203720359U (en) | Multi-mode multi-band continuous operational reference system (CORS) datum reference station based on advanced RISC machines 9 (ARM9) | |
| CN113281610A (en) | Electric power traveling wave fault location system | |
| CN102468829B (en) | A kind of signal generator and wave table recombination method thereof | |
| CN103792551A (en) | Multimode multi-frequency CORS standard reference station based on ARM9 | |
| CN103368974A (en) | Device for supporting IEC61850 protocol based on FPGA (Field Programmable Gata Array) | |
| CN208924395U (en) | A kind of super low-power consumption lora- serial ports transparent transmission conversion module | |
| CN213545067U (en) | Low-power consumption underwater acoustic signal processing board | |
| CN108733135A (en) | Extremely low power dissipation real time clock circuit and control method | |
| CN203178411U (en) | Collection system for partial discharge array signals | |
| CN205160205U (en) | Terminal is optimized in monitoring of distribution transformer operating mode and power consumption monitoring | |
| CN209659298U (en) | 9kHz-6GHz radio-frequency signal source intermediate frequency hardware system and device | |
| CN201060393Y (en) | 8 bit online debugging microcontroller | |
| CN204596096U (en) | A kind of preventing child of solar cell for supplying power is wandered away system | |
| CN202502613U (en) | Building energy consumption data collector | |
| CN204833088U (en) | Be applied to multi -functional embedded mainboard of engineering geophysics instrument | |
| CN201673429U (en) | Integrated circuit used for wave beam control | |
| CN105630400A (en) | High-speed massive data storage system | |
| CN105791770A (en) | ARM9-based embedded video acquisition system | |
| CN107272868A (en) | Low-power consumption RDSS baseband chips | |
| CN205945693U (en) | Superelevation frequency stability's simulation temperature compensated crystal oscillat |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110525 Termination date: 20111117 |