CN103810126A - Mixed DRAM storage and method of reducing refresh power consumption of DRAM storage - Google Patents

Mixed DRAM storage and method of reducing refresh power consumption of DRAM storage Download PDF

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Publication number
CN103810126A
CN103810126A CN201410040107.9A CN201410040107A CN103810126A CN 103810126 A CN103810126 A CN 103810126A CN 201410040107 A CN201410040107 A CN 201410040107A CN 103810126 A CN103810126 A CN 103810126A
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dram
memory
primary memory
time
storage unit
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CN103810126B (en
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景蔚亮
陈邦明
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Shanghai Xinchu Integrated Circuit Co Ltd
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Shanghai Xinchu Integrated Circuit Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a mixed DRAM storage and method of reducing refresh power consumption of the DRAM storage. A non-volatile storage is combined with a DRAM main storage, a specified storage cell of the non-volatile storage is used to replace a tail end storage cell of the DRAM main storage, so that a refresh cycle is greatly improved, refresh rate is reduced, and refresh power consumption of the DRAM main storage is reduced greatly.

Description

The method of power consumption when mixing DRAM storer and reducing this DRAM memory refress
Technical field
The present invention relates to semiconductor devices and technical field of integrated circuits, a kind of method of power consumption when being specifically related to the DRAM of mixing storer and reducing this DRAM memory refress.
Background technology
In the past few decades, the cost of dynamic RAM (DRAM) is along with Moore's Law constantly reduces.But along with characteristic dimension is more and more less, chip is also more and more higher to the requirement of power consumption, due to the electric leakage of DRAM memory capacitance, therefore must just refresh once at set intervals, and strengthen the power consumption that refreshes, as shown in Figure 1, the DRAM that capacity is less refreshes power consumption can be lower, only account for less a part of power consumption, but along with DRAM capacity becomes large, refresh power consumption and significantly raise, this is because feature size downsizing, other part change of power consumption of DRAM are not obvious, but very large to capacitive effect, therefore refresh power consumption and significantly improve; Therefore the power consumption that refreshes that how to reduce DRAM is problem demanding prompt solution.
In the last few years, some novel DRAM structures or storage medium were suggested to solve the defect of current DRAM technology.IBM Corporation advocates to be combined with DRAM and to form a kind of mixing memory with nonvolatile memory phase transition storage (PCM).Although PCM is nonvolatile memory, and power consumption is very low, and because the PCM write time is relevant with write data, therefore the access speed of PCM is not as good as DRAM, and PCM has the restriction of writing indegree.For the advantage separately in conjunction with the two, a kind of primary structure of solution, Fig. 2 a kind ofly utilizes nonvolatile memory to be combined with DRAM to form the structural representation of mixing memory; As shown in Figure 2, wherein (1) is processor, and mixing memory comprises DRAM buffer memory, and (3) PCM primary memory and (4) PCM write tfi module.In figure, can find out, DRAM is only as Cache, and buffer memory most recently used information, only has when needed and just data are stored in PCM.Because DRAM is just as buffer memory, capacity does not need very large, PCM as primary storage medium storage when data without periodic refreshing, therefore this structure can reduce the power consumption of data storage greatly, but due to PCM storage and reading speed slower, therefore this structure on overall performance obviously decline.Fig. 3 is that another kind utilizes nonvolatile memory to be combined with DRAM to form the structural representation of mixing memory; As shown in Figure 3, wherein (1) is processor, and mixing memory comprises DRAM primary memory, nonvolatile memory and (6) reserve battery.In the time of normal use, DRAM is still main storage medium, once power down, large battery for subsequent use will store the data in DRAM in nonvolatile memory into rapidly.While powering on again, data can return in DRAM automatically from nonvolatile memory.Although this structure has solved DRAM volatility issues, the power consumption producing while still not reducing the regular refresh data of DRAM, and cost also improves greatly.
Micron Technology (Micron) has proposed a kind of mixing storage cubic structure (HMC, Hybrid Memory Cube), the 3-D technology that it connects based on a kind of silicon through hole (TSV, Through-Silicon Vias).Fig. 4 is planar structure schematic diagram between layers in traditional DRAM; As shown in Figure 4, DRAM is planar structure between layers, connects between layers by PAD, takies ample resources.If processor wants to access the data of DRAM layer 9, just must through other DRAM layers, for example, pass through DRAM layer 2, DRAM layer 5, DRAM layer 8 could arrive DRAM9, waste plenty of time and power consumption.HMC structure as shown in Figure 5, DRAM is spatial structure between layers, and connect by silicon through hole (TSV), without PAD, saved a large amount of areas, and greatly shorten the access time, for example, while accessing DRAM layer 4, without through other DRAM layers, directly addressable by TSV, significantly reduced power consumption, the performance of device is greatly enhanced.But this structure is very high to technological requirement, cost increases, and DRAM still needs periodic refreshing, refreshes power consumption and does not still reduce.
Chinese patent (publication number: CN101216751B) discloses a kind of DRAM device with data-handling capacity based on distributed store structure, comprise: memory device interface, control interface, processing unit, DRAM memory bank, communication network, DRAM bank controller, dma controller, memory device interface is used for and external memory bus interaction data, be connected with DRAM memory controller and dma controller in device simultaneously, dma controller, processing unit is connected by communication network with DRAM bank controller, inner DRAM bank controller also connects inner DRAM storer simultaneously.The advantage of this invention is other hardware in data handling system not to be changed, can be used as normal memory uses, also can utilize programmed control to there is the data processing unit of the memory storage of data-handling capacity, accelerate to process to installing inner data, play the effect that significantly improves whole data handling system performance.
Chinese patent (publication number: CN1424658A) discloses a kind of flash memory device and method for designing thereof, that use dynamic RAM is that DRAM memory chip is as storage medium and method for designing thereof, adopt the measure of reduction power consumption to make the power-dissipation-reduced of memory chip to acceptable scope, use external power supply to power for memory chip, carry out exchanges data by external interface and host.Said flash memory device at least comprises: the memory interface of the DRAM memory chip that (a) is used for connecting storage data; (b) be used for connecting and host carries out the outer interface controller of the general channels of communication; (c) external direct current power supply being used for as DRAM memory chip power supply; (d) be used for the microprocessor of managing access to data and host communication; (e) be used for reducing the software and hardware method of power consumption into memory chip; (f) file storage structure of applicable memory chip access data.Compared with prior art, the flash memory device of this invention has that cost is lower, capacity is larger, speed is faster, the easy feature of upgrading, longer service life.
Summary of the invention
A kind of DRAM of mixing storer disclosed by the invention and the method for power consumption while reducing this DRAM memory refress, by nonvolatile memory is combined with DRAM primary memory, and utilize the storage unit of specifying in nonvolatile memory to substitute the tail end storage unit in DRAM primary memory, thereby greatly improve the refresh cycle, reduce refreshing frequency, greatly reduced the power consumption that refreshes of DRAM primary memory.
The present invention has recorded a kind of mixing DRAM storer, wherein, comprises DRAM primary memory, nonvolatile memory and logic detection module;
Described DRAM primary memory is connected with the two-way communication of described logic detection module, and described DRAM primary memory is connected with described nonvolatile memory two-way communication, and described logic detection module is connected with described nonvolatile memory two-way communication;
Wherein, described logic detection module detects the duty of described DRAM primary memory, and the operating state data obtaining according to it arranges tail end storage unit and main memory unit in described DRAM primary memory, set the refresh cycle of described DRAM primary memory according to this operating state data, and described logic detection module is controlled the data transmission between described DRAM primary memory and described nonvolatile memory according to the refresh cycle of setting simultaneously.
Above-mentioned mixing DRAM storer, wherein, is provided with several storage unit in described DRAM primary memory, and is preset with an interval time;
Described logic detection module keeps the time of data to detect to each described storage unit every interval time described in one, and the described storage unit detecting according to it keeps the time of data that described storage unit is divided into described tail end storage unit and described main memory unit.
Above-mentioned mixing DRAM storer, wherein, the refresh cycle of described DRAM primary memory comprises the first refresh time and the second refresh time.
Above-mentioned mixing DRAM storer, wherein, described the first refresh time is greater than the second refresh time, and this first refresh time is not more than the time that described main memory unit keeps data.
Above-mentioned mixing DRAM storer, wherein, described logic detection module detects in real time frequency of access and the refreshing frequency of described DRAM primary memory, and the frequency of access detecting according to it and refreshing frequency judge the duty of described DRAM primary memory.
Above-mentioned mixing DRAM storer, wherein, the duty of described DRAM primary memory comprises busy state and idle condition;
When described frequency of access is more than or equal to described refreshing frequency, described DRAM primary memory is in busy state;
When described frequency of access is less than described refreshing frequency, described DRAM primary memory is in idle condition.
Above-mentioned mixing DRAM storer, wherein, in the time that the duty of described DRAM primary memory is idle condition, described in described logic detection module controls, nonvolatile memory substitutes described tail end storage unit and reads and store data manipulation, and the refresh cycle that described logic detection module is set described DRAM primary memory is the first refresh time;
In the time that the duty of DRAM primary memory is converted to busy state from idle condition, described in described logic detection module controls, data transmission is returned described DRAM primary memory by nonvolatile memory, and the refresh cycle that described logic detection module is set described DRAM primary memory is the second refresh time.
The present invention has also recorded a kind of method that reduces power consumption while mixing DRAM memory refress, wherein, be applied to and in the claims 1~7, described in any one, mix DRAM storer, this storer comprises DRAM primary memory, nonvolatile memory and logic detection module, described DRAM primary memory comprises tail end storage unit and main memory unit, and concrete grammar is as follows:
Described logic detection module is determined tail end storage unit and the main memory unit in described DRAM primary memory;
In the time that the duty of described DRAM primary memory is idle condition, described in described logic detection module controls, nonvolatile memory substitutes described tail end storage unit and reads and store data manipulation, and the refresh cycle that described logic detection module is set described DRAM primary memory is the first refresh time;
In the time that the duty of DRAM primary memory is converted to busy state from idle condition, described in described logic detection module controls, data transmission is returned described DRAM primary memory by nonvolatile memory, and the refresh cycle that described logic detection module is set described DRAM primary memory is the second refresh time.
When above-mentioned reduction mixing DRAM memory refress, the method for power consumption, wherein, is provided with several storage unit in storer, and is preset with an interval time;
Described logic detection module keeps the time of data to detect to each described storage unit every interval time described in one, and the described storage unit detecting according to it keeps the time of data that described storage unit is divided into described tail end storage unit and described main memory unit.
The method of power consumption when above-mentioned reduction mixing DRAM memory refress, wherein, the refresh cycle of described DRAM primary memory comprises the first refresh time and the second refresh time.
The method of power consumption when above-mentioned reduction mixing DRAM memory refress, wherein, described the first refresh time is greater than the second refresh time, and this first refresh time is not more than the time that described main memory unit keeps data.
The method of power consumption when above-mentioned reduction mixing DRAM memory refress, wherein, the duty of described DRAM primary memory comprises busy state and idle condition;
When described frequency of access is more than or equal to described refreshing frequency, described DRAM primary memory is in described busy state;
When described frequency of access is less than described refreshing frequency, described DRAM primary memory is in described idle condition.
The present invention has following technical advantage:
1, by conjunction with nonvolatile memory and dynamic RAM, can improve the refresh cycle of dynamic RAM, thereby greatly reduce the power consumption that dynamic RAM produces.
2, utilize nonvolatile memory to substitute tail end storage unit, thereby greatly improve the refresh cycle, lower refreshing frequency, greatly reduce the power consumption that refreshes of dynamic RAM, and the performance of dynamic RAM is influenced hardly.
Accompanying drawing explanation
The accompanying drawing that forms a part of the present invention is used to provide a further understanding of the present invention, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is current and following DRAM capacity and refreshes power consumption, the non-power dissipation ratio illustration intention that refreshes;
Fig. 2 a kind ofly utilizes nonvolatile memory to be combined with DRAM to form the structural representation of mixing memory;
Fig. 3 is that another kind utilizes nonvolatile memory to be combined with DRAM to form the structural representation of mixing memory;
Fig. 4 is planar structure schematic diagram between layers in traditional DRAM;
Fig. 5 is mixing memory cube (HMC) structural representation that Micron Technology proposes;
Fig. 6 is tail end storage unit and the schematic diagram of main memory unit retention time in DRAM;
Fig. 7 is the present invention's mixing DRAM memory construction schematic diagram;
Fig. 8 is the schematic diagram that in DRAM storer, tail end storage unit and main memory unit changed with service time;
Fig. 9 is the process flow diagram that the present invention's mixing DRAM memory function is realized;
Figure 10 is the embodiment of the present invention three structural representations;
Figure 11 is refresh cycle contrast schematic diagram in embodiment tri-;
Figure 12 is the embodiment of the present invention four structural representations;
Figure 13 is prior art refresh cycle schematic diagram in embodiment tetra-;
Figure 14 is the refresh cycle schematic diagram of embodiment tetra-;
Figure 15 is the structural representation of existing hard disk;
Figure 16 is the structural representation of the present embodiment hard disk.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the content of mentioning specially below, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
The distribution that the present invention is based on the retention time of DRAM data proposes a kind of DRAM of mixing storer.The retention time (retention time) of data has directly determined the refresh cycle of DRAM storer.Research shows, the time that the storage unit in DRAM primary memory keeps according to data is divided into two parts, and a part is main memory unit, and another part is tail end storage unit, and Fig. 6 is tail end storage unit and main memory unit retention time schematic diagram in DRAM; As shown in Figure 6, the time of the maintenance data of main memory unit can reach the even longer time of 1s, is tail end storage unit and only have the storage unit of less than 1%, and the time of their maintenance data is lower than 1s, even less than 100ms.But determine the DRAM memory refress time keep exactly the poorest tail end storage unit of data capability (tail bit).DRAM primary memory refresh time can reach 64ms at present, now just progressively stride forward to the target of 128ms, but due to technological problems, allow retention time of all storage unit all reach this target very difficult, this also causes many DRAM storer factory costs greatly to improve, and directly causes many DRAM storeies factory to go bankrupt one after another.Along with DRAM memory span is done larger and larger, DRAM memory refress power consumption is also always high.
Embodiment mono-
Although tail end storage unit keeps the non-constant of ability of data, exceed more than storage unit retention time of 99% but can reach 1s.Based on above analysis, the present invention proposes a kind of structure of the DRAM of mixing storer, and Fig. 7 is the present invention's mixing DRAM memory construction schematic diagram, as shown in Figure 7, described mixing DRAM storer comprises a DRAM primary memory, nonvolatile memory and logic detection module, described DRAM primary memory is connected with the two-way communication of described logic detection module, can detect the working of DRAM primary memory, such as frequency of access and the refreshing frequency of DRAM primary memory, if frequency of access is more than or equal to refreshing frequency, show that DRAM primary memory is in busy state, DRAM primary memory moves with former refresh mode, refresh cycle is the second refresh time, now logic detection module regularly detects the duty of DRAM primary memory, if refreshing frequency is greater than frequency of access, surface DRAM is in idle condition, DRAM primary memory will move with low-power consumption refresh mode, refresh cycle is the first refresh time, entering before low-power consumption refresh mode, logic detection module mainly completes following operation: first, in DRAM primary memory, be provided with several storage unit, logic detection module is set to an interval time, logic detection module keeps the time of data to detect to each storage unit every an interval time, and the storage unit detecting according to it keeps the time of data that storage unit is divided into tail end storage unit and main memory unit.
Secondly, determine the tail end storage unit and the main memory unit that are arranged in DRAM primary memory, moreover, two-way communication is connected DRAM primary memory with nonvolatile memory, the data of tail end storage unit and nonvolatile memory can be transmitted mutually, by in the data write non-volatile memory of tail end cell stores in DRAM primary memory, logic detection module controls nonvolatile memory substitutes tail end storage unit and reads and store data, then, logic detection module can be according to the boundary of the retention time of the retention time of main memory unit and afterbody storage unit, DRAM primary memory is set to the first refresh time, the first refresh time is greater than the second refresh time, be less than the retention time of main memory unit, if carry the information of poor storage unit in DRAM primary memory, it comprises that tail end storage unit distributes and the boundary of the retention time of tail end storage unit and main memory unit, logic detection module can be directly by the data write non-volatile memory of tail end cell stores in DRAM primary memory so, described in described logic detection module controls, nonvolatile memory substitutes described tail end storage unit and reads and store data, and DRAM primary memory is set to the first refresh time.
Because DRAM primary memory is elongated service time, the hydraulic performance decline of device, electric capacity keeps data capability also to decline gradually, in Fig. 6 the distributive province of tail end storage unit and main memory unit can entirety to left, Fig. 8 be in DRAM storer tail end storage unit and main memory unit with the schematic diagram of variation service time; As shown in Figure 8, tail end storage unit increases, and the retention time of DRAM primary storage device also reduces.Therefore logic detection module can be according to the boundary of the retention time of the retention time of upgrading main memory unit interval time setting and afterbody storage unit; For example when electricity under system, reset tail end storage unit and main memory unit in DRAM primary memory, thereby the storage unit that logic detection module resets in nonvolatile memory substitutes newly-increased tail end storage unit, then guarantee the first refresh time, also or reset the first refresh time.
For the nonvolatile memory of low capacity, logic detection module only can realize with state machine; For the larger nonvolatile memory of capacity, logic detection module can adopt the microcontroller (MCU) that large capacity nonvolatile memory carries to realize, thereby saves cost; Above-mentioned nonvolatile memory can be selected flash memory, phase transition storage PCM, ferroelectric memory (FeRAM), magnetic store (MRAM), all non-volatile storeies such as variable resistance type storer (ReRAM), be used for substituting the tail end storage unit in DRAM, thereby can greatly improve the refresh time of DRAM primary memory, reduce DRAM and refresh produced power consumption.
Embodiment bis-
The present embodiment discloses a kind of implementation method of mixing dynamic RAM, and Fig. 9 is the process flow diagram that the present invention's mixing DRAM memory function is realized; As shown in Figure 9, its method comprises:
Step 1: logic detection module keeps the time of data to detect to each storage unit every an interval time, and the storage unit detecting according to it keeps the time of data that storage unit is divided into tail end storage unit and main memory unit.
Step 2: in the time mixing DRAM storer in normal operating conditions, logic detection module will detect the duty of DRAM primary memory: whether DRAM primary memory is in busy state, such as DRAM main memory access frequency is more than or equal to the refreshing frequency of mixing DRAM, the power consumption of now mixing DRAM is mainly to the access visit that mixes DRAM, mixes refreshing power consumption and can ignoring of DRAM.Now mix DRAM still with former refresh mode operation; If the DRAM primary memory in mixing DRAM is in idle condition, such as DRAM main memory access frequency is less than the refreshing frequency of mixing DRAM, the power consumption of so now mixing DRAM mainly comes from the power consumption that refreshes of DRAM primary memory, mixes DRAM and will enter low-power consumption refresh mode.
Step 3: entering before low-power consumption refresh mode, alternative these tail end storage unit of designating unit that logic detection module controls in nonvolatile memory read or store data, if when system needs lastest imformation to be stored to the tail end storage unit in DRAM primary memory next time under low-power consumption mode, described lastest imformation can directly be stored to the substituting unit in nonvolatile memory; Instantly, when subsystem needs to read the tail end storage unit in DRAM primary memory under low-power consumption mode, system can directly be accessed the appointment substituting unit in nonvolatile memory.
Step 4: logic detection module is set the first refresh time to DRAM primary memory, described the first refresh time is greater than the second refresh time, and this first refresh time is not more than the retention time of described main memory unit, thereby make to mix DRAM in low-power consumption refresh mode.
Step 5: logic detection module detects the duty of DRAM primary memory in real time, once DRAM enters busy state from idle condition, so the data in nonvolatile memory to be transmitted back in the storage unit in former DRAM primary memory, logic detection module DRAM primary memory refresh time is set to the second refresh time, mixes afterwards DRAM and again enters former refresh mode.
Embodiment tri-
Mixing DRAM memory construction in the present embodiment is applied to non-volatile dynamic storage (NVDIMM) (as Fig. 3) product, and object is the power consumption that refreshes in order to reduce inner DRAM primary memory.Than DRAM primary memory in former NVDIMM with former refreshing frequency periodic refresh, refresh time is the second refresh time, refresh power consumption large, after power down, be used for storing the data in DRAM primary memory after power down by nonvolatile memory, after powering on, the data transmission of nonvolatile memory is returned in DRAM primary memory.
Figure 10 is the embodiment of the present invention three structural representations; As shown in figure 10.For example: the capacity of DRAM primary memory is 1GB, be divided into 8 DRAM pieces, in each DRAM piece, contain several storage unit, the capacity of nonvolatile memory is 1GB, and the capacity that is used for substituting the tail end storage unit in DRAM primary memory may only need 32MB, all the other are still used for storing the data in DRAM primary memory after power down.First logic detection module detects 8 DRAM pieces, and sets the boundary of tail end storage unit and main memory unit maintenance data time, for example: data hold time is tail end storage unit lower than the storage unit of 3.2s, and is main memory unit higher than 3.2s.In the time that logic detection unit inspection is operated in idle condition to DRAM primary memory, logic detection unit is the designating unit to 32MB in nonvolatile memory by the data transmission of all tail end storage unit in 8 DRAM pieces.The storage unit retention time in the DRAM primary memory that now needs to refresh, 8 DRAM pieces that logic detection module can be set DRAM primary memory all refreshed with the first refresh time of 3.2s all more than 3.2s.Compare the every 64ms of original the second refresh time and will refresh once, refreshing frequency has reduced by 50 times fully, greatly reduces and refreshes power consumption; Figure 11 is refresh cycle contrast schematic diagram in embodiment tri-; As shown in Figure 11 and table 1.Because tail end storage unit proportion is very low, most of data are still arranged in the main memory unit of former DRAM primary memory.When DRAM primary memory is under low-power consumption refresh mode, if access frequency is far smaller than refreshing frequency (64ms), and to time very short (being approximately a few tens of milliseconds) of data writing in nonvolatile memory, therefore the performance of data writing is unaffected; Again because the relative DRAM primary memory of data of nonvolatile storage reading speed is slower, therefore from nonvolatile memory, the speed of reading out data can decrease, but because tail end storage unit proportion is very little, be only 32mb, therefore the performance of this mixing DRAM primary memory is influenced hardly.
? Refresh cycle Power consumption
Former refresh mode 64ms Refresh power consumption high
Low-power consumption refresh mode 3.2s Refresh power consumption very low
Table 1
Embodiment tetra-
The mixing DRAM memory application of the present embodiment is in DRAM(Fig. 5 of mixing memory cubic structure (HMC)), can reduce it and refresh power consumption, Figure 12 is the embodiment of the present invention four structural representations; As shown in figure 12, nonvolatile memory and logic detection module are arranged in DRAM logic core lamella, and the capacity of supposing DRAM primary memory is 1GB, and it comprises 8 DRAM layers, are respectively DRAM layer 0 to DRAM layer 7, and the capacity of nonvolatile memory can be 32MB.Because DRAM logic chip can directly be accessed each DRAM layer by silicon through hole (TSV), because tail end storage unit in each DRAM layer distributes all different with the storage unit retention time, logic detection module can detect respectively and set for each DRAM layer the boundary of different tail end storage unit and main memory unit maintenance data time, when DRAM primary memory is under low-power consumption mode, in different DRAM layers, the data of tail end storage unit are all written into the designating unit in nonvolatile memory, and different DRAM layers can refresh under the first different refresh times.For example, DRAM layer 0 first refresh time is 6.4s, DRAM layer 1 and DRAM layer 5 first refresh time are 3.2s, the first refresh time of DRAM layer 2 and DRAM layer 6 is 0.8s, the first refresh time of DRAM layer 4, DRAM layer 7 and DRAM layer 3 is 1.6s, compare original all DRAM layer the second refresh times and be 64ms, refresh power consumption and greatly reduce, Figure 13 is prior art refresh cycle schematic diagram in embodiment tetra-; Figure 14 is the refresh cycle schematic diagram of embodiment tetra-; As Figure 13,14 and table 2 shown in.When DRAM primary memory is under low-power consumption refresh mode, if access frequency is far smaller than refreshing frequency (64ms), and to time very short (being approximately a few tens of milliseconds) of data writing in nonvolatile memory, the performance of therefore mixing DRAM data writing will can not be affected; Because the relative DRAM of speed of nonvolatile memory reading out data is slower, therefore from nonvolatile memory, the speed of reading out data decreases, but because tail end storage unit proportion is very little, therefore the performance of this mixing DRAM is influenced hardly.
? Refresh cycle Power consumption
Former refresh mode 64ms Refresh power consumption high
Low-power consumption refresh mode 0.8s/1.6s/3.2s/6.4s Refresh power consumption very low
Table 2
Embodiment five
We know that the access speed of hard disk is many slowly than processor operating rate, if data need to be stored in hard disk and go now, because hard disk speed is quite slow, user need to wait for that long time just can complete storage operation, and user's experience sense will be very poor.From hard disk, sense data also needs to wait for for a long time equally.So in order to improve performance, generally all can add a fritter internal memory, the namely buffer memory of hard disk, the structural representation that Figure 15 is existing hard disk in hard disk; As shown in figure 15, buffer memory reading speed is far longer than hard disk, when needs write hard disk by data or from hard disk when sense data, can first data be stored in the buffer memory of hard disk and go, thereby direct read/write data can improve system speed greatly from buffer memory.And this buffer memory is generally taked DRAM structure.Processor is general only directly carries out data interaction with DRAM primary memory, and DRAM primary memory most of the time in hard disk is all in idle condition, but because electric capacity is revealed the electric charge periodic refresh of having to, for example every 64ms refreshes once, and power consumption is very large.
The present embodiment adopts and mixes DRAM storer for hard disk, and Figure 16 is the structural representation of the present embodiment hard disk; As shown in figure 16, first, keep the boundary of data time to divide main memory unit and tail end storage unit by tail end storage unit and main memory unit in logic detection module setting DRAM primary memory, for example, data hold time is tail end storage unit lower than 3.2s, and is main memory unit higher than 3.2s.Now logic detection unit is by the designating unit in the data write non-volatile memory of tail end storage unit, and substitute tail end storage unit by designating unit, the main memory unit retention time in the DRAM primary memory that now needs to refresh is all more than 3.2s, the first refresh time that logic detection module can be set DRAM primary memory is 3.2s, comparing the every 64ms of original the second refresh time will refresh once, refreshing frequency has reduced by 50 times fully, greatly reduces and refreshes power consumption.Because tail end storage unit proportion is very low, most of data are still arranged in DRAM primary memory.When DRAM primary memory is under low-power consumption refresh mode, if access frequency is far smaller than refreshing frequency (64ms), and to the time of data writing in nonvolatile memory very short (approximately a few tens of milliseconds), therefore mix DRAM data writing unaffected; Due to nonvolatile memory reading speed, relative DRAM is slower, and therefore from nonvolatile memory, the speed of reading out data decreases, but because tail end storage unit proportion is very little, therefore the performance of this mixing DRAM is influenced hardly.
In sum, a kind of method of power consumption when the invention discloses the DRAM of mixing storer and reducing this DRAM memory refress, in conjunction with nonvolatile memory and DRAM primary memory, utilize the storage unit in nonvolatile memory to substitute tail end storage unit in DRAM primary memory, thereby can greatly reduce refreshing frequency, greatly reduce DRAM primary memory and refreshed power consumption.
These are only preferred embodiment of the present invention; not thereby limit embodiments of the present invention and protection domain; to those skilled in the art; the scheme that being equal to of should recognizing that all utilizations instructions of the present invention and diagramatic content make replaces and apparent variation obtains, all should be included in protection scope of the present invention.

Claims (12)

1. mix a DRAM storer, it is characterized in that, comprise DRAM primary memory, nonvolatile memory and logic detection module;
Described DRAM primary memory is connected with the two-way communication of described logic detection module, and described DRAM primary memory is connected with described nonvolatile memory two-way communication, and described logic detection module is connected with described nonvolatile memory two-way communication;
Wherein, described logic detection module detects the duty of described DRAM primary memory, and the operating state data obtaining according to it arranges tail end storage unit and main memory unit in described DRAM primary memory, set the refresh cycle of described DRAM primary memory according to this operating state data, and described logic detection module is controlled the data transmission between described DRAM primary memory and described nonvolatile memory according to the refresh cycle of setting simultaneously.
2. mixing DRAM storer as claimed in claim 1, is characterized in that, is provided with several storage unit, and is preset with an interval time in described DRAM primary memory;
Described logic detection module keeps the time of data to detect to each described storage unit every interval time described in one, and the described storage unit detecting according to it keeps the time of data that described storage unit is divided into described tail end storage unit and described main memory unit.
3. mixing DRAM storer as claimed in claim 1, is characterized in that, the refresh cycle of described DRAM primary memory comprises the first refresh time and the second refresh time.
4. mixing DRAM storer as claimed in claim 3, is characterized in that, described the first refresh time is greater than the second refresh time, and this first refresh time is not more than the time that described main memory unit keeps data.
5. mixing DRAM storer as claimed in claim 1, it is characterized in that, described logic detection module detects in real time frequency of access and the refreshing frequency of described DRAM primary memory, and the frequency of access detecting according to it and refreshing frequency judge the duty of described DRAM primary memory.
6. mixing DRAM storer as claimed in claim 5, is characterized in that, the duty of described DRAM primary memory comprises busy state and idle condition;
When described frequency of access is more than or equal to described refreshing frequency, described DRAM primary memory is in busy state;
When described frequency of access is less than described refreshing frequency, described DRAM primary memory is in idle condition.
7. mixing DRAM storer as claimed in claim 6, it is characterized in that, in the time that the duty of described DRAM primary memory is idle condition, described in described logic detection module controls, nonvolatile memory substitutes described tail end storage unit and reads and store data manipulation, and the refresh cycle that described logic detection module is set described DRAM primary memory is the first refresh time;
In the time that the duty of DRAM primary memory is converted to busy state from idle condition, described in described logic detection module controls, data transmission is returned described DRAM primary memory by nonvolatile memory, and the refresh cycle that described logic detection module is set described DRAM primary memory is the second refresh time.
8. one kind is reduced the method for power consumption while mixing DRAM memory refress, it is characterized in that, be applied to and in the claims 1~7, described in any one, mix DRAM storer, this storer comprises DRAM primary memory, nonvolatile memory and logic detection module, described DRAM primary memory comprises tail end storage unit and main memory unit, and described method comprises:
Described logic detection module is determined tail end storage unit and the main memory unit in described DRAM primary memory;
In the time that the duty of described DRAM primary memory is idle condition, described in described logic detection module controls, nonvolatile memory substitutes described tail end storage unit and reads and store data manipulation, and the refresh cycle that described logic detection module is set described DRAM primary memory is the first refresh time;
In the time that the duty of DRAM primary memory is converted to busy state from idle condition, described in described logic detection module controls, data transmission is returned described DRAM primary memory by nonvolatile memory, and the refresh cycle that described logic detection module is set described DRAM primary memory is the second refresh time.
9. the method for power consumption when reduction mixing DRAM memory refress as claimed in claim 8, is characterized in that, is provided with several storage unit, and is preset with an interval time in storer;
Described logic detection module keeps the time of data to detect to each described storage unit every interval time described in one, and the described storage unit detecting according to it keeps the time of data that described storage unit is divided into described tail end storage unit and described main memory unit.
10. the method for power consumption when reduction mixing DRAM memory refress as claimed in claim 8, is characterized in that, the refresh cycle of described DRAM primary memory comprises the first refresh time and the second refresh time.
When 11. reduction mixing DRAM memory refress as claimed in claim 10, the method for power consumption, is characterized in that, described the first refresh time is greater than the second refresh time, and this first refresh time is not more than the time that described main memory unit keeps data.
When 12. reduction mixing DRAM memory refress as claimed in claim 8, the method for power consumption, is characterized in that, the duty of described DRAM primary memory comprises busy state and idle condition;
When described frequency of access is more than or equal to described refreshing frequency, described DRAM primary memory is in described busy state;
When described frequency of access is less than described refreshing frequency, described DRAM primary memory is in described idle condition.
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