CN103810126B - Mixing DRAM memory and the method for reducing power consumption when the DRAM memory refreshes - Google Patents
Mixing DRAM memory and the method for reducing power consumption when the DRAM memory refreshes Download PDFInfo
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Abstract
A kind of method for mixing DRAM memory and reducing power consumption when the DRAM memory refreshes disclosed by the invention, it is combined with DRAM main memory by by nonvolatile memory, and substitute the tail end memory cell in DRAM main memory using the memory cell specified in nonvolatile memory, so as to substantially increase the refresh cycle, refreshing frequency is reduced, the refresh power consumption of DRAM main memory is significantly reduced.
Description
Technical field
The present invention relates to semiconductor devices and technical field of integrated circuits, and in particular to one kind mixing DRAM memory and drop
The method of power consumption when the low DRAM memory refreshes.
Background technology
In the past few decades, dynamic RAM（DRAM）Cost constantly reduce with Moore's Law.But with feature
Size is less and less, requirement of the chip to power consumption also more and more higher, due to the electric leakage of DRAM storage capacitances, it is therefore necessary to every one section
Time just refreshes once, and increases the power consumption of refreshing, as shown in figure 1, the less DRAM refresh power consumptions of capacity can be relatively low, only account for compared with
Few a part of power consumption, but as DRAM capacity becomes big, refresh power consumption is significantly raised because feature size downsizing, DRAM its
His part change of power consumption is not obvious, but very big to capacitive effect, therefore refresh power consumption is significantly improved；Therefore how to reduce
The refresh power consumption of DRAM is problem demanding prompt solution.
In the last few years, some new DRAM structures or storage material were suggested to solve lacking for current DRAM technology
Fall into.IBM Corporation advocates to use nonvolatile memory phase transition storage（PCM）A kind of mixing memory is combined to form with DRAM.Though
Right PCM is nonvolatile memory, and power consumption is very low, but by the PCM write times are relevant with write data, therefore PCM
Access speed is not as good as DRAM, and PCM has the limitation of write-in number of times.In order to combine the respective advantage of the two, one kind solves to do
The primary structure of method, Fig. 2 is the structural representation that a kind of utilization nonvolatile memory and DRAM combine to form mixing memory；
As shown in Fig. 2 wherein（1）It is processor, mixing memory includes DRAM cache,（3）PCM main storages and（4）When PCM writes
Sequence module.As can be seen that DRAM is only used as Cache in figure, most recently used information is cached, only just will when needed
In data Cun Chudao PCM.Because DRAM is intended only as caching, capacity need not be very big, and PCM is as primary storage medium in storage number
According to when without periodic refreshing, therefore this structure can substantially reduce the power consumption of data storage, but because PCM is stored and is read
Speed is slower, therefore this structure is decreased obviously on overall performance.Fig. 3 utilizes nonvolatile memory and DRAM for another
Combine to form the structural representation of mixing memory；As shown in figure 3, wherein（1）It is processor, mixing memory includes DRAM master
Memory, nonvolatile memory and（6）Reserve battery.In normal use, DRAM is still primary storage medium, once fall
Electricity, standby big battery will rapidly by the data Cun Chudao nonvolatile memories in DRAM.When going up electricity again, data meeting
It is automatic to return to DRAM from nonvolatile memory.Although this structure solves DRAM volatility issues, but still
Without reducing the power consumption that produces when DRAM is periodically flushed data, and cost is also greatly improved.
Micron Technology（Micron）Propose a kind of mixing storage cubic structure（HMC, Hybrid Memory Cube）, it is based on
A kind of silicon hole（TSV, Through-Silicon Vias）The 3-D technology of connection.Fig. 4 be tradition DRAM between layers
Planar structure schematic diagram；As shown in figure 4, DRAM is between layers planar structure, connected by PAD between layers, accounted for
Use ample resources.If processor is wanted to access DRAM layers 9 of data, just have to pass through other DRAM layers, such as by DRAM layers 2,
Get to DRAM9 for DRAM layers 5, DRAM layers 8, waste plenty of time and power consumption.HMC structures as shown in figure 5, DRAM layers with layer it
Between spatially structure, and by silicon hole（TSV）Connection, without PAD, saves a large amount of areas, and substantially reduce visit
Ask the time, such as when accessing DRAM layers 4, need not move through other DRAM layers, be directly that may have access to by TSV, significantly reduce work(
Consumption, the performance of device is greatly enhanced.But this structure is very high to technological requirement, cost increases, and DRAM is still
Periodic refreshing is needed, refresh power consumption is still without reduction.
Chinese patent（Publication number：CN101216751B）Disclose it is a kind of based on distribution storage organization with data processing
The DRAM device of ability, including：Memory device interface, control interface, processing unit, DRAM memory banks, communication network, DRAM
Bank controller, dma controller, memory device interface are used for and external memory bus interaction data, while and device
Interior DRAM storage controls and dma controller are connected, and dma controller, processing unit and DRAM bank controllers are by logical
Communication network is connected, and internal DRAM bank controllers are also connected with internal DRAM memory simultaneously.The advantage of the invention is not right
Other hardware are modified in data handling system, can be used as normal memory, it is also possible to have using programme-control
The data processing unit of the storage device of data-handling capacity, to inside device data acceleration treatment, play significantly improve it is whole
The effect of individual data handling system performance.
Chinese patent（Publication number：CN1424658A）A kind of flash memory device and its method for designing are disclosed, is to use
Dynamic RAM is DRAM memory chips as storage medium and its method for designing, and internal memory core is made using power consumption measure is reduced
The lower power consumption of piece to acceptable scope, using external power supply for memory chip is powered, by external interface and host
Carry out data exchange.Described flash memory device at least includes：A () is used for connecting the interior of the DRAM memory chips of storage data
Deposit interface；B () is used for connecting the outer interface controller of the general channels communicated with host；C () is used for as in DRAM
Deposit the external direct current power supply of chip power supply；D () is used for the microprocessor that managing access to data and host are communicated；E () is used for
The software and hardware method of memory chip reduction power consumption；F () is adapted to the file storage structure that memory chip accesses data.With it is existing
Technology is compared, the flash memory device of the invention has that cost is lower, capacity bigger, speed faster, easily scalable, service life
Longer the characteristics of.
The content of the invention
A kind of method for mixing DRAM memory and reducing power consumption when the DRAM memory refreshes disclosed by the invention, passes through
Nonvolatile memory is combined with DRAM main memory, and is substituted using the memory cell specified in nonvolatile memory
Tail end memory cell in DRAM main memory, so as to substantially increase the refresh cycle, reduces refreshing frequency, significantly reduces
The refresh power consumption of DRAM main memory.
This invention describes one kind mixing DRAM memory, wherein, including DRAM main memory, nonvolatile memory and
Logic detection module；
The DRAM main memory and the logic detection module two-way communication link, the DRAM main memory and described
Nonvolatile memory two-way communication link, the logic detection module and the nonvolatile memory two-way communication link；
Wherein, the logic detection module detects the working condition of the DRAM main memory, and the work obtained according to it
Make status data and tail end memory cell and main memory unit are set in the DRAM main memory, while according to the working condition
The refresh cycle of DRAM main memory described in data setting, and the logic detection module controls institute according to the refresh cycle of setting
State the data transfer between DRAM main memory and the nonvolatile memory.
Above-mentioned mixing DRAM memory, wherein, several memory cell are provided with the DRAM main memory, and preset
There is an interval time；
The logic detection module is the time that data are kept to memory cell each described every interval time described in one
Detected, and the memory cell detected according to it is kept for the time of data the memory cell is divided into the tail
End memory cell and the main memory unit.
Above-mentioned mixing DRAM memory, wherein, refresh cycle of the DRAM main memory include the first refresh time and
Second refresh time.
Above-mentioned mixing DRAM memory, wherein, first refresh time is more than the second refresh time, and first refreshing
Time is not more than the time that the main memory unit keeps data.
Above-mentioned mixing DRAM memory, wherein, DRAM main memory deposits described in the logic detection module real-time detection
Frequency and refreshing frequency are taken, and the frequency of access that is detected according to it and refreshing frequency judge the work of the DRAM main memory
Make state.
Above-mentioned mixing DRAM memory, wherein, the working condition of the DRAM main memory includes busy state and free time
State；
When the frequency of access is more than or equal to the refreshing frequency, the DRAM main memory is in busy state；
When the frequency of access is less than the refreshing frequency, the DRAM main memory is in idle condition.
Above-mentioned mixing DRAM memory, wherein, it is described when the working condition of the DRAM main memory is idle condition
The logic detection module control nonvolatile memory replacement tail end memory cell is read out and is operated with data storage,
And it is the first refresh time that the logic detection module sets refresh cycle of the DRAM main memory；
When the working condition of DRAM main memory is converted to busy state from idle condition, the logic detection module control
Make the nonvolatile memory and data transfer is returned into the DRAM main memory, the logic detection module sets the DRAM
The refresh cycle of main storage is the second refresh time.
The present invention also describes a kind of method for reducing power consumption when mixing DRAM memory refreshes, wherein, it is applied to above-mentioned
Mix DRAM memory in claim 1~7 described in any one, the memory includes DRAM main memory, non-volatile deposits
Reservoir and logic detection module, the DRAM main memory include tail end memory cell and main memory unit, and specific method is as follows：
The logic detection module determines tail end memory cell and main memory unit in the DRAM main memory；
When the working condition of the DRAM main memory is idle condition, the logic detection module control is described non-easy
The property lost memory substitutes the tail end memory cell and is read out and data storage operation, and logic detection module setting institute
The refresh cycle for stating DRAM main memory is the first refresh time；
When the working condition of DRAM main memory is converted to busy state from idle condition, the logic detection module control
Make the nonvolatile memory and data transfer is returned into the DRAM main memory, the logic detection module sets the DRAM
The refresh cycle of main storage is the second refresh time.
The method of power consumption when above-mentioned reduction mixing DRAM memory refreshes, wherein, several storages are provided with memory
Unit, and it is preset with an interval time；
The logic detection module is the time that data are kept to memory cell each described every interval time described in one
Detected, and the memory cell detected according to it is kept for the time of data the memory cell is divided into the tail
End memory cell and the main memory unit.
The method of power consumption when above-mentioned reduction mixing DRAM memory refreshes, wherein, the refreshing week of the DRAM main memory
Phase includes the first refresh time and the second refresh time.
The method of power consumption when above-mentioned reduction mixing DRAM memory refreshes, wherein, first refresh time is more than second
Refresh time, and first refresh time is not more than the time that the main memory unit keeps data.
The method of power consumption when above-mentioned reduction mixing DRAM memory refreshes, wherein, the work shape of the DRAM main memory
State includes busy state and idle condition；
When the frequency of access is more than or equal to the refreshing frequency, the DRAM main memory is in the busy shape
State；
When the frequency of access is less than the refreshing frequency, the DRAM main memory is in the idle condition.
The present invention has following technical advantage：
1st, by combining nonvolatile memory and dynamic RAM, the refreshing week of dynamic RAM can be improved
Phase, so as to substantially reduce the power consumption produced by dynamic RAM.
2nd, tail end memory cell is substituted using nonvolatile memory, so as to greatly improve the refresh cycle, lowers and refresh frequency
Rate, greatly reduces the refresh power consumption of dynamic RAM, and the performance of dynamic RAM is barely affected.
Brief description of the drawings
The accompanying drawing for constituting a part of the invention is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its illustrate, for explaining the present invention, not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 for currently with following DRAM capacity and refresh power consumption, non-refresh power consumption ratio schematic diagram；
Fig. 2 is the structural representation that a kind of utilization nonvolatile memory and DRAM combine to form mixing memory；
Fig. 3 is another structural representation for combining to form mixing memory with DRAM using nonvolatile memory；
Fig. 4 is the planar structure schematic diagram in traditional DRAM between layers；
Fig. 5 is the mixing memory cube that Micron Technology proposes（HMC）Structural representation；
Fig. 6 is the schematic diagram of tail end memory cell and main memory unit retention time in DRAM；
Fig. 7 is present invention mixing DRAM memory structure schematic diagram；
The schematic diagram that Fig. 8 changes with main memory unit for tail end memory cell in DRAM memory with use time；
Fig. 9 is the flow chart of present invention mixing DRAM memory functional realiey；
Figure 10 is the structural representation of the embodiment of the present invention three；
Figure 11 is refresh cycle contrast schematic diagram in embodiment three；
Figure 12 is the structural representation of the embodiment of the present invention four；
Figure 13 is prior art refresh cycle schematic diagram in example IV；
Figure 14 is the refresh cycle schematic diagram of example IV；
Figure 15 is the structural representation of existing hard disk；
Figure 16 is the structural representation of the present embodiment hard disk.
Specific embodiment
With reference to specific examples below and accompanying drawing, the present invention is described in further detail.Implement process of the invention,
Condition, experimental technique etc., in addition to the following special content for referring to, are the universal knowledege and common knowledge of this area, this hair
It is bright that content is not particularly limited.
The distribution of retention time of the present invention based on DRAM data proposes a kind of mixing DRAM memory.During the holding of data
Between（retention time）Directly determine the refresh cycle of DRAM memory.Research shows, depositing in DRAM main memory
Storage unit is divided into two parts according to the time that data keep, and a part is main memory unit, and another part is tail end memory cell,
Fig. 6 is tail end memory cell and main memory unit retention time schematic diagram in DRAM；As shown in fig. 6, the holding of main memory unit
The time of data can reach the 1s even longer times, and the memory cell only less than 1% is tail end memory cell, they
Kept for the time of data be less than 1s, or even less than 100ms.But determine that DRAM memory refresh time is exactly to maintain data
The worst tail end memory cell of ability（tail bit）.Current DRAM main memory refresh time can reach 64ms, now just
Progressively strided forward to the target of 128ms, but due to technological problemses, allow the retention time of all of memory cell all to reach the target ten
Divide difficulty, this also causes many DRAM memory factory costs to greatly improve, directly results in many DRAM memory factories numerous and confused
Close down.As DRAM memory capacity does bigger and bigger, DRAM memory refresh power consumption also remains high always.
Embodiment one
Although tail end memory cell keeps, and the ability of data is excessively poor, the memory cell retention time more than 99% is but
Can reach more than 1s.Analyzed based on more than, the present invention proposes a kind of structure for mixing DRAM memory, Fig. 7 mixes for the present invention
DRAM memory structure schematic diagram；As shown in fig. 7, the mixing DRAM memory includes a DRAM main memory, it is non-volatile
Memory and logic detection module, the DRAM main memory and the logic detection module two-way communication link, can detect
The frequency of access and refreshing frequency of the working of DRAM main memory, such as DRAM main memory, if frequency of access is big
In equal to refreshing frequency, show DRAM main memory be in busy state, then DRAM main memory run with former refresh mode, brush
The new cycle is the second refresh time, and now logic detection module is periodically detected to the working condition of DRAM main memory, if
Refreshing frequency is more than frequency of access, and surface DRAM is in idle condition, then DRAM main memory will be transported with low-power consumption refresh mode
OK, the refresh cycle is the first refresh time；Before low-power consumption refresh mode is entered, logic detection module mainly completes following behaviour
Make：First, several memory cell are provided with DRAM main memory, an interval time, logic is set to logic detection module
Detection module is to be kept for the time of data detect each memory cell every an interval time, and detected according to it
Memory cell is kept for the time of data memory cell is divided into tail end memory cell and main memory unit.
Next, it is determined that tail end memory cell and main memory unit in DRAM main memory, furthermore, DRAM primary storages
The data of device and nonvolatile memory two-way communication link, tail end memory cell and nonvolatile memory can be transmitted mutually,
By in the data write-in nonvolatile memory of tail end memory cell storage in DRAM main memory, the control of logic detection module is non-
Volatile memory substitutes tail end memory cell and reads and data storage；Then, logic detection module can be according to main memory unit
Retention time and afterbody memory cell retention time boundary, to DRAM main memory set the first refresh time, first
Refresh time is more than the second refresh time, less than the retention time of main memory unit, if carrying worst depositing in DRAM main memory
The information of storage unit, the boundary of its retention time for including the distribution of tail end memory cell and tail end memory cell and main memory unit
Limit, then logic detection module can be directly non-volatile by the data write-in of tail end memory cell storage in DRAM main memory
In memory, the logic detection module controls the nonvolatile memory to substitute the tail end memory cell reading and store
Data, and the first refresh time is set to DRAM main memory.
Because DRAM main memory use time is elongated, the hydraulic performance decline of device, electric capacity keep data capability also gradually under
Drop, the distributed area of tail end memory cell and main memory unit can be overall to left in Fig. 6, and Fig. 8 is tail end in DRAM memory
The schematic diagram that memory cell changes with main memory unit with use time；As shown in figure 8, tail end memory cell increases, DRAM master
The retention time of memory device also reduces.Therefore the interval time that logic detection module can be according to set by updates main memory unit
Retention time and afterbody memory cell retention time boundary；For example under system during electricity, DRAM primary storages are reset
Tail end memory cell and main memory unit in device, so that logic detection module resets the storage list in nonvolatile memory
Unit substitutes newly-increased tail end memory cell, then ensures the first refresh time, also or resets the first refresh time.
For the nonvolatile memory of low capacity, logic detection module can only be realized with state machine；For
The larger nonvolatile memory of capacity, the microcontroller that logic detection module can be carried using Large Copacity nonvolatile memory
Device（MCU）To realize, so that cost-effective；Above-mentioned nonvolatile memory can select flash memory, phase transition storage PCM, ferroelectricity
Memory（FeRAM）, magnetic memory（MRAM）, variable resistance type memory（ReRAM）Deng all non-volatile memories, use
To substitute the tail end memory cell in DRAM, such that it is able to greatly improve the refresh time of DRAM main memory, DRAM brushes are reduced
Power consumption produced by new.
Embodiment two
Present embodiment discloses a kind of implementation method for mixing dynamic RAM, Fig. 9 is deposited for present invention mixing DRAM
The flow chart of reservoir functional realiey；As shown in figure 9, its method includes：
Step one：Logic detection module is to be kept for the time of data examine each memory cell every an interval time
Survey, and the memory cell detected according to it is kept for the time of data memory cell is divided into tail end memory cell and primary storage
Unit.
Step 2：When DRAM memory is mixed in normal operating conditions, logic detection module will detect that DRAM is hosted
The working condition of reservoir：I.e. DRAM main memory whether be in busy state, such as DRAM main memory frequency of access more than etc.
In the refreshing frequency of mixing DRAM, now mix the power consumption of DRAM essentially from the access visit to mixing DRAM, mix DRAM
Refresh power consumption it is negligible.Now mixing DRAM is still run with former refresh mode；If at the DRAM main memory in mixing DRAM
In idle condition, such as refreshing frequency of the DRAM main memory frequency of access less than mixing DRAM, then now mix DRAM's
Power consumption mostlys come from the refresh power consumption of DRAM main memory, and mixing DRAM will be into low-power consumption refresh mode.
Step 3：Before low-power consumption refresh mode is entered, logic detection module controls the finger in nonvolatile memory
Order unit substitutes these tail end memory cell and reads or data storage, if system needs to believe renewal next time under low-power consumption mode
When breath stores the tail end memory cell into DRAM main memory, the fresh information can be stored directly to nonvolatile memory
In substituting unit；Instantly when subsystem needs to read the tail end memory cell in DRAM main memory under low-power consumption mode,
System can directly access the specified substituting unit in nonvolatile memory.
Step 4：Logic detection module sets the first refresh time to DRAM main memory, and first refresh time is big
In the second refresh time, and first refresh time is not more than the retention time of the main memory unit, so that mixing DRAM
In low-power consumption refresh mode.
Step 5：The working condition of logic detection module real-time detection DRAM main memory, once DRAM is from idle condition
Into busy state, then the data in nonvolatile memory will be transmitted back into the memory cell in former DRAM main memory
In, DRAM main memory refresh time is set to the second refresh time by logic detection module, DRAM is mixed afterwards and is again introduced into
Former refresh mode.
Embodiment three
Mixing DRAM memory structure in the present embodiment is applied to non-volatile dynamic memory（NVDIMM）（Such as Fig. 3）
Product, in order to the refresh power consumption of the DRAM main memory inside reducing.Compared to DRAM main memory in former NVDIMM
With former refreshing frequency periodic refresh, refresh time is the second refresh time, and refresh power consumption is big, is deposited by non-volatile after a power failure
Reservoir is used for storing the data after power down in DRAM main memory, and the data transfer of nonvolatile memory returns DRAM master after upper electricity
In memory.
Figure 10 is the structural representation of the embodiment of the present invention three；As shown in Figure 10.For example：The capacity of DRAM main memory is
1GB, is divided into 8 DRAM blocks, and several memory cell are contained in each DRAM block, and the capacity of nonvolatile memory is 1GB, and
Capacity for substituting the tail end memory cell in DRAM main memory may only need 32MB, after remaining is still used for storing power down
Data in DRAM main memory.Logic detection module detects 8 DRAM blocks first, and sets tail end memory cell and primary storage
Unit keeps the boundary of data time, for example：Memory cell of the data hold time less than 3.2s is tail end memory cell, and
Main memory unit is higher than 3.2s.When logic detection unit detects DRAM main memory is operated in idle condition, logic
Detection unit is by the specified list of the data transfer of all tail end memory cell in 8 DRAM blocks to 32MB in nonvolatile memory
Unit.Now need the memory cell retention time in the DRAM main memory for refreshing in more than 3.2s, logic detection module can
All refreshed with first refresh time of 3.2s with 8 DRAM blocks for setting DRAM main memory.Refresh compared to original second
Time will refresh once per 64ms, and refreshing frequency reduces 50 times fully, greatly reduces refresh power consumption；Figure 11 is embodiment
Refresh cycle contrast schematic diagram in three；As shown in Figure 11 and Biao 1.It is most of because tail end memory cell proportion is very low
Data are still located in the main memory unit in former DRAM main memory.When DRAM main memory is under low-power consumption refresh mode,
If access frequency is far smaller than refreshing frequency（64ms）, and it is very short to the time that data are write in nonvolatile memory（Greatly
About a few tens of milliseconds）, therefore the performance of write-in data is unaffected；Again because data of nonvolatile storage reading speed is relative
DRAM main memory is slower, therefore the speed of reading data can decrease from nonvolatile memory, but due to tail end
Memory cell proportion is very small, only 32mb, therefore the performance of this mixing DRAM main memory is barely affected.
| Refresh cycle | Power consumption | |
| Former refresh mode | 64ms | Refresh power consumption is high |
| Low-power consumption refresh mode | 3.2s | Refresh power consumption is very low |
Table 1
Example IV
The mixing DRAM memory of the present embodiment is applied to mixing memory cubic structure（HMC）DRAM（Fig. 5）, can be with
Its refresh power consumption is reduced, Figure 12 is the structural representation of the embodiment of the present invention four；As shown in figure 12, nonvolatile memory and logic
Detection module is located in DRAM logic core lamellas, it is assumed that the capacity of DRAM main memory is 1GB, and it includes 8 DRAM layers, respectively
It it is DRAM layers 0 to DRAM layers 7, the capacity of nonvolatile memory can be 32MB.Because DRAM logic chips can be by silicon hole
（TSV）Each DRAM layers is directly accessed, because the distribution of tail end memory cell and memory cell retention time are equal in each DRAM layers
Difference, logic detection module can respectively detect and set different tail end memory cell and main memory units for each DRAM layers
The boundary of data time is kept, when DRAM main memory is under low-power consumption mode, tail end memory cell in different DRAM layers
Data be written into designating unit in nonvolatile memory, and different DRAM layers can be in the first different refresh times
Under refreshed.For example, DRAM layers of 0 first refresh time is 6.4s, DRAM layer 1 and DRAM layers of 5 first refresh time are 3.2s,
DRAM layers 2 and DRAM layers 6 of the first refresh time is 0.8s, and DRAM layers 4, DRAM layers 7 and DRAM layers 3 of the first refresh time is
1.6s, 64ms is compared to original all DRAM layers of the second refresh times, and refresh power consumption is substantially reduced, and Figure 13 is in example IV
Prior art refresh cycle schematic diagram；Figure 14 is the refresh cycle schematic diagram of example IV；Such as Figure 13,14 and table 2 shown in.When
DRAM main memory is under low-power consumption refresh mode, if access frequency is far smaller than refreshing frequency（64ms）, and to non-volatile
Property memory in write data time it is very short（About a few tens of milliseconds）, therefore the performance of mixing DRAM write-in data will not
Can be affected；Because the speed that nonvolatile memory reads data is slower with respect to DRAM, therefore from nonvolatile memory
The middle speed for reading data decreases, but because tail end memory cell proportion is very small, therefore this mixing DRAM
Performance be barely affected.
| Refresh cycle | Power consumption | |
| Former refresh mode | 64ms | Refresh power consumption is high |
| Low-power consumption refresh mode | 0.8s/1.6s/3.2s/6.4s | Refresh power consumption is very low |
Table 2
Embodiment five
It is understood that the access speed of hard disk is slow many compared to processor operating rate, if need data now
Store in hard disk because hard disk speed is relatively slow, user need wait long time could complete storage operation, use
Family experience sense will be very poor.The same data that read from hard disk are also required to wait for a long time.So in order to improve performance, typically
Will in a hard disk add a fritter internal memory, that is, hard disk caching, Figure 15 is the structural representation of existing hard disk；Such as Figure 15
Shown, caching reading speed is far longer than hard disk, when needing to write data into hard disk or read data from hard disk, can be first
Store data into the caching of hard disk, direct read/write data are such that it is able to greatly improve system speed from caching.And this
Plant caching and typically take DRAM structures.Processor is general only directly to carry out data interaction with DRAM main memory, and is in hard disk
In the DRAM main memory most of the time all in idle condition, but because electric capacity leakage electric charge is had to periodic refresh,
For example refresh once per 64ms, power consumption is very big.
For hard disk using mixing DRAM memory, Figure 16 is the structural representation of the present embodiment hard disk to the present embodiment；Such as
Shown in Figure 16, first, kept by tail end memory cell in logic detection module setting DRAM main memory and main memory unit
The boundary of data time divides main memory unit and tail end memory cell, for example, data hold time is tail end less than 3.2s
Memory cell, and be higher than that 3.2s is main memory unit.Now logic detection unit is non-by the data write-in of tail end memory cell
In designating unit in volatile memory, and tail end memory cell is substituted by designating unit, now need the DRAM for refreshing
The main memory unit retention time in main storage, logic detection module can set DRAM main memory in more than 3.2s
First refresh time is 3.2s, will be refreshed once per 64ms compared to original second refresh time, and refreshing frequency is reduced fully
50 times, greatly reduce refresh power consumption.Because tail end memory cell proportion is very low, most of data are still located at DRAM master
In memory.When DRAM main memory is under low-power consumption refresh mode, if access frequency is far smaller than refreshing frequency（64ms）,
And it is very short to the time that data are write in nonvolatile memory（About a few tens of milliseconds）, therefore mixing DRAM write-ins data are not
It is impacted；Because nonvolatile memory reading speed is slower with respect to DRAM, therefore data are read from nonvolatile memory
Speed decrease, but because tail end memory cell proportion is very small, therefore this mixing DRAM performance almost
It is unaffected.
In sum, mix DRAM memory and reduce power consumption when the DRAM memory refreshes the invention discloses a kind of
Method, with reference to nonvolatile memory and DRAM main memory, DRAM is substituted using the memory cell in nonvolatile memory
Tail end memory cell in main storage, such that it is able to substantially reduce refreshing frequency, significantly reduces DRAM main memory refreshing
Power consumption.
Preferred embodiments of the present invention are these are only, embodiments of the present invention and protection domain is not thereby limited, it is right
For those skilled in the art, should can appreciate that all utilization description of the invention and diagramatic content made equivalent replaces
Change and obviously change resulting scheme, should be included in protection scope of the present invention.
Claims (12)
1. it is a kind of to mix DRAM memory, it is characterised in that including DRAM main memory, nonvolatile memory and logic detection
Module；
The DRAM main memory and the logic detection module two-way communication link, the DRAM main memory and it is described it is non-easily
The property lost memory two-way communication link, the logic detection module and the nonvolatile memory two-way communication link；
Wherein, the logic detection module detects the working condition of the DRAM main memory, according to the working condition that it is obtained
Data set tail end memory cell and main memory unit in the DRAM main memory, and by the nonvolatile memory with
The DRAM main memory is combined, and operating state data according to the acquired DRAM main memory decides whether
The nonvolatile memory replacement tail end memory cell is controlled to be read out and store using the logic detection module
Data manipulation, while the refresh cycle of the DRAM main memory is set according to the operating state data, and the logic detection
Module controls the data transfer between the DRAM main memory and the nonvolatile memory according to the refresh cycle of setting.
2. it is as claimed in claim 1 to mix DRAM memory, it is characterised in that to be provided with the DRAM main memory some
Individual memory cell, and it is preset with an interval time；
The logic detection module is to keep the time of data to carry out to memory cell each described every interval time described in one
Detect, and the memory cell is divided into by the tail end according to the time of its memory cell holding data for detecting and deposit
Storage unit and the main memory unit.
3. it is as claimed in claim 1 to mix DRAM memory, it is characterised in that the refresh cycle bag of the DRAM main memory
Include the first refresh time and the second refresh time.
4. it is as claimed in claim 3 to mix DRAM memory, it is characterised in that first refresh time refreshes more than second
Time, and first refresh time is not more than the time that main memory unit keeps data.
5. it is as claimed in claim 1 to mix DRAM memory, it is characterised in that described in the logic detection module real-time detection
The frequency of access and refreshing frequency of DRAM main memory, and the frequency of access that is detected according to it and refreshing frequency are come described in judging
The working condition of DRAM main memory.
6. it is as claimed in claim 5 to mix DRAM memory, it is characterised in that the working condition bag of the DRAM main memory
Include busy state and idle condition；
When the frequency of access is more than or equal to the refreshing frequency, the DRAM main memory is in busy state；
When the frequency of access is less than the refreshing frequency, the DRAM main memory is in idle condition.
7. it is as claimed in claim 6 to mix DRAM memory, it is characterised in that when the working condition of the DRAM main memory
During for idle condition, the logic detection module controls the nonvolatile memory replacement tail end memory cell to be read
Take when set refresh cycle of the DRAM main memory as the first refreshing with data storage operation, and the logic detection module
Between；
When the working condition of DRAM main memory is converted to busy state from idle condition, the logic detection module controls institute
State nonvolatile memory and data transfer is returned into the DRAM main memory, the logic detection module sets the DRAM and hosts
The refresh cycle of reservoir is the second refresh time.
8. it is a kind of reduce mixing DRAM memory refresh when power consumption method, it is characterised in that be applied to the claims 1~
Mix DRAM memory in 7 described in any one, the memory includes the inspection of DRAM main memory, nonvolatile memory and logic
Module is surveyed, the DRAM main memory includes tail end memory cell and main memory unit, and methods described includes：
The operating state data of the DRAM main memory according to acquired in the logic detection module determines the DRAM master
Tail end memory cell and main memory unit in memory, and the nonvolatile memory is entered with the DRAM main memory
Row is combined, and is decided whether to control the non-volatile memories using the logic detection module according to the operating state data
The device replacement tail end memory cell is read out and is operated with data storage, while according to operating state data setting
The refresh cycle of DRAM main memory；
When the working condition of the DRAM main memory is idle condition, the logic detection module control is described non-volatile
The memory replacement tail end memory cell is read out and is operated with data storage, and logic detection module setting is described
The refresh cycle of DRAM main memory is the first refresh time；
When the working condition of DRAM main memory is converted to busy state from idle condition, the logic detection module controls institute
State nonvolatile memory and data transfer is returned into the DRAM main memory, the logic detection module sets the DRAM and hosts
The refresh cycle of reservoir is the second refresh time.
9. it is as claimed in claim 8 to reduce the method for mixing power consumption when DRAM memory refreshes, it is characterised in that in memory
Several memory cell are provided with, and are preset with an interval time；
The logic detection module is to keep the time of data to carry out to memory cell each described every interval time described in one
Detect, and the memory cell is divided into by the tail end according to the time of its memory cell holding data for detecting and deposit
Storage unit and the main memory unit.
10. it is as claimed in claim 8 to reduce the method for mixing power consumption when DRAM memory refreshes, it is characterised in that described
The refresh cycle of DRAM main memory includes the first refresh time and the second refresh time.
The 11. as claimed in claim 10 methods for reducing power consumption when mixing DRAM memories refresh, it is characterised in that described the
One refresh time is more than the second refresh time, and first refresh time is not more than the time that main memory unit keeps data.
12. methods for reducing power consumption when mixing DRAM memory refreshes as claimed in claim 8, it is characterised in that described
The working condition of DRAM main memory includes busy state and idle condition；
When the frequency of access is more than or equal to the refreshing frequency, the DRAM main memory is in the busy state；When
The frequency of access is less than the refreshing frequency, and the DRAM main memory is in the idle condition.
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| CN104636452B (en) * | 2015-01-28 | 2018-02-27 | 江苏大学 | A kind of unified file system management method towards SCM |
| CN104932991B (en) * | 2015-06-15 | 2018-08-28 | 上海新储集成电路有限公司 | A method of substituting mixing memory using afterbody hybrid cache |
| CN106406493B (en) | 2015-07-30 | 2020-04-28 | 华为技术有限公司 | Electronic device capable of reducing power consumption and method for reducing power consumption of electronic device |
| JP2018049385A (en) * | 2016-09-20 | 2018-03-29 | 東芝メモリ株式会社 | Memory system and processor system |
| US10714179B2 (en) | 2016-10-07 | 2020-07-14 | Hewlett-Packard Development Company, L.P. | Hybrid memory devices |
| CN107015628B (en) * | 2017-03-30 | 2020-08-28 | 中国科学院计算技术研究所 | Low-overhead DRAM refreshing method and system for approximate application |
| CN109741777A (en) * | 2018-12-28 | 2019-05-10 | 上海新储集成电路有限公司 | A kind of memory for improving speed and keeping data time |
| CN111124966B (en) * | 2019-11-12 | 2021-08-24 | 上海移远通信科技有限公司 | Method and device for improving stability of module data |
| CN111625265B (en) * | 2020-05-26 | 2023-07-04 | 深圳忆联信息系统有限公司 | Method and device for reducing DRAM space consumption in firmware upgrade |
| CN114255799B (en) * | 2020-09-22 | 2023-10-17 | 长鑫存储技术有限公司 | Memory data refreshing method, controller thereof and memory |
| EP4002368A4 (en) | 2020-09-22 | 2022-05-25 | Changxin Memory Technologies, Inc. | Memory data refresh method and controller therefor, and memory |
| CN114333972B (en) * | 2020-09-30 | 2023-09-01 | 长鑫存储技术有限公司 | Self-refresh cycle test method and device |
| US11929130B2 (en) | 2020-09-30 | 2024-03-12 | Changxin Memory Technologies, Inc. | Method and device for testing sr cycle as well as method and device for testing ar number |
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