CN107015628A - It is a kind of towards the low overhead DRAM method for refreshing and system approximately applied - Google Patents
It is a kind of towards the low overhead DRAM method for refreshing and system approximately applied Download PDFInfo
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Abstract
The present invention proposes a kind of towards the low overhead DRAM method for refreshing and system approximately applied, it is related to reservoir designs technical field, this method includes static matching mapping step, the offline global memory access information for obtaining application, the maximum reuse distance of each memory line in the global memory access information is analyzed, in the memory line that the content migration in each memory line to holding time is more than to the maximum reuse distance；Dynamic threshold set-up procedure, at regular intervals, periodically predicts the maximum reuse distance in each mapping cycle according to history mapping result, and matches corresponding memory line in being distributed in the DRAM retention times.The present invention is after the mapping and migration that progress routine data is stored in internal memory, the error rate of static matching mapping method is almost nil, the error rate of Dynamic Matching mapping method can be controlled within 0.7%, and original refreshing energy consumption can be saved more than 99% by two methods.
Description
Technical field
It is more particularly to a kind of to refresh towards the low overhead DRAM approximately applied the present invention relates to reservoir designs technical field
Method and system.
Background technology
A big chunk power consumption of current processor system is all produced by DRAM main memory, and the trend is also drilled more
It is stronger.There are some researches show in Modern server system, the power consumption that main storage system is produced occupies up to 30~40% ratio in the recent period
Example, and Memory Controller Hub power consumption, background power consumption and dynamic power consumption can be divided into by hosting power consumption, the generation and memory access of background power consumption are lived
Dynamic unrelated, it is mainly derived from main memory peripheral circuit, transistor leakage and refresh power consumption, and wherein refresh power consumption is deposited by DRAM
Caused by storage unit capacity fall off, dram controller must by periodic refresh operation compensating electric capacity leak electricity electric charge so that
Protect the correctness of positive data storage.Bhati et al. research shows that the main memory power consumption more than 20% is the refresh operation by DRAM
Produce, therefore, the refresh power consumption for reducing DRAM main memories is extremely important for system energy efficiency optimization.
Although JEDEC defines 64ms refresh interval standard, practical study shows, 99% DRAM cell is kept
Time can reach nearly 10s, as shown in figure 1, therefore, the flush mechanism of convential memory system also has very big design space.
Approximate calculation is taken seriously more and more as a kind of thinking for reducing energy consumption, particularly current mobile and embedded
The rise of formula equipment, many calculating tasks such as media handling (video, audio and image etc.), identification and data mining etc. are not
It is required that result of calculation is completely correct, possess a certain degree of mistake tolerance, however, traditional memory system is shown
It is significant wastage to energy consumption that " long tail effect " come, which has spent in 99% effort on the error rate of elimination 1%,.
In DRAM, refresh operation can be replaced to the read-write operation of memory cell, if to same address location
Double access time interval is less than the retention time of the unit, it is meant that the unit can without refresh operation, from
And refresh power consumption is saved, classical approximation, which is calculated, applies such as multimedia, game, audio frequency and video, only sub-fraction and programme-control
The correctness that the related data of stream are performed to program plays key effect, and this partial data is referred to as critical data, this part
The retention time failure occurred in data is very big on output correctness influence, and other mass data collection, during to comprising keeping
Between failure including failure and insensitive, this partial data is commonly known as non-critical data, therefore is deposited to reduce as far as possible
The refresh operation of reservoir, it is possible to use the memory access mode of non-critical data is weighed to its storage in DRAM in approximate calculation
Mapping, therefore, with reference to the distribution of retention time deviation in DRAM memory, is remapped by rational data, can be in not shadow
On the premise of response Consumer's Experience, data refresh operation is reduced, refresh power consumption is reduced.
It is prior art below, it is as follows：
Smart Refresh：Due to the continuous loss of the capacitance charge of internal storage location data storage, internal storage location is every one
The section time will be refreshed to prevent charge loss from excessively causing error in data, and JEDEC has formulated DRAM and refreshed every 64ms
Standard once, current memory chip have followed this standard, and counter is provided with DRAM Memory Controller Hub, works as counting
Device is decremented to show when zero that Memory Controller Hub will reset counter and send refresh command, such as Fig. 2 institutes by the 64ms times
It is fixed send to show that row refreshes (Row Refresh) order.
Substantially it is then that reading to DRAM cell and writing back again is deposited with recovery to ensure the correct refresh operation of data
The charge level that storing up electricity is held, and the reading and write operation to internal memory can inherently brush the data of correspondence memory line unit
Newly, the refresh operation therefore after accessing operation is avoidable, and it is Smart that Fig. 2 rows, which are accessed shown in (Row Access),
Refresh best-cases, before each row Rk refresh command is sent, the row have received access request Ak, therefore all
Refresh operation after memory access can be cancelled saving energy consumption.
Smart Refresh basic ideas are that the association of 2 bits or 3 bit sizes is set for the often row in Bank
Counter, the value of counter is all stored and updated in Memory Controller Hub, will in the value of a refresh interval inside counting device
Zero is decremented to from maximum, and when memory line is read and write, the value of corresponding counter will be reset to maximum and restart to pass
Subtract, the memory line that Memory Controller Hub only can be zero to counter refreshes, if the value of counter is decremented to zero, now means
The memory line must be to be refreshed, therefore accessing operation is postponed refresh operation, best-case by triggering counter to reset
As shown in Fig. 2 refresh command generation is not had in internal memory.
Smart Refresh working mechanisms have been inquired into shown in Fig. 3, e.g., in Fig. 3 shown in (a) figure, 2-bit sizes have been used
Counter, and refresh interval is 64ms, it is assumed that in whole process, access request, internal memory are initiated to DRAM without any program
Controller will automatically update the value of counter, be successively decreased every 16ms, when counter is decremented to zero, and correspondence memory row is needed
To be refreshed, now the Counter Value of all memory lines is all zero, and Memory Controller Hub needs to refresh all rows, due to brush
Newer command can not be performed parallel, therefore now the performance of memory system will be influenceed by serious, be counted in Fig. 3 in (b) figure
It is staggered during the value initialization of device from 0 to 3, a large amount of memory lines can be avoided to need the feelings being refreshed simultaneously to a certain extent
Condition, but such scheme still has some problems, first, counter random initializtion is meaned to have 1/4 every time
Memory line needs to be refreshed, and the Counter Value for even just having started just to have during initialization 1/4 is 0, secondly, in the process of running,
Because register can be reset to maximum by the read-write requests of memory access, therefore it can be possible to face the feelings in Fig. 3 shown in (a) figure
Shape.
In order to solve problem above, Smart Refresh are taken counter initial value and decrement operations while staggering
Thinking, in (b) figure memory line being divided into N groups in such as Fig. 3, (N size depends on N=in the size of memory refresh queue, figure
4, every group of counter comprising 16 memory lines), original scheme is in 0ms, 16ms, 32ms and 48ms refresh counter, currently
Scheme is then further to disperse each renewal before, and such as the original counter at the 0ms moment updates correspondence：
The counter of the 1st memory line in all 4 packets is updated in 0ms,
The counter of the 2nd memory line in all 4 packets is updated in 1ms,
……
The counter of the 16th memory line in all 4 packets is updated in 15ms.
The essence of such scheme is that the time interval granularity of refresh counter diminishes, and is disperseed so that operation will be updated, together
When need the number of lines refreshed also accordingly to reduce, can all there is N number of memory line to need refreshing per 1ms as shown in Figure 3, and N is basis
What the size of the refresh command request queue of DRAM Memory Controller Hub was set, therefore avoid a large amount of refresh operations obstructions and normally please
Seek the hydraulic performance decline caused.
Flikker：Tolerance of the Flikker technologies based on application itself to mistake, will have in application data to mistake
The non-critical data of tolerance, which is separated and carries out low frequency, to be refreshed to reduce power consumption, and Flikker passes through software and hardware
Refresh with reference to the low frequency for completing non-critical data.
Each DRAM Bank are divided into ensureing the correct normal refresh region of critical data by hardware aspect, Flikker
With for save power consumption be directed to non-critical data low frequency refresh region, as shown in Figure 4.
Software aspects are broadly divided into following steps, and programmer first needs to enter rower to critical data when writing application
Note；Secondly, in program operation process system need critical data and non-critical data being respectively stored into it is normal in internal memory
Refresh region and low frequency refresh region；Then operating system configures autonomous refresh counter and DRAM is switched into autonomous refresh mode
(in Mobile operating system, refresh control power is given DRAM itself by processor to save operating system when power consumption enters dormancy
Mechanism)；Finally, autonomous refresh controller carries out different frequency respectively according to operating system configuration parameter to DRAM different zones
Refreshing.Software aspects need to modify to cooperate, specifically to application program's source code, runtime system and operating system
As shown in Figure 5.
For approximate calculation apply dynamic memory DRAM refresh control optimization methods, achievement in research both domestic and external compared with
Few, existing achievement in research is primarily present problems with：First, the premise of refresh operation how is reduced in reduction refreshing frequency
Under, it is ensured that the correct operation of computer application simultaneously ensures its service quality；Second, the DRAM for how designing dynamic memory is different
The refreshing frequency of address block, minimizes refresh overhead；3rd, it is impossible to by data address and memory address space one by one
Matching, with reference to memory address distribution, minimizes refreshing frequency.3 points of the above, which directly results in existing achievement, three big defects：The
One, refreshing frequency is too high, it is impossible to make full use of the fault-tolerant ability approximately applied；Second, refresh scheme is unreliable, causes to apply out
Existing mistake or influence output quality；3rd, higher area and power dissipation overhead.
The technical problem present in prior art, as follows below：
SmartRefresh：1) Smart refresh are that each eDRAM (embedded DRAM) rows introduce a meter
When device, by being stabbed for each eDRAM row once refreshing recorded thereon/access time, it is to avoid the unnecessary refreshing to eDRAM rows,
But this method, mainly in eDRAM on piece, for the DRAM memory of Large Copacity, then the counter expense introduced is excessive；
2) SmartRefresh can averagely save 52.6% refresh power consumption, and the present invention can save more than 99% refreshing work(
Consumption.
Flikker：Flikker needs programmer to mark non-critical data, and combines the collaboration work such as compiler operations system
Make, technology is excessively complicated, larger using difficulty.Flikker reduces refresh rate to non-critical data, is configured to refresh in DRAM
Rate region, saving refresh power consumption is limited, and this technology can almost save most refresh power consumptions.
The content of the invention
In view of the shortcomings of the prior art, the present invention propose a kind of towards the low overhead DRAM method for refreshing approximately applied and be
System.
Present invention proposition is a kind of towards the low overhead DRAM method for refreshing approximately applied, including：
Static matching mapping step, the offline global memory access information for obtaining application analyzes every in the global memory access information
The maximum reuse distance of individual memory line, is more than the maximum reuse distance by the content migration in each memory line to holding time
Memory line in；
Dynamic threshold set-up procedure, at regular intervals, periodically according to history mapping result prediction each mapping week
The maximum reuse distance of phase, and corresponding memory line is matched in being distributed in the DRAM retention times.
The static matching mapping step includes
(1) the global memory access information includes：Memory access address, memory access type, timestamp, and formed in set D, set D
Each element be two tuple (Pi,Tij),Wherein PiRepresent the page i of internal memory address, TijRepresent jth time
The timestamp conducted interviews to page i, according to set D, it is a two tuple (P to obtain each element in set V, set Vi,
Vij),Wherein PiRepresent the page i of internal memory address, VijRepresent that jth time is visited page i for -1 time with jth
The difference for the timestamp asked, the difference is reuse distance.
(2) for DRAM retention time distributed intelligence, represented by set R, wherein each element is two tuples
(Rk,rtk),RkRepresent memory line k address, rtkThen represent memory line k retention time.
(3) in order to each P in set ViCorresponding memory line R is found in set Rk, for some page of PiThere is set
(Pi,Vij),A page P is found out firstiAll maximums for accessing reuse distance, are designated as (Pi, maxV), then keeping
Annual distribution set (Rk,rtk),Find rt in all memory lines of the retention time more than maxVkMinimum memory line
Rk, by page PiWith RkMatched, repeating (3), corresponding memory line maps until all pages in set V are all searched out.
The dynamic threshold set-up procedure includes：
1. in each mapping end cycle, the threshold value of the page is predicted, wherein obtaining the maximum that the page currently maps the cycle
Reuse distance, assesses the threshold error rate of last time mapping period forecasting；
2. according to the threshold value, in the memory line that all retention times are more than the threshold value, find out unallocated and protect
Hold the memory line of time minimum；
3. the page memory line minimum with the retention time is matched.
4. it is as claimed in claim 1 towards the low overhead DRAM method for refreshing approximately applied, it is characterised in that also to include
Error Control is carried out to the dynamic threshold set-up procedure.
The Error Control is specifically included：The horizontal E of Error Control is set first, and in each controlling cycle, statistics is all
The error rate of page, it is assumed that current for k-th of controlling cycle Tk, then page i error rate is eik.In TkAt the end of, traversal assesses institute
The statistical information for having page decides whether migration, wherein for page i, the relative error rate that it is calculated first in current time fragment is
reik=eik- E, then obtains control weight values, as follows
cwik=P*reik+I*(reik+rei(k-1))+D*(reik-rei(k-1))
According to control weight values cwikSize determine page i whether be migrated.
The present invention also propose it is a kind of towards the low overhead DRAM updating systems approximately applied, including：
Static matching mapping block, the global memory access information for obtaining application offline, analyzes the global memory access information
In each memory line maximum reuse distance, the content migration in each memory line to holding time is more than described maximum reuse
In the memory line of distance；
Dynamic threshold adjusting module, at regular intervals, periodically each being reflected according to the prediction of history mapping result
Penetrate the maximum reuse distance in cycle, and match corresponding memory line in being distributed in the DRAM retention times.
The static matching mapping block includes
(1) the global memory access information includes：Memory access address, memory access type, timestamp, and formed in set D, set D
Each element be two tuple (Pi,Tij),Wherein PiRepresent the page i of internal memory address, TijRepresent jth time
The timestamp conducted interviews to page i, according to set D, it is a two tuple (P to obtain each element in set V, set Vi,
Vij),Wherein PiRepresent the page i of internal memory address, VijRepresent that jth time is visited page i for -1 time with jth
The difference for the timestamp asked, the difference is reuse distance.
(2) for DRAM retention time distributed intelligence, represented by set R, wherein each element is two tuples
(Rk,rtk),RkRepresent memory line k address, rtkThen represent memory line k retention time.
(3) in order to each P in set ViCorresponding memory line R is found in set Rk, for some page of PiThere is set
(Pi,Vij),A page P is found out firstiAll maximums for accessing reuse distance, are designated as (Pi, maxV), then keeping
Annual distribution set (Rk,rtk),Find rt in all memory lines of the retention time more than maxVkMinimum memory line
Rk, by page PiWith RkMatched, repeating (3), corresponding memory line maps until all pages in set V are all searched out.
The dynamic threshold adjusting module includes：
1. in each mapping end cycle, the threshold value of the page is predicted, wherein obtaining the maximum that the page currently maps the cycle
Reuse distance, assesses the threshold error rate of last time mapping period forecasting；
2. according to the threshold value, in the memory line that all retention times are more than the threshold value, find out unallocated and protect
Hold the memory line of time minimum；
3. the page memory line minimum with the retention time is matched.
Also include carrying out Error Control to the dynamic threshold set-up procedure.
The Error Control is specifically included：The horizontal E of Error Control is set first, and in each controlling cycle, statistics is all
The error rate of page, it is assumed that current for k-th of controlling cycle Tk, then page i error rate is eik.In TkAt the end of, traversal assesses institute
The statistical information for having page decides whether migration, wherein for page i, the relative error rate that it is calculated first in current time fragment is
reik=eik- E, then obtains control weight values, as follows
cwik=P*reik+I*(reik+rei(k-1))+D*(reik-rei(k-1))
According to control weight values cwikSize determine page i whether be migrated.
From above scheme, the advantage of the invention is that：
The present invention is after the mapping and migration that progress routine data is stored in internal memory, the mistake of static matching mapping method
Rate is almost nil by mistake, and the error rate of Dynamic Matching mapping method can be controlled within 0.7%, and two methods can will be original
Refresh energy consumption and save more than 99%.
Brief description of the drawings
Fig. 1 is DRAM retention time distribution maps；
Fig. 2 is Smart Refresh schematic diagrames；
Fig. 3 is Smart Refresh counter works mechanism choices；
Fig. 4 is Flikker DRAM Bank structure charts；
Fig. 5 is Flikker system framework figures；
Fig. 6 is to consider that mistake tolerates the DRAM refresh control method general thought figures of characteristic；
Fig. 7 is the DRAM refresh control method overall construction drawings based on static state/Dynamic Matching mapping；
Fig. 8 is PID error controller structure charts.
Embodiment
Inventor has found that DRAM read-write requests are inherently when carrying out the DRAM refresh control researchs based on mistake tolerance
Interviewed memory cell can be refreshed, be observed based on more than, inventor attempts to replace refresh operation using read-write requests, proposes quiet
State, Dynamic Matching mapping method access application at the interval (reuse distance) of internal memory and DRAM retention time distribution progress
Match somebody with somebody, be finally reached the purpose for decreasing or even eliminating refreshing, now DRAM turns into " non-volatile " equipment, i.e. NV-DRAM.Due to dynamic
State matching mapping can not ensure that all memory lines after matching all can be by memory access before occurring retention time failure, therefore can go out
Now certain error rate, traditional application can ultimately result in program crashing or result mistake because of no tolerance, in recent years,
It is completely correct using being not required for for output quality with approximate calculation and the appearance of big data, and it is poor to only need to control
Mistake within the specific limits, therefore replaces the thinking of refresh operation to provide possibility for read-write requests, meanwhile, in order to ensure matching
The error rate of mapping method is inventors herein proposed based on the theoretical PID error controllers of Industry Control in controlled range.
For an application being currently running, its history memory access information can be collected, by simply handling
To the reuse distance information (time interval of the double same memory line of access) of the application, while DRAM can be obtained offline
The retention time distributed intelligence do not gone together, by static, Dynamic Matching mapping method, by reuse distance and retention time be distributed into
Row matching, will access the content migration stored at intervals of t memory line and be protected to memory line of the retention time more than t
Deposit, it is normal to read because DRAM read-write operation may be considered to by the refreshing of read-write row unit, therefore after the matching
Write operation instead of original flush mechanism, and the correctness of data, original flush mechanism are ensure that while read-write requests are completed
Energy consumption also will accordingly disappear, the input of whole system as shown in Figure 6 correspondence reuse distance and retention time distribution, by quiet
State, Dynamic Matching mapping method, finally provide matching mapping result and instruct to apply the storage in internal memory.
It is that the DRAM refresh control structure charts mapped with Dynamic Matching are mapped based on static matching respectively shown in Fig. 7, is based on
The critical piece of the DRAM refresh control structures of static matching mapping is SMP (StaticMapping) unit, and its effect is to pass through
Application memory access information memory trace and the DRAM retention times obtained offline are distributed retention time and run in program
Before provide the mapping scheme that data are stored in DRAM in its running, e.g., in Fig. 7 shown in (a) figure, base in (b) figure in Fig. 7
The DRAM refresh controls structure mapped in Dynamic Matching mainly has three parts, is DTP (Dynamic respectively
ThresholdMapping), PID-EC and migration page/modification page table.DTP is dynamic threshold method of adjustment, and it is knot that it, which is acted on,
Close the memory access information memory access trace and conventional matching mapping effect (i.e. error rate system in Fig. 7 collected in application running
Meter unit) matching mapping result is dynamically adjusted, when DTP provides matching mapping result, Migration units then will be right
The content migration answered is into the row being matched, further by changing page table, so as to ensure that operating system can be by original
Virtual page address find migration after internal memory physical address.PID-EC (PID Error Controllor) is PID mistake controls
Device processed, has used for reference the widely used control theory of industrial quarters, PID-EC purpose be find out in matching mapping process error rate compared with
High page, then by migrating page unit by the higher page migration of error rate to the region of normal refresh, so as to reduce error rate simultaneously
And ensure application output quality.
It is embodiments of the invention below, it is as follows：
1. the DRAM refresh control methods mapped based on static matching
Fixed for the corresponding relation without virtual memory and linear address space and physical address space such as embedded
System in, because the application of operation is relatively fixed, the memory access mode of application also has very big certainty, therefore matching mapping
Thinking it is relatively easy.The global memory access trace for obtaining application offline first, analyzes the maximum reuse distance of each memory line,
Each memory line is matched in DRAM row of the retention time more than maximum reuse distance.
Static matching mapping method is divided into two stages of Profiling and Mapping.The Profiling stages we first
Need off-line operation intended application and collect its memory access trace, further processing obtains reuse distance information, its secondary acquisition
The DRAM retention times are distributed；The reuse distance information of application and DRAM retention times are distributed by the Mapping stages to be matched.
A.Profiling early stage program analysis phases
(1) reuse distance information is applied.Assuming that the trace forms (i.e. global memory access information) accessed every time are：Memory access
Location, memory access type (read/write), timestamp.The application memory access trace so collected offline is set D, each element in set
For a two tuple (Pi,Tij),Wherein PiRepresent the page i of memory access address, TijRepresent that jth time is visited page i
The timestamp asked.According to set D, we, which can calculate, obtains set V, and each element in set V is a two tuple (Pi,
Vij),Wherein PiRepresent the page i of memory access address, VijRepresent that jth time is visited page i for -1 time with jth
The difference for the timestamp asked, that is, the reuse distance accessed.
(2) the DRAM retention times are distributed.For DRAM retention time distributed intelligence, we are represented by set R, wherein
Each element be two tuple (Rk,rtk),RkRepresent memory line k address, rtkThen represent memory line k's
Retention time.
B.Mapping storage object mapping phases
The thinking of static matching mapping method is, for each page P in set ViSuitable memory line is found in set R
Rk, matched, the storage of final tutorial program corresponding data in the process of running, to reach the purpose of " no to refresh ".
In order to each page P in set ViSuitable memory line R is found in set Rk, for some page of PiThere is set
(Pi,Vij),This page of all maximum for accessing reuse distance is found out first, is designated as (Pi, maxV), then keeping
Annual distribution set (Rk,rtk),Find rt in all memory lines of the retention time more than maxVkMinimum memory line
Rk, by PiWith the RkMatched.Repeating above method, suitable memory line maps until all pages in set V are all searched out.
In order to avoid some page of PiMaximum reuse distance maxV be far longer than other reuse distances and cause matching effect to become
Difference, therefore its reasonability can be judged first after maxV is found out, if unreasonable will abandon and re-search for most
Big reuse distance.It is due to that approximate calculation application possesses certain mistake tolerance although this can cause partial error, because
This does not have the influence of essence to application output quality.
2. the DRAM refresh control methods mapped based on Dynamic Matching
(1) dynamic thresholds are adjusted
In static matching mapping method, the maximum reuse distance of the page is found out first, the page is then matched into DRAM
The middle retention time is more than the memory line of the maximum reuse distance of the page, it becomes possible to ensure the read-write operation of the page in retention time event
Barrier refreshes internal storage location before occurring, and original refresh operation can be completely eliminated.Accordingly, each reflected what Dynamic Matching mapped
Penetrate the cycle and how to predict maximum reuse distance in the subsequent mapping cycle, and match in suitable in being distributed in the DRAM retention times
Depositing row just turns into key issue, and the maximum reuse distance of this prediction is referred to as threshold value.
Following steps are broadly divided into based on the matching mapping that dynamic threshold is adjusted：
(illustrated with the matching mapping flow of the single page, it is necessary to each page having access in actual moving process
Face traversal repeats following mapping process)
1. in each mapping end cycle, predict the threshold value of page-out.Specifically include acquisition the page currently map week
The maximum reuse distance of phase, the threshold error rate for assessing last time mapping period forecasting (matches the number of times failed and accounts for total access times
Ratio), with reference to information above analyze prediction the page threshold value.
2. using the threshold value obtained in previous step, in the memory line that all retention times are more than threshold value, find out unallocated
And the memory line that the retention time is minimum.
3. the memory line that the page and the above are found is matched.Specific practice is：It is first that the virtual page is corresponding
In physical address after the Data Migration of physical address to matching, then change page table and original virtual page address is mapped to
New physical address is to ensure normal program operation.
Assuming that the trace forms accessed every time are：Memory access address, memory access type (read/write), timestamp.We are every one
Section time Tslot(referred to as mapping the cycle) counts the program memory access information in the current mapping cycle, assesses the matching effect of mapping,
Then the reuse distance Threshold Trend of each page is predicted to be matched.It is assumed that in moment t (t=n*Tslot, n=1,2 ...),
The application memory access trace collected is set T, and each element in set is a two tuple (Pi,Tij),Wherein PiRepresent the virtual page i of memory access address, TijRepresent that jth time is entered to page i
The timestamp that row is accessed.It is a two tuple (P to be calculated according to set T and obtain each element in set V, set Vi,Vij),Wherein PiRepresent the page i of memory access address, VijRepresent what jth time and jth conducted interviews for -1 time to page i
The difference of timestamp, that is, the reuse distance accessed.For DRAM retention time distributed intelligence, we are represented by set R, its
In each element be two tuple (Rk,rtk),RkRepresent memory line k address, rtkThen represent memory line k
Retention time.
The thinking of Dynamic Matching mapping is, according to current slot TslotStatistical information, be each page of PiIn set R
Match corresponding memory line Rk, and during matching, Ct value effect is mapped according to current mapping cycle and upper one
Variation tendency is predicted, and finally provides internal memory mapping guidance information.
Dynamic prediction method employs a simple hill-climbing algorithm to carry out the adjustment of threshold value.Specifically, work as every time
Preceding mapping cycle TslotAt the end of, we can count effects of the last time mapping Ct value lastThresh in current period,
Calculate error rate (ErrorRate=# (Vij>lastThresh)/#Tij, wherein # (Vij>LastThresh) represent to access distance
Beyond the number of times of threshold value, #TijRepresent total access times of the page), if error rate is more than the error rate in mapping cycle last time
PreviousErrorRate, it was demonstrated that lastThresh effects are poor, using the threshold value of current slot.If error rate is less than
PreviousErrorRate then needs to be chosen according to changes of threshold trend, and idiographic flow is as shown in Algorithm 1.
(2) .PID error controllers
In actual running, most mistakes can be all concentrated on certain partial page.Therefore consider this
A little higher page migrations of error rate are gone out, and carry out normal refresh to ensure that data are correct.If directly counting all pages of mistake
Rate, in each mapping end cycle, error rate highest page migration is gone out, the control to error rate is simultaneously inaccurate, so
The result caused is probably that error rate is much smaller than the error rate upper control limit that provides, but simultaneously because exceedingly migrate page,
Migration overhead is caused to exceed the power consumption for avoiding refreshing and saving and finally lose more than gain.
It is PID error controller structures as shown in Figure 8, in PID each controlling cycle, error rate statistic part will
The current all pages error rate of statistics, each page is calculated according to above error rate information and given error rate controller leveler
Relative error rate and give PID error controllers and handled, which PID error controllers determine according to the controlled quentity controlled variable calculated
A little pages need to be migrated, and then send migration order to DRAM.
The horizontal E of Error Control is provided first, it is meant that PID controls the error rate of system near E.In each control
In cycle, the error rate of all pages of statistics.It is assumed that being currently k-th of controlling cycle Tk, then page i error rate is eik.In TkKnot
Shu Shi, the statistical information that traversal assesses all pages decides whether migration.For example, for page i, it is calculated first in current time piece
The relative error rate of section is reik=eik- E, then obtains the weighted value of PID controller, as follows
cwik=P*reik+I*(reik+rei(k-1))+D*(reik-rei(k-1))
According to control weight values cwikSize determine page i whether be migrated.
The present invention also propose it is a kind of towards the low overhead DRAM updating systems approximately applied, including：
Static matching mapping block, the global memory access information for obtaining application offline, analyzes the global memory access information
In each memory line maximum reuse distance, the content migration in each memory line to holding time is more than described maximum reuse
In the memory line of distance；
Dynamic threshold adjusting module, at regular intervals, periodically each being reflected according to the prediction of history mapping result
Penetrate the maximum reuse distance in cycle, and match corresponding memory line in being distributed in the DRAM retention times.
The static matching mapping block includes
(1) the global memory access information includes：Memory access address, memory access type, timestamp, and formed in set D, set D
Each element be two tuple (Pi,Tij),Wherein PiRepresent the page i of internal memory address, TijRepresent jth time
The timestamp conducted interviews to page i, according to set D, it is a two tuple (P to obtain each element in set V, set Vi,
Vij),Wherein PiRepresent the page i of internal memory address, VijRepresent that jth time is visited page i for -1 time with jth
The difference for the timestamp asked, the difference is reuse distance.
(2) for DRAM retention time distributed intelligence, represented by set R, wherein each element is two tuples
(Rk,rtk),RkRepresent memory line k address, rtkThen represent memory line k retention time.
(3) in order to each P in set ViCorresponding memory line R is found in set Rk, for some page of PiThere is set
(Pi,Vij),A page P is found out firstiAll maximums for accessing reuse distance, are designated as (Pi, maxV), then keeping
Annual distribution set (Rk,rtk),Find rt in all memory lines of the retention time more than maxVkMinimum memory line
Rk, by page PiWith RkMatched, repeating (3), corresponding memory line maps until all pages in set V are all searched out.
The dynamic threshold adjusting module includes：
1. in each mapping end cycle, the threshold value of the page is predicted, wherein obtaining the maximum that the page currently maps the cycle
Reuse distance, assesses the threshold error rate of last time mapping period forecasting；
2. according to the threshold value, in the memory line that all retention times are more than the threshold value, find out unallocated and protect
Hold the memory line of time minimum；
3. the page memory line minimum with the retention time is matched.
Also include carrying out Error Control to the dynamic threshold set-up procedure.
The Error Control is specifically included：The horizontal E of Error Control is set first, and in each controlling cycle, statistics is all
The error rate of page, it is assumed that current for k-th of controlling cycle Tk, then page i error rate is eik.In TkAt the end of, traversal assesses institute
The statistical information for having page decides whether migration, wherein for page i, the relative error rate that it is calculated first in current time fragment is
reik=eik- E, then obtains control weight values, as follows
cwik=P*reik+I*(reik+rei(k-1))+D*(reik-rei(k-1))
Wherein, P and I are respectively the scale parameter and integral parameter in pid control algorithm, change the empirical value of parameter and can lead to
Actual conditions are crossed, manually adjusts and looks for the minimum value of error rate and set, K is time parameter, it is specific to represent what is be currently located
Controlling cycle number.
According to control weight values cwikSize determine page i whether be migrated.
Claims (10)
1. it is a kind of towards the low overhead DRAM method for refreshing approximately applied, it is characterised in that including：
Static matching mapping step, the offline global memory access information for obtaining application is analyzed in each in the global memory access information
Capable maximum reuse distance is deposited, the content migration in each memory line to holding time is more than in the maximum reuse distance
Deposit in row；
Dynamic threshold set-up procedure, at regular intervals, periodically predicts each mapping cycle according to history mapping result
Maximum reuse distance, and corresponding memory line is matched in being distributed in the DRAM retention times.
2. it is as claimed in claim 1 towards the low overhead DRAM method for refreshing approximately applied, it is characterised in that described static
Include with mapping step
(1) the global memory access information includes：Memory access address, memory access type, timestamp, and form every in set D, set D
Individual element is two tuplesWherein PiRepresent the page i of internal memory address, TijRepresent jth time to page
The timestamp that i conducts interviews, according to set D, it is two tuples to obtain each element in set V, set VWherein PiRepresent the page i of internal memory address, VijRepresent that jth time is entered for -1 time with jth to page i
The difference for the timestamp that row is accessed, the difference is reuse distance.
(2) for DRAM retention time distributed intelligence, represented by set R, wherein each element is two tuplesRkRepresent memory line k address, rtkThen represent memory line k retention time.
(3) in order to each P in set ViCorresponding memory line R is found in set Rk, for some page of PiThere is setA page P is found out firstiAll maximums for accessing reuse distance, are designated as (Pi, maxV), then keeping
Annual distribution setFind rt in all memory lines of the retention time more than maxVkMinimum internal memory
Row Rk, by page PiWith RkMatched, repeating (3), corresponding memory line maps until all pages in set V are all searched out.
3. it is as claimed in claim 1 towards the low overhead DRAM method for refreshing approximately applied, it is characterised in that the dynamic threshold
Value set-up procedure includes：
1. in each mapping end cycle, the threshold value of the page is predicted, wherein obtaining the maximum reuse that the page currently maps the cycle
Distance, assesses the threshold error rate of last time mapping period forecasting；
2. according to the threshold value, in the memory line that all retention times are more than the threshold value, find out unallocated and when keeping
Between minimum memory line；
3. the page memory line minimum with the retention time is matched.
4. it is as claimed in claim 1 towards the low overhead DRAM method for refreshing approximately applied, it is characterised in that also including to institute
State dynamic threshold set-up procedure and carry out Error Control.
5. it is as claimed in claim 4 towards the low overhead DRAM method for refreshing approximately applied, it is characterised in that the mistake control
System is specifically included：The horizontal E of Error Control is set first, in each controlling cycle, the error rate of all pages of statistics, it is assumed that current
For k-th of controlling cycle Tk, then page i error rate is eik.In TkAt the end of, the statistical information decision that traversal assesses all pages is
No migration, wherein for page i, it is re that it is calculated first in the relative error rate of current time fragmentik=eik- E, is then obtained
Control weight values are as follows
cwik=P*reik+I*(reik+rei(k-1))+D*(reik-rei(k-1))
According to control weight values cwikSize determine page i whether be migrated.
6. it is a kind of towards the low overhead DRAM updating systems approximately applied, it is characterised in that including：
Static matching mapping block, the global memory access information for obtaining application offline analyzes every in the global memory access information
The maximum reuse distance of individual memory line, is more than the maximum reuse distance by the content migration in each memory line to holding time
Memory line in；
Dynamic threshold adjusting module, at regular intervals, periodically according to history mapping result prediction each mapping week
The maximum reuse distance of phase, and corresponding memory line is matched in being distributed in the DRAM retention times.
7. it is as claimed in claim 6 towards the low overhead DRAM updating systems approximately applied, it is characterised in that described static
Include with mapping block
(1) the global memory access information includes：Memory access address, memory access type, timestamp, and form every in set D, set D
Individual element is two tuplesWherein PiRepresent the page i of internal memory address, TijRepresent jth time to page
The timestamp that i conducts interviews, according to set D, it is two tuples to obtain each element in set V, set VWherein PiRepresent the page i of internal memory address, VijRepresent that jth time is entered for -1 time with jth to page i
The difference for the timestamp that row is accessed, the difference is reuse distance.
(2) for DRAM retention time distributed intelligence, represented by set R, wherein each element is two tuplesRkRepresent memory line k address, rtkThen represent memory line k retention time.
(3) in order to each P in set ViCorresponding memory line R is found in set Rk, for some page of PiThere is setA page P is found out firstiAll maximums for accessing reuse distance, are designated as (Pi, maxV), then keeping
Annual distribution setFind rt in all memory lines of the retention time more than maxVkMinimum internal memory
Row Rk, by page PiWith RkMatched, repeating (3), corresponding memory line maps until all pages in set V are all searched out.
8. it is as claimed in claim 6 towards the low overhead DRAM updating systems approximately applied, it is characterised in that the dynamic threshold
Value adjusting module includes：
1. in each mapping end cycle, the threshold value of the page is predicted, wherein obtaining the maximum reuse that the page currently maps the cycle
Distance, assesses the threshold error rate of last time mapping period forecasting；
2. according to the threshold value, in the memory line that all retention times are more than the threshold value, find out unallocated and when keeping
Between minimum memory line；
3. the page memory line minimum with the retention time is matched.
9. it is as claimed in claim 6 towards the low overhead DRAM updating systems approximately applied, it is characterised in that also including to institute
State dynamic threshold set-up procedure and carry out Error Control.
10. it is as claimed in claim 9 towards the low overhead DRAM updating systems approximately applied, it is characterised in that the mistake
Control is specifically included：The horizontal E of Error Control is set first, in each controlling cycle, the error rate of all pages of statistics, it is assumed that when
Before be k-th of controlling cycle Tk, then page i error rate is eik.In TkAt the end of, the statistical information that traversal assesses all pages is determined
Whether migrate, wherein for page i, it is re that it is calculated first in the relative error rate of current time fragmentik=eik- E, is then obtained
Control weight values are taken, it is as follows
cwik=P*reik+I*(reik+rei(k-1))+D*(reik-rei(k-1))
According to control weight values cwikSize determine page i whether be migrated.
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