CN106128499A - A kind of device refreshed for DRAM or eDRAM and method for refreshing - Google Patents
A kind of device refreshed for DRAM or eDRAM and method for refreshing Download PDFInfo
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- CN106128499A CN106128499A CN201610488683.9A CN201610488683A CN106128499A CN 106128499 A CN106128499 A CN 106128499A CN 201610488683 A CN201610488683 A CN 201610488683A CN 106128499 A CN106128499 A CN 106128499A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
Abstract
The present invention relates to a kind of device refreshed for DRAM or eDRAM and method for refreshing, refresh operation is performed in the data hold time each data base of DRAM or eDRAM, including: refresh control device, it is used for controlling the refresh cycle less than data hold time, and control generate whether perform refresh signal: Memory control device, it receives read-write requests, and the signal generated according to described refresh control device, sends read-write requests or refresh command to internal memory；Wherein, Memory control device is after sending refresh requests to internal memory, during refreshing execution, if receiving read-write requests, Memory control device is asked for instructions to refresh control device and could be interrupted refreshing and performing read-write operation, and refresh control device generates in predefined conditions and suspends the signal refreshed.The problem can not being written and read when can solve refresh by the present invention, and then enhance the impact of performance of DRAM or eDRAM.
Description
Technical field
The present invention relates to a kind of refreshing circuit, particularly relates to a kind of device refreshed for DRAM or eDRAM and method for refreshing.
Background technology
DRAM (Dynamic Random Access Memory), i.e. dynamic random access memory, is most commonly seen
Installed System Memory.Data can only be kept the shortest time by DRAM.In order to keep data, DRAM uses electric capacity storage, thus necessary
Refreshing (refresh) once every a period of time, if memory element is not refreshed, the information of storage will be lost.Due to
DRAM is manufactured by MOS technology, uses electric capacity to do memory element.DRAM's is low in energy consumption, and speed is slow.On the other hand, static random
Memorizer (SRAM) speed is fast and need not refresh, but the area of SRAM (SRAM) is the most greatly and more high
Expensive, therefore DRAM application is more extensive than SRAM.
SRAM (SRAM) is to store information with trigger, and DRAM electric capacity stores information.But
Electric capacity can gradually leak electricity, thus loses data.Therefore the memory element of DRAM needs periodically to refresh, and the refresh cycle is less than
Data hold time, if memory element is not refreshed in data hold time, storage information will be lost.Traditional
In concentrated refresh mode, within each refresh cycle can the section of the having time for carrying out refreshing (such as Fig. 1), in each refresh cycle
In, time shaft is divided into two parts, and portion of time is used for reading and writing, and another part time is used for refreshing.When DRAM is being carried out
During refreshing, it is impossible to be written and read operation, this period of time is referred to as Dead Time, the most just reduces DRAM read-write amount,
And the time delay making read-write increases.
Therefore, how to reduce DRAM read-write delay and become those skilled in the art's a great problem to be solved, how to carry
Refreshing can be made in the way of improving concentration refreshing to become more flexible for a kind of, coordinate to refresh and read/write conflict, and then raising
The handling capacity of DRAM for DRAM or eDRAM refresh device be those skilled in the art and relevant manufactures urgency be intended to solve
Problem place.
Summary of the invention
For above-mentioned technical problem, it is an object of the invention to solve at least the above and defect, and provide at least
The advantage that will be described later.
The present invention has designed and developed a kind of device refreshed for DRAM or eDRAM and method for refreshing, and the present invention's is main
Purpose is that providing a kind of can make refreshing become more flexible in the way of improving concentration refreshing, coordinates to refresh and read/write conflict,
And then improve the device refreshed for DRAM or eDRAM of the handling capacity of DRAM.
In order to realize according to object of the present invention and further advantage, it is provided that a kind of for DRAM or eDRAM refreshing
Device and method for refreshing, in the data hold time of each data base of DRAM or eDRAM perform refresh operation, bag
Including: refresh control device, it is used for controlling the refresh cycle less than data hold time, and controls to generate the letter whether performing to refresh
Number；Memory control device, it receives read-write requests, and the signal generated according to described refresh control device, sends to internal memory and read
Write request or refresh command；Wherein, Memory control device is after sending refresh requests to internal memory, during refreshing execution,
If receiving read-write requests, Memory control device is asked for instructions to refresh control device and could be interrupted refreshing and performing read-write operation,
Refresh control device generates in predefined conditions and suspends the signal refreshed.
Preferably, wherein, described predetermined condition is that refreshing can interrupt a time delay, and this time delay is that data are protected
Hold the difference between time and refresh cycle.
Preferably, wherein, described refresh control device, when the refresh cycle starts, generates and performs refresh signal, and lead to
Knowing that Memory control device controls internal memory and performs refresh operation, when a predetermined condition is satisfied, refresh control device generates to suspend and refreshes
Signal, and notify Memory control device control internal memory suspend refresh, perform read-write operation, when read-write operation cumulative time surpass
When spending time delay, described refresh control device generates execution refresh signal again, and notifies that Memory control device controls internal memory
Perform refresh operation, no longer response memory and control the read-write requests of device, until having refreshed.
Preferably, wherein, after having refreshed, Memory control device controls internal memory and performs read-write operation, until next
Refresh cycle, again perform refresh operation.
Preferably, wherein, described refresh control device includes: refresh cycle depositor, and it is used for storing the refresh cycle；
Refresh delay enumerator, it is used for storing the time that current refreshing has been delayed by；Refresh cycle intervalometer, it is used for recording works as
The time that the front refresh cycle passes through；Refreshing line number enumerator, it is used for current refreshing in database of record and has been refreshed
The line number of data；Total line number depositor, its total line number being used for storing the data in data base；And refresh delay deposits
Device, it is used for storing the time that can be delayed by that refreshing is total, i.e. this time delay.
Preferably, wherein, described refresh control device also includes: flush logic device, and it is deposited according to described total line number
Device calculates and has refreshed the required time；When having refreshed required residue always according to the calculating of described refreshing line number enumerator
Between；The beginning of refresh cycle is determined always according to refresh cycle depositor；Determine always according to refresh cycle intervalometer and to have refreshed
Time；Always according to the difference between refresh delay depositor and refresh delay enumerator, determine and suspend the time refreshed.
Preferably, wherein, described Memory control device includes: read caching, and it is used for caching the number stayed alone from internal memory
According to；Writing caching, it is used for caching the data that will be written to internal memory；Controlling logic, it is used for receiving read-write requests, and according to institute
State the signal that refresh control device generates, send read-write requests or refresh command to internal memory；And memory control signal generator,
It is used for the order becoming internal memory to identify the command decoder controlling logic transmission.
Preferably, wherein, each data base configures a set of refreshing apparatus；Or one group of data base with same number of rows
Configure a set of refreshing apparatus.
Preferably, wherein, the separate operation of refreshing apparatus of data base is often organized.
A kind of for DRAM or eDRAM method for refreshing, when the data of each data base at DRAM or eDRAM keep
Interior execution refresh operation, including:
Refresh cycle is set less than data hold time, and when the refresh cycle starts, refresh control device generates and performs
The signal refreshed；
Memory control device, according to the signal performing to refresh generated, sends refresh command to internal memory；
If in refresh process, Memory control device receives read-write requests, then to refresh control device ask for instructions could in
Break and refresh and perform read-write operation；
Refresh control device generates and suspends the signal refreshed, when the accumulative applicable time of this time-out refresh signal is a delay
Between, this time delay is the difference between data hold time and refresh cycle, and described time delay is the 3-5 second.
The present invention at least includes following beneficial effect: by interrupting concentrated refresh mode, solves can not carry out when refreshing
The problem of read-write, and then enhance the impact of performance of DRAM or eDRAM.When concentrating refreshing, work can be interrupted by read-write,
Thus reduce the upper delay of read-write, make refreshing become more flexible, refresh and become more to coordinate with reading writing working, and then increase
Add work efficiency.
Part is embodied by the further advantage of the present invention, target and feature by description below, and part also will be by this
Invention research and practice and be understood by the person skilled in the art.
Accompanying drawing explanation
Fig. 1 is the existing operating diagram concentrating refreshing apparatus for DRAM or eDRAM；
Fig. 2 is the operating diagram for DRAM or eDRAM refreshing apparatus of the present invention；
Fig. 3 is the system architecture schematic diagram for DRAM or eDRAM refreshing apparatus of the present invention；
Fig. 4 is the internal structure schematic diagram for DRAM or eDRAM refreshing apparatus of the present invention；
Fig. 5 is the embodiment schematic diagram for DRAM or eDRAM refreshing apparatus of the present invention；
Fig. 6 is another embodiment schematic diagram for DRAM or eDRAM refreshing apparatus of the present invention；
Fig. 7 is another embodiment schematic diagram for DRAM or eDRAM refreshing apparatus of the present invention.
Detailed description of the invention
The present invention is described in further detail below in conjunction with the accompanying drawings, so that those skilled in the art are with reference to description
Word can be implemented according to this.
Being illustrated in figure 1 the operating diagram of existing concentration refreshing apparatus, its refresh cycle (data hold time) wraps
Including reading and writing and refresh two parts, it can not be written and read operation refreshing when, makes DRAM or eDRAM thus
Work efficiency step-down.
It is illustrated in figure 2 the operating diagram for DRAM or eDRAM refreshing apparatus of the present invention, this DRAM or eDRAM
The refreshing apparatus setting refresh cycle, described data hold time was the 1-3 second less than data hold time.Within each refresh cycle
Time domain is divided into three parts, and Part I is called concentration refresh time, and Part I is to do concentration to refresh, but when there being read-write
During operation, concentrate refreshing to be interrupted, be preferentially written and read operation；Part II is called delay refresh time, Part II
Starting also is preferentially to be written and read, but when the Part II remaining time be able to finish refresh operation, then carries out forcing brush
New operation, is now not responding to read-write requests.Part III is called access time, and this part only does read-write operation
Fig. 3 is the system architecture schematic diagram for DRAM or eDRAM refreshing apparatus of the present invention, for DRAM or eDRAM
The device refreshed, for performing refresh operation in the data hold time of each data base of DRAM or eDRAM, including: brush
Newly controlling device, it is used for controlling the refresh cycle less than data hold time, and controls to generate the signal whether performing to refresh；In
Depositing control device, it receives read-write requests, and the signal generated according to described refresh control device, sends read-write requests to internal memory
Or refresh command；Wherein, Memory control device is after sending refresh requests to internal memory, during refreshing execution, if connect
Receiving read-write requests, Memory control device is asked for instructions to refresh control device and could be interrupted refreshing and performing read-write operation, refreshes control
Device processed generates in predefined conditions and suspends the signal refreshed.Described predetermined condition is that refreshing can interrupt a time delay, should
Time delay is the difference between data hold time and refresh cycle.Described refresh control device when the refresh cycle starts,
Generate and perform refresh signal, and notify that Memory control device controls internal memory and performs refresh operation, when a predetermined condition is satisfied, refresh
Control device generation and suspend the signal refreshed, and notify that Memory control device controls internal memory and suspends refreshing, perform read-write operation, when
When the cumulative time of read-write operation exceedes time delay, described refresh control device generates execution refresh signal again, and notifies
Memory control device controls internal memory and performs refresh operation, the no longer read-write requests of response memory control device, until having refreshed.
After having refreshed, Memory control device controls internal memory and performs read-write operation, until the next refresh cycle, again performs brush
New operation.The present invention is divided into two parts i.e. Memory control device and refresh control dress for DRAM or eDRAM refreshing apparatus
Putting, refresh control device is used for controlling to generate refresh signal, and Memory control device is used for receiving read-write requests and sending to internal memory
Refresh requests or read-write requests, Memory control device to determine to send read-write to internal memory according to the output of refresh control device
Request or refresh requests, according to the output of Memory control device, refresh control device records whether refreshing is delayed by.
Fig. 4 is the internal structure schematic diagram for DRAM or eDRAM refreshing apparatus of the present invention, wherein refresh control device
Including: refresh cycle depositor 5, it is used for storing the refresh cycle；Refresh delay enumerator 6, it is used for storing current refreshing
Time through being delayed by；Refresh cycle intervalometer 7, it is used for recording the time that the current refresh cycle passes through；Refresh line number
Enumerator 8, it is used for the line number of the data that current refreshing has been refreshed in database of record；Total line number depositor 10, it is used
Store total line number of data in data base；And refresh delay depositor 11, it is used for storing total can being prolonged of refreshing
Slow time, i.e. this time delay.Described refresh control device also includes: flush logic device 9, and it is deposited according to described total line number
Device calculates and has refreshed the required time；When having refreshed required residue always according to the calculating of described refreshing line number enumerator
Between；The beginning of refresh cycle is determined always according to refresh cycle depositor；Determine always according to refresh cycle intervalometer and to have refreshed
Time；Always according to the difference between refresh delay depositor and refresh delay enumerator, determine and suspend the time refreshed.In described
Depositing control device to include: read caching 1, it is used for caching the data read from internal memory；Writing caching 2, it is used for caching and will writing
Enter the data to internal memory；Controlling logic 3, it is used for receiving read-write requests, and the signal generated according to described refresh control device,
Read-write requests or refresh command is sent to internal memory；And memory control signal generator 4, it is used for control the life that logic sends
Order is decoded into the order that internal memory can identify.Each data base configures a set of refreshing apparatus；Or one group has same number of rows
Data base configures a set of refreshing apparatus.Often organize the separate operation of refreshing apparatus of data base.
In one embodiment as it is shown in figure 5, for DRAM or eDRAM method for refreshing, each at DRAM or eDRAM
Perform refresh operation in the data hold time of data base, including: the refresh cycle is set less than data hold time, and refreshing
When cycle starts, refresh control device generates the signal performing to refresh；Memory control device refreshes according to the execution generated
Signal, sends refresh command to internal memory；If in refresh process, Memory control device receives read-write requests, then to refreshing control
Device processed is asked for instructions and could be interrupted refreshing and performing read-write operation；Refresh control device generates and suspends the signal refreshed, this time-out brush
The accumulative applicable time of new signal is a time delay, and this time delay is the difference between data hold time and refresh cycle
Value.
When only arranging one group of refreshing apparatus, the refresh operation of all of data base is identical.Flush logic device 9 is by judging
The state of each refresh register sends to controlling logic 3.Refresh line number enumerator 8 line number of database refresh is counted
Number, time delay when refreshing is counted by refresh delay enumerator 11, when concentrating refreshing, if there being read-write requests, brushes
Newly being interrupted, refresh delay enumerator 6 starts counting up.Whether control logic 3 of issuing flush logic device 9 currently refreshes can be beaten
Disconnected signal, if current refreshing does not complete, and refresh delay enumerator 6 is equal to refresh delay register registers 11,
So flush logic device 9 returns a refreshing and can not be interrupted signal, and controls the logic continuation remaining row of refreshing.If brush
Newly complete, or refresh delay enumerator 6 be less than refresh delay depositor 11, then flush logic device 9 return one permissible
The signal read and write.Refresh cycle depositor 5 stores the time of refresh cycle, and refresh cycle intervalometer starts timing always, when
When refresh cycle intervalometer 7 is equal to the refresh cycle, represents and arrived the next refresh cycle that refresh cycle intervalometer 7 refreshes line number
Enumerator 8, refresh delay enumerator 6 makes zero.
Refer to Fig. 3, Fig. 4, Fig. 5, be below the workflow for DRAM or eDRAM refreshing apparatus of the present invention: be first
First initialization register, refresh cycle depositor 5 stores the refresh cycle of DRAM, and total line number depositor 10 stores DRAM mono-
The line number of individual data base, refresh delay depositor 11 stores and refreshes, when concentrating and refreshing, the time that can be delayed by.Wherein, brush
The data hold time of new time delay+refresh cycle≤memory element, above-mentioned depositor is required in advance before normal work
Configure.
Controlling logic 3 to be used for receiving the order of outside and performing, before accessing memory element, controlling logic 3 will examine
Consulting the signal that flush logic device 9 returns, not performing if being in Flushing status, otherwise perform.Concentrate when entering
During refresh time, needing to access memory element if controlling logic 3, flush logic device 9 needs to judge whether current refreshing can quilt
Interrupting, if refresh delay enumerator 6 is less than refresh delay depositor 11, then current refreshing can be interrupted, and controls logic 3 and opens
Beginning to access memory element, simultaneously refreshed delay counter 6 starts counting up and refreshes the time being delayed by.Refresh cycle intervalometer 7 begins
Eventually in timing, if refresh cycle intervalometer 7 is equal to refresh cycle depositor 5, represents and arrived the next refresh cycle, refresh week
Phase intervalometer, refreshes line number enumerator, refresh delay counter clear.
Described time delay is the 3-5 second because within this period refreshing frequency ensure that to greatest extent stable with
Efficiently.
In another kind of example, as shown in Figure 6, the groundwork flow process of each of which unit and principle and the invention described above
Identical for the workflow of DRAM or eDRAM refreshing apparatus, therefore do not repeat them here, only in the present embodiment, it is provided that multiple
Data base, and each data base has oneself independent refreshing apparatus, and the refreshing between each data base is separate, when one
When individual data base is interrupted in concentrating refresh time, do not interfere with the refreshing of other data bases.
In another kind of example, as it is shown in fig. 7, the groundwork flow process of each of which unit and principle and the invention described above
Identical for the workflow of DRAM or eDRAM refreshing apparatus, therefore do not repeat them here, only in the present embodiment, all of data
Storehouse is all divided into M group, often organizes N number of data base, and often group has an independent refreshing apparatus, and the refreshing between each group is the most only
Vertical, when a group is interrupted in concentrating refresh time, do not interfere with the refreshing of other groups.
As it has been described above, a kind of device refreshed for DRAM or eDRAM provided according to the present invention, solving can not when refreshing
The problem being written and read, and then enhance the impact of performance of DRAM or eDRAM.When concentrating refreshing, work can be read and write
Interrupt, thus reduce the upper delay of read-write, make refreshing become more flexible, refresh and become more to coordinate with reading writing working, and then
Considerably increase work efficiency.
Although embodiment of the present invention are disclosed as above, but it is not restricted in description and embodiment listed
Using, it can be applied to various applicable the field of the invention completely, for those skilled in the art, and can be easily
Realizing other amendment, therefore under the general concept limited without departing substantially from claim and equivalency range, the present invention does not limit
In specific details with shown here as the legend with description.
Claims (10)
1. the device refreshed for DRAM or eDRAM, when the data of each data base at DRAM or eDRAM keep
Interior execution refresh operation, including:
Refresh control device, whether it is used for controlling the refresh cycle less than data hold time, and control to generate and perform to refresh
Signal；
Memory control device, it receives read-write requests, and the signal generated according to described refresh control device, sends to internal memory and read
Write request or refresh command；
Wherein, Memory control device is after sending refresh requests to internal memory, during refreshing execution, if receiving read-write
Asking, Memory control device is asked for instructions to refresh control device and could be interrupted refreshing and performing read-write operation, and refresh control device exists
Generating under predetermined condition and suspend the signal refreshed, described predetermined condition is that refreshing can interrupt a time delay, this time delay
For the difference between data hold time and refresh cycle.
2. the device refreshed for DRAM or eDRAM as claimed in claim 1, wherein, described refresh control device is refreshing
When cycle starts, generate and perform refresh signal, and notify that Memory control device controls internal memory and performs refresh operation, predetermined when meeting
During condition, refresh control device generates and suspends the signal refreshed, and notifies that Memory control device controls internal memory time-out and refreshes, and performs
Read-write operation, when the cumulative time of read-write operation exceedes time delay, described refresh control device again generates and performs refreshing
Signal, and notify that Memory control device controls internal memory and performs refresh operation, the no longer read-write requests of response memory control device, directly
Complete to refreshing.
3. the device refreshed for DRAM or eDRAM as claimed in claim 2, wherein, after having refreshed, Memory control device
Control internal memory and perform read-write operation, until the next refresh cycle, again perform refresh operation.
4. the device refreshed for DRAM or eDRAM as claimed in claim 3, wherein, described refresh control device includes:
Refresh cycle depositor, it is used for storing the refresh cycle；
Refresh delay enumerator, it is used for storing the time that current refreshing has been delayed by；
Refresh cycle intervalometer, it is used for recording the time that the current refresh cycle passes through；
Refreshing line number enumerator, it is used for the line number of the data that current refreshing has been refreshed in database of record；
Total line number depositor, its total line number being used for storing the data in data base；And
Refresh delay depositor, it is used for storing the time that can be delayed by that refreshing is total, i.e. this time delay.
5. the device refreshed for DRAM or eDRAM as claimed in claim 4, wherein, described refresh control device also includes:
Flush logic device, it calculates according to described total line number depositor and has refreshed the required time；Always according to described refreshing
Line number enumerator calculates and has refreshed required remaining time；Opening of refresh cycle is determined always according to refresh cycle depositor
Begin；The time refreshed is determined always according to refresh cycle intervalometer；Count with refresh delay always according to refresh delay depositor
Difference between device, determines and suspends the time refreshed.
6. the device refreshed for DRAM or eDRAM as claimed in claim 5, wherein, described Memory control device includes:
Reading caching, it is used for caching the data read from internal memory；
Writing caching, it is used for caching the data that will be written to internal memory；
Controlling logic, it is used for receiving read-write requests, and the signal generated according to described refresh control device, sends to internal memory and reads
Write request or refresh command；And
Memory control signal generator, it is used for the order becoming internal memory to identify the command decoder controlling logic transmission.
7. the device refreshed for DRAM or eDRAM as claimed in claim 6, wherein, each data base configures a set of refreshing
Device；Or one group of data base with same number of rows configures a set of refreshing apparatus.
8. the device refreshed for DRAM or eDRAM as claimed in claim 7, wherein, the refreshing apparatus phase of each data base
Independent operating mutually.
9. for a DRAM or eDRAM method for refreshing, for the data hold time of each data base at DRAM or eDRAM
Interior execution refresh operation, including:
Refresh cycle is set less than data hold time, and when the refresh cycle starts, refresh control device generates and performs refreshing
Signal；
Memory control device, according to the signal performing to refresh generated, sends refresh command to internal memory；
If in refresh process, Memory control device receives read-write requests, then ask for instructions to refresh control device and could interrupt brush
Newly perform read-write operation；
Refresh control device generates and suspends the signal refreshed, and the accumulative applicable time of this time-out refresh signal is a time delay,
This time delay is the difference between data hold time and refresh cycle.
10. as claimed in claim 9 for DRAM or eDRAM method for refreshing, described time delay is the 3-5 second.
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| CN106601286A (en) * | 2016-12-20 | 2017-04-26 | 湖南国科微电子股份有限公司 | DDRx SDRAM memory refreshing method and memory controller |
| CN107015628A (en) * | 2017-03-30 | 2017-08-04 | 中国科学院计算技术研究所 | It is a kind of towards the low overhead DRAM method for refreshing and system approximately applied |
| CN108337538A (en) * | 2017-01-20 | 2018-07-27 | 创盛视联数码科技（北京）有限公司 | A method of live streaming delay is eliminated based on Flash player |
| TWI641995B (en) * | 2017-02-16 | 2018-11-21 | 中國商上海兆芯集成電路有限公司 | Controller and control method for dynamic random access memory |
| CN111158585A (en) * | 2019-11-27 | 2020-05-15 | 核芯互联科技(青岛)有限公司 | Memory controller refreshing optimization method, device, equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106601286A (en) * | 2016-12-20 | 2017-04-26 | 湖南国科微电子股份有限公司 | DDRx SDRAM memory refreshing method and memory controller |
| CN108337538A (en) * | 2017-01-20 | 2018-07-27 | 创盛视联数码科技（北京）有限公司 | A method of live streaming delay is eliminated based on Flash player |
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| CN111158585A (en) * | 2019-11-27 | 2020-05-15 | 核芯互联科技(青岛)有限公司 | Memory controller refreshing optimization method, device, equipment and storage medium |
| CN111158585B (en) * | 2019-11-27 | 2023-08-01 | 核芯互联科技(青岛)有限公司 | Memory controller refreshing optimization method, device, equipment and storage medium |
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