CN105489240A - DRAM or eDRAM refreshing apparatus and method - Google Patents
DRAM or eDRAM refreshing apparatus and method Download PDFInfo
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- CN105489240A CN105489240A CN201510857644.7A CN201510857644A CN105489240A CN 105489240 A CN105489240 A CN 105489240A CN 201510857644 A CN201510857644 A CN 201510857644A CN 105489240 A CN105489240 A CN 105489240A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
Abstract
The invention discloses a DRAM or eDRAM refreshing apparatus and method. The method comprises the steps that step 1, a storage control apparatus receives a reading-writing request and determines to send the reading-writing request or a refreshing request to a storage apparatus according to an output of a refreshing control apparatus; and step 2, the refreshing control apparatus generates a refreshing signal by control and records whether the refreshing is delayed or not according to an output of the storage control apparatus. According to the DRAM or eDRAM refreshing apparatus and method, the conflicts between the reading-writing and the refreshing can be reduced and the effect of improving the DRAM or eDRAM performance can be achieved.
Description
Technical field
The present invention relates to refresh technique, particularly relate to a kind of devices and methods therefor refreshed for DRAM or eDRAM.
Background technology
In traditional concentrated refresh mode, within each refresh cycle can the section of the having time for refreshing, as shown in Figure 1, within each refresh cycle, time shaft is divided into two parts, portion of time be used for read-write, another part time be used for refresh.
Existing refreshing mode, when DRAM is when refreshing, cannot be carried out read-write operation, be referred to as Dead Time, reducing DRAM handling capacity, and the delay of read-write can become very high.
Summary of the invention
The object of the present invention is to provide a kind of devices and methods therefor refreshed for DRAM or eDRAM, for reducing the collision problem refreshed between read-write, reaching the effect increasing DRAM or eDRAM performance.
To achieve these goals, the invention provides a kind of device refreshed for DRAM or eDRAM, DRAM or eDRAM is provided with storage unit, and this device comprises: memory control device, refresh control device;
Described memory control device, for receiving read-write requests, and determines to send read-write requests or refresh requests to storage unit according to the output of described refresh control device;
Whether described refresh control device, generate refresh signal for controlling, and record refreshing according to the output of described memory control device and be delayed by.
The described device refreshed for DRAM or eDRAM, wherein, described memory control device comprises:
Read buffer memory, for the data that buffer memory reads from storage unit;
Write buffer memory, the data of storage unit will be written to for buffer memory;
Steering logic unit, for receiving read-write requests;
Storage control signal generator, for receiving the order that described steering logic unit sends, and becomes the discernible order of storage unit by this command decoder.
The described device refreshed for DRAM or eDRAM, wherein, described refresh control device comprises:
Refresh cycle register, for storing the refresh cycle;
Refresh delay counter, for storing the time that current refreshing is delayed by;
Refresh cycle timer, for the timing of each refresh cycle;
Refreshed rows counter, for recording the line number of current refreshing;
Flush logic unit, for judge register current by read-write state, and send the state refreshed to described steering logic unit;
Head office's number register, for storing total line number;
Refresh delay register, refreshes total time be delayed by for storing.
The described device refreshed for DRAM or eDRAM, wherein, described flush logic unit, when receiving read-write requests, stops refreshing, control described refresh delay counter and start counting, and send current refreshing whether can by the signal extremely described steering logic unit interrupted.
The described device refreshed for DRAM or eDRAM, wherein, described flush logic unit does not complete in current refreshing, and when the time in described refresh delay counter equals the time in described refresh delay register, return a current refreshing by the signal extremely described steering logic unit interrupted, described steering logic unit to be controlled and continue to refresh; Or when current refreshing has completed or time difference in described refresh delay register and described refresh delay counter is greater than product with every row refresh time of line number difference in described head office number register and described refreshed rows counter, returning one can by the signal read and write to described steering logic unit.
The described device refreshed for DRAM or eDRAM, wherein, when the time in described refresh cycle timer equals the time in described refresh cycle register, described refresh cycle timer, described refreshed rows counter, described refresh delay counter clear.
The described device refreshed for DRAM or eDRAM, wherein, the refresh cycle of described refresh cycle register and the time sum be delayed by of described refresh delay counter are less than data hold time.
The described device refreshed for DRAM or eDRAM, wherein, described refresh control device is one or more, and the refreshing between each described refresh control device is separate.
To achieve these goals, the invention provides a kind of method refreshed for DRAM or eDRAM, DRAM or eDRAM is provided with storage unit, and the method comprises:
Step one, memory control device receives read-write requests, and determines to send read-write requests or refresh requests to storage unit according to the output of refresh control device;
Step 2, whether refresh control device controls to generate refresh signal, and record refreshing according to the output of described memory control device and be delayed by.
The described method refreshed for DRAM or eDRAM, wherein, described refresh control device comprises:
Refresh cycle register, for storing the refresh cycle;
Refresh delay counter, for storing the time that current refreshing is delayed by;
Refresh cycle timer, for the timing of each refresh cycle;
Refreshed rows counter, for recording the line number of current refreshing;
Flush logic unit, for judge register current by read-write state, and send the state refreshed to described steering logic unit;
Head office's number register, for storing total line number;
Refresh delay register, refreshes total time be delayed by for storing.
The described method refreshed for DRAM or eDRAM, wherein, in described step 2, comprising:
Described flush logic unit, when receiving read-write requests, stops refreshing, and controls described refresh delay counter and starts counting, and send current refreshing whether can by the signal that interrupts to the steering logic unit of described memory control device.
The described method refreshed for DRAM or eDRAM, wherein, in described step 2, comprising:
Described flush logic unit does not complete in current refreshing, and when the time in described refresh delay counter equals the time in described refresh delay register, return a current refreshing by the signal extremely described steering logic unit interrupted, described steering logic unit to be controlled and continue to refresh; Or when current refreshing has completed or time difference in described refresh delay register and described refresh delay counter is greater than product with every row refresh time of line number difference in described head office number register and described refreshed rows counter, returning one can by the signal read and write to described steering logic unit.
The described method refreshed for DRAM or eDRAM, wherein, in described step 2, comprising:
When the time in described refresh cycle timer equals the time in described refresh cycle register, described refresh cycle timer, described refreshed rows counter, described refresh delay counter clear.
The described method refreshed for DRAM or eDRAM, wherein, the refresh cycle of described refresh cycle register and the time sum be delayed by of described refresh delay counter are less than data hold time.
The described method refreshed for DRAM or eDRAM, wherein, described refresh control device is one or more, and the refreshing between each described refresh control device is separate.
Compared with prior art, Advantageous Effects of the present invention is:
The invention provides a kind of method refreshed for DRAM or eDRAM, this method for refreshing improves the mode concentrated and refresh, and makes refreshing become more flexible, coordinates to refresh and read/write conflict, thus improve the handling capacity of DRAM, achieve the raising of DRAM performance.Be embodied in following several aspect:
1, by interruptible price concentrated refresh mode, reduce the collision problem refreshed between read-write, reach the effect increasing DRAM or eDRAM performance.
2, concentrate when refreshing and can be interrupted by read-write, reduce read-write and postpone.
3, must set the refresh cycle and refresh can time delay sum be less than data hold time.
4, concentrate when refreshing and can be interrupted by read-write.
5, one group of refreshing apparatus can be had, also can share one group of refreshing apparatus by multiple block bank, also can exclusively enjoy one group of refreshing apparatus by each block bank.
Accompanying drawing explanation
Fig. 1 is traditional concentrated refresh mode schematic diagram;
Fig. 2 is refreshing mode schematic diagram of the present invention;
Fig. 3 is refreshing apparatus structural drawing of the present invention;
Fig. 4 is method for refreshing process flow diagram of the present invention;
Fig. 5 is refreshing mode first embodiment of the present invention;
Fig. 6 is refreshing mode second embodiment of the present invention.
Embodiment
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
As shown in Figure 2, be refreshing mode schematic diagram of the present invention.Figure 2 illustrates the sequential of refreshing, this DRAM refresh circuit sets the retention time that the refresh cycle is less than data.Within each refresh cycle, time domain is divided into three parts, and Part I is called concentrated refresh time, do to concentrate and refresh, but when there being read-write operation, concentrated refreshing can be interrupted, and preferentially carries out read-write operation at Part I; Part II is called delay refresh time, starts also to be preferentially read and write, but when the time of Part II remainder be able to finish refresh operation, then carry out pressure refresh operation, now do not respond read-write requests at Part II.Part III is called access time, only does read-write operation in this section.This method for refreshing may be used for, in DRAM or eDRAM controller, to be described below for dram controller to technical scheme, and this is equally applicable to eDRAM controller.
DRAM is manufactured by MOS technology, uses electric capacity to do storage unit (concerning eDRAM controller, being also use electric capacity to do storage unit).DRAM's is low in energy consumption, and speed is slow.On the other hand, soon and do not need to refresh, but the area of SRAM too greatly and more expensive for SRAM speed, and therefore DRAM application is more extensive than SRAM.
Store information unlike SRAM trigger, DRAM electric capacity stores information.But electric capacity can leak electricity gradually, thus obliterated data.Therefore the storage unit of DRAM needs periodically to refresh, and the refresh cycle is less than data hold time, if storage unit is not refreshed in data hold time, storage information will be lost.
As shown in Figure 3, be refreshing apparatus structural drawing of the present invention, Fig. 4 is method for refreshing process flow diagram of the present invention.
Composition graphs 3,4, this refreshing apparatus 300 is the devices refreshed for DRAM or eDRAM, comprises memory control device 31 and refresh control device 32.DRAM or eDRAM comprises storage unit 33.
Refresh control device 32 generates refresh signal for controlling, memory control device 31 is for receiving read-write requests and sending refresh requests or read-write requests to storage unit 33, memory control device 31 will decide to send read-write requests or refresh requests to storage unit 33 according to the output of refresh control device 32, and whether refresh control device 32 records refreshing according to the output of memory control device 31 and be delayed by.
Further, memory control device 31 comprises:
Read buffer memory 1, for the data that buffer memory reads from storage unit 33.
Write buffer memory 2, the data of storage unit 33 will be written to for buffer memory.
Steering logic unit 3, for receiving read-write requests and sending order to storage unit control signal generator 4.
Storage control signal generator 4, the order that the command decoder for being sent by steering logic unit 3 becomes storage unit 33 to identify.
Further, refresh control device 32, as a block bank, can comprise multiple block bank in device 300.
Further, refresh control device 32 comprises:
Refresh cycle register 5, for storing the refresh cycle.
Refresh delay counter 6, for storing the time that current concentrated refreshing has been delayed by.
Refresh cycle timer 7, for recording the time of current refresh cycle, to each refresh cycle timing.
Refreshed rows counter 8, for recording current refreshing progress, as the line number of current refreshing.
Flush logic unit 9, by judging the several registers (namely judging current whether can read-write) about refreshing, sends the state refreshed to steering logic unit 3.
Head office's number register 10, for storing line number total in a bank.
Refresh delay register 11, refreshes total time that can be delayed by for storing.
Further, the refresh cycle that refresh cycle register 5 stores is less than data hold time.
Further, refresh delay register 11 stores the time of refreshing and can be delayed by, and meet the following conditions: the time sum that refresh cycle and refreshing can be delayed by is less than or equal to data hold time.
In the present invention, altogether only have one group of refreshing apparatus, the refresh operation of all block bank is identical.Flush logic unit 9 is by judging that the state of each refresh register sends to steering logic unit 3.The line number that refreshed rows counter 8 couples of block bank refresh counts, and refresh delay counter 11 counted time delay when refreshing, and when concentrated refreshing, if there is read-write requests, refreshed and was interrupted, and refresh delay counter 6 starts counting.Whether flush logic unit 9 issues the current refreshing of steering logic unit 3 can by the signal interrupted, if current refreshing does not complete, and refresh delay counter 6 equals refresh delay register 11, so flush logic unit 9 returns a refreshing and can not be interrupted signal, and steering logic unit 3 continues to refresh remaining row.Complete if refreshed, or the time in refresh delay counter 6 is less than the time in refresh delay register 11, so flush logic unit 9 return one can by the signal read and write.Refresh cycle register 5 stores the time of refresh cycle, and refresh cycle timer 7 starts timing always, when refresh cycle timer 7 equals the refresh cycle, represent and arrived the next refresh cycle, refresh cycle timer 7, refreshed rows counter 8, refresh delay counter 6 makes zero.
Refer to Fig. 3,4, introduce the course of work of DRAM refresh circuit below in conjunction with Fig. 3 in detail:
Initialization register, refresh cycle register 5 stores the refresh cycle of DRAM, and head office's number register 10 stores the line number of a DRAM block bank, and refresh delay register 11 stores and refreshes the time that can be delayed by when concentrated refreshing.Wherein, refresh can time delay+data hold time of refresh cycle <=storage unit 33, above-mentioned register all needs to configure in advance before normal work.
Steering logic unit 3 is for receiving outside order and performing, and before storage unit access 33, steering logic unit 3 all will check and if be in Flushing status, so just not perform the signal that flush logic unit 9 returns, otherwise perform.
When entering concentrated refresh time, if steering logic unit 3 needs storage unit access 33, flush logic unit 9 needs to judge whether current refreshing can be interrupted, if when refresh delay register 11 and the time difference in refresh delay counter 6 are greater than product with every row refresh time of head office's number register 10 and the line number difference in refreshed rows counter 8, then current refreshing can be interrupted, steering logic unit 3 starts storage unit access 33, and refresh delay counter 6 starts to count the time of refreshing and being delayed by simultaneously.
Refresh cycle timer 7 is all the time in timing, if refresh cycle timer 7 equals refresh cycle register 5, represent and arrived the next refresh cycle, refresh cycle timer 5, refreshed rows counter 8, refresh delay counter 6 make zero.As shown in Figure 5, be refreshing mode first embodiment of the present invention.
In the present embodiment, each block bank has oneself independently refreshing apparatus, and the refreshing between each block bank is separate.Each block bank has oneself refreshing apparatus, when a block bank is interrupted in concentrated refresh time, can not have influence on the refreshing of other blocks bank.
As shown in Figure 6, be refreshing mode second embodiment of the present invention.
In the present embodiment, all block bank are divided into M group, often organize N number of block bank, and often group has an independently refreshing apparatus, and the refreshing between each group is separate.As shown above, often organize the refreshing apparatus of oneself, when a group is interrupted in concentrated refresh time, the refreshing of other groups can not be had influence on.
Further, in a DRAM or eDRAM controller, a refreshing apparatus is only had.
Further, all block Bank share a refreshing apparatus, and all block bank Flushing status are identical.
Further, each block bank has oneself refreshing apparatus, and the refreshing of each block bank is separate.
Further, several blocks bank can be divided into one group, often organizing block bank has a refreshing apparatus.
Further, each organizes the refreshing apparatus that block bank has oneself, and the block bank Flushing status often in group is identical, and the refreshing between group is separate.
The present invention improves and concentrates the mode refreshed to make refreshing become more flexible, effectively can coordinate the conflict between reading and writing and refreshing, improve the handling capacity of DRAM, thus improve the performance of DRAM.
Certainly; the present invention also can have other various embodiments; when not deviating from the present invention's spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and distortion according to the present invention, but these change accordingly and are out of shape the protection domain that all should belong to the claim appended by the present invention.
Claims (15)
1., for the device that DRAM or eDRAM refreshes, DRAM or eDRAM is provided with storage unit, it is characterized in that, this device comprises: memory control device, refresh control device;
Described memory control device, for receiving read-write requests, and determines to send read-write requests or refresh requests to storage unit according to the output of described refresh control device;
Whether described refresh control device, generate refresh signal for controlling, and record refreshing according to the output of described memory control device and be delayed by.
2. the device refreshed for DRAM or eDRAM according to claim 1, it is characterized in that, described memory control device comprises:
Read buffer memory, for the data that buffer memory reads from storage unit;
Write buffer memory, the data of storage unit will be written to for buffer memory;
Steering logic unit, for receiving read-write requests;
Storage control signal generator, for receiving the order that described steering logic unit sends, and becomes the discernible order of storage unit by this command decoder.
3. the device refreshed for DRAM or eDRAM according to claim 2, it is characterized in that, described refresh control device comprises:
Refresh cycle register, for storing the refresh cycle;
Refresh delay counter, for storing the time that current refreshing is delayed by;
Refresh cycle timer, for the timing of each refresh cycle;
Refreshed rows counter, for recording the line number of current refreshing;
Flush logic unit, for judge register current by read-write state, and send the state refreshed to described steering logic unit;
Head office's number register, for storing total line number;
Refresh delay register, refreshes total time be delayed by for storing.
4. the device refreshed for DRAM or eDRAM according to claim 3, it is characterized in that, described flush logic unit is when receiving read-write requests, stop refreshing, control described refresh delay counter and start counting, and send current refreshing whether can by the signal extremely described steering logic unit interrupted.
5. the device refreshed for DRAM or eDRAM according to claim 4, it is characterized in that, described flush logic unit does not complete in current refreshing, and when the time in described refresh delay counter equals the time in described refresh delay register, return a current refreshing by the signal extremely described steering logic unit interrupted, described steering logic unit to be controlled and continue to refresh; Or when current refreshing has completed or time difference in described refresh delay register and described refresh delay counter is greater than product with every row refresh time of line number difference in described head office number register and described refreshed rows counter, returning one can by the signal read and write to described steering logic unit.
6. the device refreshed for DRAM or eDRAM according to claim 3, it is characterized in that, when the time in described refresh cycle timer equals the time in described refresh cycle register, described refresh cycle timer, described refreshed rows counter, described refresh delay counter clear.
7. the device refreshed for DRAM or eDRAM according to claim 3, it is characterized in that, the refresh cycle of described refresh cycle register and the time sum be delayed by of described refresh delay counter are less than data hold time.
8., according to the described device refreshed for DRAM or eDRAM arbitrary in claim 1-7, it is characterized in that, described refresh control device is one or more, and the refreshing between each described refresh control device is separate.
9., for the method that DRAM or eDRAM refreshes, DRAM or eDRAM is provided with storage unit, it is characterized in that, the method comprises:
Step one, memory control device receives read-write requests, and determines to send read-write requests or refresh requests to storage unit according to the output of refresh control device;
Step 2, whether refresh control device controls to generate refresh signal, and record refreshing according to the output of described memory control device and be delayed by.
10. the method refreshed for DRAM or eDRAM according to claim 9, it is characterized in that, described refresh control device comprises:
Refresh cycle register, for storing the refresh cycle;
Refresh delay counter, for storing the time that current refreshing is delayed by;
Refresh cycle timer, for the timing of each refresh cycle;
Refreshed rows counter, for recording the line number of current refreshing;
Flush logic unit, for judge register current by read-write state, and send the state refreshed to described steering logic unit;
Head office's number register, for storing total line number;
Refresh delay register, refreshes total time be delayed by for storing.
11. methods refreshed for DRAM or eDRAM according to claim 10, is characterized in that, in described step 2, comprising:
Described flush logic unit, when receiving read-write requests, stops refreshing, and controls described refresh delay counter and starts counting, and send current refreshing whether can by the signal that interrupts to the steering logic unit of described memory control device.
12. methods refreshed for DRAM or eDRAM according to claim 11, is characterized in that, in described step 2, comprising:
Described flush logic unit does not complete in current refreshing, and when the time in described refresh delay counter equals the time in described refresh delay register, return a current refreshing by the signal extremely described steering logic unit interrupted, described steering logic unit to be controlled and continue to refresh; Or when current refreshing has completed or time difference in described refresh delay register and described refresh delay counter is greater than product with every row refresh time of line number difference in described head office number register and described refreshed rows counter, returning one can by the signal read and write to described steering logic unit.
13. methods refreshed for DRAM or eDRAM according to claim 10, is characterized in that, in described step 2, comprising:
When the time in described refresh cycle timer equals the time in described refresh cycle register, described refresh cycle timer, described refreshed rows counter, described refresh delay counter clear.
14. methods refreshed for DRAM or eDRAM according to claim 10, it is characterized in that, the refresh cycle of described refresh cycle register and the time sum be delayed by of described refresh delay counter are less than data hold time.
15. according to the described method refreshed for DRAM or eDRAM arbitrary in claim 9-14, and it is characterized in that, described refresh control device is one or more, and the refreshing between each described refresh control device is separate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510857644.7A CN105489240A (en) | 2015-11-30 | 2015-11-30 | DRAM or eDRAM refreshing apparatus and method |
| PCT/CN2016/086092 WO2017092282A1 (en) | 2015-11-30 | 2016-06-17 | Device and method for refreshing dram or edram |
| CN201611080414.5A CN106856098B (en) | 2015-11-30 | 2016-11-30 | Device and method for refreshing DRAM or eDRAM |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510857644.7A CN105489240A (en) | 2015-11-30 | 2015-11-30 | DRAM or eDRAM refreshing apparatus and method |
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| CN201611080414.5A Active CN106856098B (en) | 2015-11-30 | 2016-11-30 | Device and method for refreshing DRAM or eDRAM |
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| WO2017092282A1 (en) * | 2015-11-30 | 2017-06-08 | 中国科学院计算技术研究所 | Device and method for refreshing dram or edram |
| CN106128499A (en) * | 2016-06-28 | 2016-11-16 | 田彬 | A kind of device refreshed for DRAM or eDRAM and method for refreshing |
| CN106601286A (en) * | 2016-12-20 | 2017-04-26 | 湖南国科微电子股份有限公司 | DDRx SDRAM memory refreshing method and memory controller |
| CN110058793A (en) * | 2018-01-19 | 2019-07-26 | 华为技术有限公司 | A kind of refreshing processing method, device, system and Memory Controller Hub |
| CN110058793B (en) * | 2018-01-19 | 2020-04-28 | 华为技术有限公司 | Refreshing processing method, device and system and memory controller |
| US11037615B2 (en) | 2018-01-19 | 2021-06-15 | Huawei Technologies Co., Ltd. | Refresh processing method, apparatus, and system, and memory controller |
| CN111400246A (en) * | 2020-03-26 | 2020-07-10 | 广州酷旅旅行社有限公司 | Asynchronous file importing method and device, computer equipment and storage medium |
| CN111400246B (en) * | 2020-03-26 | 2023-12-19 | 广州酷旅旅行社有限公司 | Asynchronous file import method, device, computer equipment and storage medium |
| CN115101104A (en) * | 2022-07-18 | 2022-09-23 | 山东浪潮科学研究院有限公司 | Method for improving DDR read-write efficiency based on FPGA |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106856098A (en) | 2017-06-16 |
| CN106856098B (en) | 2020-02-28 |
| WO2017092282A1 (en) | 2017-06-08 |
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Application publication date: 20160413 |