TWI447741B - Dynamic random access memory unit and data refreshing method thereof - Google Patents

Description

Dynamic random access memory unit and data updating method thereof

The present invention relates to a semiconductor random access memory (DRAM) semiconductor memory device technology, and in particular to a memory cell in a specified word line address interval for refresh operation (refresh operation) Semiconductor memory component technology to reduce power consumption.

Dynamic Random Access Memory (DRAM) uses the amount of charge stored in a capacitor to represent a binary bit "1" or "0", so each memory cell of the DRAM requires only one capacitor and one switch (or The transistor can be used.

In actual operation, the capacitance in the DRAM may leak, and the potential difference of the capacitor is insufficient, so that the data stored in the DRAM disappears. Therefore, the DRAM must enter a refresh mode to periodically update all the memory cells (also It can be called data charging/data refreshing operation to ensure the correctness of information stored in DRAM. 1 and FIG. 2, FIG. 1 is a block diagram of a conventional dynamic random access memory unit 10, and FIG. 2 is a signal waveform diagram of a data updating method of the conventional dynamic random access memory unit 10. Referring to FIG. 1, the DRAM memory unit 10 includes a memory array 110, an update clock unit 120, and a word line address counter 130. The memory array 110 includes a plurality of word lines and a plurality of bit lines. The word lines and the bit lines vertically intersect each other, and each of the intersections has a memory cell to store one bit. Bit information for binary (ie "0" or "1").

The update clock unit 120 receives an entry update signal S _{ref to} know if the DRAM unit 10 is in the update mode. In the update mode, the update clock unit 120 generates an update clock signal S _clk (refer to FIG. 2 ), and the word line address counter 130 cyclically calculates the word line address WL by updating the clock signal S _clk . In this embodiment, each pulse interval of the update clock signal S _clk is 8 μs, so that the stored data in the memory array 110 is incorrect by avoiding the update period being too long. In addition, the word line address WL of the memory array is composed of three-digit hexadecimal digits, and the word line address WL interval of the memory array 110 is from 000 _H to FFF _H , so the word line address counter 130 is counted from 000 _H to FFF _H and then counted again from 000 _H. The memory array 110 continuously receives the updated clock signal S _clk and the word line address WL in the update mode to periodically update all of the memory cells in the memory array 110. However, when DRAM is applied, not all memory cells have stored information, so when charging/updating a memory cell that does not have stored information, it will cause excessive charge consumption.

In this way, a variety of DRAM update technologies are derived to reduce the power consumption of the DRAM in the update mode. A self-refresh memory device is disclosed in U.S. Patent No. 6,590,822, which utilizes an update command signal generated by a computer system to mask one or more bits in a word line address data. In advance, some RAM memory blocks (such as 1/2, 1/4, 1/8, or 1/16, etc.) are provided in advance to store data and update operations, and other memory blocks are disabled. And no need to use, in order to reduce power consumption. However, the above memory device can only store data at a fixed rate of memory capacity (eg, 1/2, 1/4, 1/8, etc.), and an excessive memory capacity consumes excess power when not refreshing data. The memory block of the data, but the memory capacity that is too small does not match the computer system. The above-mentioned memory device cannot allow the computer system to specify the memory capacity that it needs to use in detail, thereby reducing the degree of freedom of application of the computer system to the DRAM.

The present invention provides a dynamic random access memory unit that updates a memory cell corresponding to a specified word line address interval in an update mode, and stops updating a memory cell located outside a specified word line address interval, thereby Reduce power consumption in the update mode.

In another aspect, the present invention provides a data update method for a dynamic random access memory unit, which updates a memory cell of a specified word line address interval and stops updating at a specified word line when updating a mode. Memory cells outside the address range to reduce power consumption.

The invention provides a dynamic random access memory unit, which comprises a memory array, an update address module and an update control module. The memory array includes a plurality of memory cells, and the update address module loops to generate an updated word line address in the update mode. The update control module is coupled to the memory array and the update address module, and the update control module first obtains a start word line address and a corresponding end word line address, wherein the start word line positions The address and the corresponding end word line address may form a memory word line address interval. The update control module determines whether the updated word line address is located in the memory word line address range, and if the updated word line address is located in the memory word line address range, the updated word line address is updated. The corresponding memory cell performs a data charging operation, otherwise the data charging operation is stopped.

In another aspect, the present invention provides a data update method for a dynamic random access memory cell, wherein the dynamic random access memory cell includes a memory array having a plurality of memory cells, and the dynamic random access memory The unit data update method includes the following steps. The start word line address and the corresponding end word line address are obtained, and the start word line address and the corresponding end word line address may form a memory word line address interval. Moreover, an update address module is provided in the update mode, and the update address module cyclically generates an update word line address. And determining that the updated word line address is located in the memory word line address interval to perform a data charging operation on the memory cell corresponding to the updated word line address, otherwise the data charging operation is stopped.

Based on the above, the embodiment of the present invention uses the instructions of the computer system or the DRAM to self-detect the result of the memory cell with the data to obtain the word line address interval. Then, in the update mode, the update control module determines whether the updated word line address is in the word line address interval, so that the memory cell in the word line address interval is updated, and the update is located in the character. The memory cells outside the line address interval, thereby reducing the power consumption of the DRAM in the update mode. In addition, in this embodiment, a plurality of word line address intervals can be obtained by determining whether the memory cells in the DRAM have stored information, thereby achieving the purpose of updating only the memory cells having the data.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 3. FIG. 3 is a block diagram of a dynamic random access memory (DRAM) unit 30 according to an embodiment of the invention. The DRAM unit 30 includes a memory array 110, an update address module 310, and an update control module 320. The memory array 110 of the present embodiment has a plurality of memory cells, the architecture of which is shown in FIG. 4. FIG. 4 is a block diagram of the memory array 110 according to an embodiment of the invention.

Referring to FIG. 4, the memory array 110 includes a memory block 410, a word line decoder 420, and a signal comparator module 430 in this embodiment. The memory block 410 includes word lines WL1 WLWLN and bit lines BL1 BBLM, where N is the total number of word lines WL1 WL WLN, and M is the number of memory cells corresponding to each word line WL1 WL WLN. . The word lines WL1 WL WLN and the bit lines BL1 BBLM intersect perpendicularly to each other, and each intersection has a memory cell (not shown) for storing a binary bit (ie, "0" or "1"). For the bit information, the memory array 110 can select the corresponding M-bit data according to one of the word lines WL1 WLWLN to perform the operations of depositing/removing/updating. The word line decoder 420 receives and decodes the word line address WL to obtain one of the word lines WL1 WL WLN of the corresponding word line address WL. The signal comparator module 430 can receive the update clock signal S _clk and the clock enable signal S _en in the update mode to compare and store the information stored in the M memory cells selected by the word line address WL. action.

Referring to FIG. 3, the update address module 310 receives the incoming update signal S _{ref to} know whether the computer system causes the DRAM unit 30 to be in the update mode, and the update address module 310 cyclically generates the update character when updating the mode. Line address WL. In particular, the update address module 310 includes an update clock unit 120 and a word line address counter 130. The update clock unit 120 generates an update clock signal S _clk when in the update mode. The address counter 130 is coupled to the update clock unit 120, and the address counter 130 receives and cyclically accumulates the word line address WL according to the update clock signal S _clk (also referred to as the update word line address in this embodiment). WL). In other words, the "loop generation" referred to herein is the word line address counter 130 incrementing the update word line address WL by "1" according to each pulse of each update clock signal S _clk , when accumulating to the memory When the last word line address of the body array 110 is re-integrated from the first word line address of the memory array 110, the memory cells having data in the memory array 110 are periodically refreshed.

The update control module 320 of FIG. 3 is coupled to the memory array 110 and the update address module 310. In this embodiment, the update control module 320 includes a temporary storage unit 330 and an address interval determination unit 340. The temporary storage unit 330 is configured to store the start word line address WLstart1~WLstartP and the end word line address WLstop1~WLstopP, and the start word line address WLstart1~WLstartP and the corresponding end word line address WLstop1~ WLstopP can form P memory word line address intervals, where P is a positive integer, and memory word line address intervals do not overlap each other.

In this embodiment, the address interval determining unit 340 of FIG. 3 is coupled to the temporary storage unit 330, and the address interval determining unit 340 is configured to determine whether the updated word line address WL is located in the memory word line address interval. AR1, AR2. If the update word line address WL is located in the memory word line address interval AR1, AR2, the address range judgment unit 340 transfers the update word line address WL and the update enable signal _Sen to the memory array 110. To perform a data charging operation on the memory cell corresponding to the updated word line address WL. In addition, in order to reduce the circuit area of the DRAM unit 30, the address range determining unit 340 of the present embodiment has a digital logic circuit as its embodiment, but the present invention should not be limited thereto.

In order to make the present invention more familiar to those skilled in the art, the data updating method and flow of the DRAM unit 30 will be described in detail below, and as illustrated in FIG. 5 and FIG. 6, FIG. 5 is an embodiment according to the present invention. A flowchart illustrating a method of updating data of the DRAM unit 30, and FIG. 6 is a waveform diagram illustrating a method of updating data of the DRAM unit 30 according to an embodiment of the present invention. Referring to FIG. 5, first in step S510, the DRAM unit 30 first obtains the start word line address WLstart1~WLstartP and the corresponding end word line address WLstop1~WLStopP, thereby forming a memory word line address interval AR1. , AR2. It is assumed here that the computer system first provides two memory word line address intervals AR1, AR2 (that is, P=2, and is illustrated on the memory block 410 of FIG. 4) to the update control module 320 of the DRAM unit 30. The first memory word line address interval AR1 is composed of WLstart1(005 _H ) to WLstop1(0FE _H ), and the second memory word line address interval AR2 is from WLstart2(200 _H ) to WLstop1 (2FF _H ) is formed, wherein the number of memory word line address intervals that the DRAM unit 30 can store and compare depends on the capacity of the temporary storage unit.

In addition, in step S510 of the embodiment, the obtained start word line address WLstart1~WLstartP and end word line address WLstop1~WLstopP can be preset by special instructions of the computer system. In other words, the computer system can pre-set the required memory capacity so that the computer system can access the data using only the memory word line address intervals AR1, AR2. Alternatively, in other embodiments, the DRAM unit 30 can detect the memory cells in the memory array 110 that have data therein, and set the start word line address of the memory word line address intervals AR1 and AR2. The end word line address is stored in the temporary storage unit 330 for the purpose of updating the memory cell having the data.

Referring to FIG. 5, when the update mode is entered, step S520 is performed, and the update address module 310 cyclically generates the update word line address WL (as shown in FIG. 6). Next, in step S530, the address section determining unit 340 receives and determines whether the updated word line address WL is located in the memory word line address interval AR1, AR2. When the update word line address WL is located in the memory word line address interval AR1, AR2 (for example, the update word line address WL is located between 005 _H ~ 0FE _H and 200 _H ~ 2FF _H ), the process proceeds to the step S540, address update interval judgment unit 340 so that the enabling signal S _en located starting potential (e.g. high potential), so that memory array 110 of the signal comparator module 430 (FIG. 4) capable of updating characters The memory cell corresponding to the line address WL performs a data charging operation.

In contrast, when the update word line address WL is outside the memory word line address interval AR1, AR2 (for example, the update word line address WL is located at 000 _H ~ 004 _H , 0FF _H ~ 1FF _H and 300 _H ~ between FFF _H), then the step S530 into the step S540, the address update interval judgment unit 340 so that the enabling signal S _en in the closed potential (e.g., low), so that the signal data comparator module 430 stops the charging operation. Further, after the end of step S540 and step S550, the process returns to step S530 to continuously determine whether the updated word line address WL is located in the memory word line address intervals AR1, AR2.

In other embodiments consistent with the present invention, as shown in FIG. 7, FIG. 7 is a block diagram of a DRAM unit in accordance with another embodiment of the present invention. Referring to FIG. 7, the difference between the embodiment and the foregoing embodiment is that the temporary storage unit of the embodiment can utilize a plurality of start word line address register 710_1~710_P and end word line address temporary storage. The 720_1~720_P are replaced. Each start word line address register 710_i may store a start word line address WLstarti, and the corresponding end word line address register 720_i stores an end word line address WLstopi, wherein i is a positive integer and 1≦i≦P. The other detailed procedures and descriptions of the present embodiment are included in the above embodiments, and thus are not described herein.

In summary, the embodiment of the present invention uses the instructions of the computer system or the DRAM to detect the result of the memory cell with the data to obtain the word line address interval. Then, in the update mode, the update control module determines whether the updated word line address is in the word line address interval, so that the memory cell in the word line address interval is updated, and the update is located in the character. The memory cells outside the line address interval, thereby reducing the power consumption of the DRAM in the update mode. In addition, in this embodiment, a plurality of word line address intervals can be obtained by determining whether the memory cells in the DRAM have stored information, thereby achieving the purpose of updating only the memory cells having the data.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 30. . . Dynamic random access memory (DRAM) unit

110. . . Memory array

120. . . Update clock unit

130. . . Word line address counter

310. . . Update address module

320. . . Update control module

330. . . Staging unit

340. . . Address interval judgment unit

410. . . Memory block

420. . . Character line decoder

430. . . Signal comparator module

710_1~710_P. . . Start word line address register

720_1~720_P. . . End character line address register

AR1, AR2. . . Memory word line address interval

BL1~BLM. . . Bit line

S _ref . . . Enter the update signal

S _clk . . . Update clock signal

S _en . . . Update enable signal

WL. . . Update character line address

WL1~WLN. . . Word line

WLstart1~WlstartP. . . Start word line address

WLstop1~WlstopP. . . End character line address

S510~S550. . . step

1 is a block diagram of a conventional dynamic random access memory unit.

2 is a waveform diagram of a data updating method of a conventional dynamic random access memory unit.

FIG. 3 is a block diagram of a dynamic random access memory unit according to an embodiment of the invention.

4 is a block diagram of a memory array in accordance with an embodiment of the invention.

FIG. 5 is a flow chart illustrating a method for updating data of a dynamic random access memory unit according to an embodiment of the invention.

FIG. 6 is a waveform diagram illustrating a method for updating a data of a dynamic random access memory unit according to an embodiment of the invention.

FIG. 7 is a block diagram of a dynamic random access memory unit according to another embodiment of the present invention.

30. . . Dynamic random access memory (DRAM) unit

110. . . Memory array

120. . . Update clock unit

130. . . Word line address counter

310. . . Update address module

320. . . Update control module

330. . . Staging unit

340. . . Address interval judgment unit

S _ref . . . Enter the update signal

S _clk . . . Update clock signal

S _en . . . Update enable signal

WL. . . Update character line address

Claims (10)

A dynamic random access memory unit includes: a memory array including a plurality of memory cells; an update address module for cyclically generating an updated word line address in an update mode; and an update The control module is coupled to the memory array and the update address module, and the update control module obtains at least one start word line address and corresponding at least one end word line address, the start words The meta-line address and the corresponding end word line address form at least one memory word line address interval, and the update control module determines that the update word line address is located in the memory word line position The address interval is performed by performing a data charging operation on the memory cells corresponding to the updated word line address, otherwise the data charging operation is stopped. The dynamic random access memory unit of claim 1, wherein the update address module comprises: an update clock unit for generating an updated clock signal in the update mode; and an address The counter is coupled to the update clock unit, and the address counter receives and cyclically accumulates the update word line address according to the update clock signal. The dynamic random access memory unit of claim 1, wherein the update control module comprises: a temporary storage unit, configured to store the start word line addresses and the end word lines Address; and The address range determining unit is coupled to the temporary storage unit, and the address interval determining unit forms the memory word line by the starting word line address and the corresponding ending word line address An address interval, and determining whether the updated word line address is located in the memory word line address interval, wherein the updated word line address is located in the memory word line address interval, the bit The address interval judging unit transmits the update address and an update enable signal to the memory array to perform the data charging operation on the memory cells corresponding to the word line address. The DRAM unit of claim 3, wherein the temporary storage unit comprises: a plurality of start word line address register, each start word line address register is used for Storing one of the start word line address addresses; and a plurality of end word line address registers, each end word line address register for storing one of the end word line addresses, Each of the start word line addresses and each of the corresponding end word line addresses form the memory word line address intervals. The dynamic random access memory unit according to claim 1, wherein the memory word line address intervals are preset by a computer system, and the computer system includes the dynamic random access memory unit. And the memory word line address intervals are composed of the start word line address and the corresponding end word line address. The dynamic random access memory unit of claim 1, wherein the dynamic random access memory unit automatically detects the memory cells having the stored data to obtain and store the start word lines. The address and the end word line address are addressed to the update control module. A data update method for a dynamic random access memory unit, the dynamic random access memory unit includes a memory array having a plurality of memory cells, and the data update method of the dynamic random access memory unit includes: obtaining at least one a start word line address and a corresponding at least one end word line address, wherein the start word line address and the corresponding end word line address form at least one memory word line address interval Providing an update address module in an update mode, the update address module cyclically generating an update word line address; and determining that the update word line address is located in the memory word line address The interval is performed by performing a data charging operation on the memory cells corresponding to the updated word line address, otherwise the data charging operation is stopped. The method for updating a data random access memory unit according to claim 7, wherein the step of generating the updated word line address comprises: generating an updated clock signal in the update mode; The update clock signal cyclically accumulates the updated word line address. The method for updating data of the dynamic random access memory unit according to claim 7, wherein the step of obtaining the start word line address and the corresponding end word line address comprises: providing a computer a system, the computer system pre-sets the memory word line address intervals, the computer system includes the dynamic random access memory unit, and the memory word line address intervals are from the start word lines The address is composed of the corresponding end word line addresses. The method for updating data of the dynamic random access memory unit according to claim 7, wherein the step of obtaining the start word line address and the corresponding end word line address comprises: the dynamic random The access memory unit automatically detects the memory cells having the stored data to obtain and store the start word line addresses and the end word line addresses.