CN102376346B - Dynamic random access memory unit and its data update method - Google Patents
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Abstract
The invention discloses a dynamic random access memory unit and its data update method. The dynamic random access memory unit comprises a memory array, an update address module and an update control module, wherein the memory array comprises a plurality of memory cells; the update address module cycles to generate an update word-line address during the updating mode; the update control module is coupled with the memory array and the update address module; the update control module acquires an initial word-line address and a corresponding end word-line address to form a memory word-line address area; the update control module determines and updates the word-line address to locate at memory word-line address area so as to carry out data charging operation on the corresponding memory cell of the update word-line address; otherwise, the data charging operation is stopped to reduce the consumption of electric energy during the updating mode.
Description
Technical field
The present invention relates to a kind of dynamic RAM (Dynamic Random Access Memory, abbreviation DRAM) semiconductor memory component technology, and particularly relevant for a kind of storage unit in designated word line address section, upgrade the semiconductor memory component technology of (refresh) operation, so as to reducing power consumption.
Background technology
Dynamic RAM (DRAM) is to utilize the number of capacitor memory accumulate lotus to represent " 1 " or " 0 " of a binary bit bit, so each storage unit of DRAM only needs an electric capacity and a switch (or transistor).
During practical operation, electric capacity in DRAM has leaky, and cause the potential difference (PD) of electric capacity not enough, the data that DRAM stores are disappeared, therefore DRAM must enter renewals (refresh) pattern with the bit cell period to whole upgrade (also can be described as data charging/Refresh Data) and operate, guarantee to store in DRAM the correctness of information.As shown in Figures 1 and 2, Fig. 1 is the block scheme of known dynamic random access storage unit 10, and Fig. 2 is the signal waveforms of the data-updating method of known dynamic random access storage unit 10.Please refer to Fig. 1, dynamic random access storage unit 10 comprises memory array 110, refresh clock pulse unit 120 and wordline address counter 130.Memory array 110 comprises many word lines (word line) and multiple bit lines (bit line), these word lines and the mutual square crossing of bit line, each point of crossing all possesses a storage unit, so as to storing the order information an of binary bit (that is " 0 " or " 1 ").
Refresh clock pulse unit 120 receives one and enters (entry) update signal S
ref, so as to learning whether DRAM unit 10 is arranged in more new model.When new model more, refresh clock pulse unit 120 produces refresh clock pulse signal S
clk(please refer to Fig. 2), wordline address counter 130 is by refresh clock pulse signal S
clkcarry out cycle calculations wordline address WL.In the present embodiment, refresh clock pulse signal S
clkeach pulse distance be 8 μ s, long and allow storage error in data in memory array 110 so as to avoiding the update cycle.In addition, the wordline address WL of memory array is comprised of three-figure 16 carry digits, and the wordline address WL interval of memory array 110 is by 000
hto FFF
h, so wordline address counter 130 is by 000
hsequentially count up to FFF
hafter just again by 000
hstart counting.Memory array 110 is in more continuing to receive refresh clock pulse signal S in new model
clkand wordline address WL, periodically all storage unit in memory array 110 are upgraded.But in application, during DRAM, be not that all storage unit all have storage information, therefore, when not thering is the storage unit of storage information and charge/upgrade, will cause unnecessary charge consumption.
Whereby, the renewal technology that just derives multiple DRAM is to reduce the power consumption of DRAM when the new model more.In United States Patent (USP) the 6th, 590, in No. 822, disclose a kind of memory storage that can self (self-refresh), the update instruction signal that this memory storage utilizes computer system to produce covers the one or more bits in (mask) wordline address data, provide in advance the RAM memory block of part (such as 1/2,1/4,1/8 or 1/16 etc.) store data and upgrade operation, other memory block is closed (disable) and is not needed and uses, so as to reducing power consumption.Yet, above-mentioned memory storage only can be stored data to the fixed multiplying power of memory span (as: 1/2,1/4,1/8 etc.), excessive memory span can expend unnecessary electric energy in not storing the memory block of data when refresh data, but too small memory span is inconsistent computer system, does not use.Above-mentioned memory storage cannot allow computer system at length specify out the memory span of its required use, thereby reduces computer system for the application degree of freedom of DRAM.
Summary of the invention
For problems of the prior art, the object of the present invention is to provide a kind of dynamic random access storage unit, it upgrades the interval corresponding storage unit of the wordline address of appointment when new model more, and stop upgrading, be positioned at the storage unit outside designated word line address section, so as to reduce the consumption of electric energy in new model more.
In another angle, the invention provides a kind of data-updating method of dynamic random access storage unit, it upgrades the storage unit of designated word line address section when new model more, and stops upgrading and be positioned at the storage unit outside designated word line address section, so as to reducing power consumption.
The present invention proposes a kind of dynamic random access storage unit, comprises memory array, scheduler module and upgrades control module.Memory array comprises a plurality of storage unit, and scheduler module will circulate and produce one and upgrade wordline address when new model more.Upgrade control module and be coupled to memory array and scheduler module, and upgrade control module and first obtain initial wordline address and corresponding end wordline address, wherein, these initial wordline addresses can form memory word line address section with corresponding end wordline address.Upgrade control module and judge whether above-mentioned renewal wordline address is positioned at memory word line address section, if upgrade wordline address, be positioned at memory word line address section, just to upgrading the corresponding storage unit of wordline address, carry out data charging operations, otherwise just stop data charging operations.
With another viewpoint, the invention provides a kind of data-updating method of dynamic random access storage unit, and this dynamic random access storage unit comprises the memory array with a plurality of storage unit, and the data-updating method of dynamic random access storage unit comprises the following steps.Obtain initial wordline address and corresponding end wordline address, these initial wordline addresses can form memory word line address section with corresponding end wordline address.And, a scheduler module is provided when new model more, this scheduler module circulation produces upgrades wordline address.And, judge that above-mentioned renewal wordline address is positioned at memory word line address section, to carry out data charging operations to upgrading the corresponding storage unit of wordline address, otherwise just stop data charging operations.
Based on above-mentioned, embodiments of the invention utilize the instruction of computer system or the result that DRAM detects the storage unit with data voluntarily, obtain wordline address interval.Then when new model more, upgrade control module judgement and upgrade wordline address whether in above-mentioned wordline address interval, so as to the storage unit in wordline address interval is carried out to more new element, and stop upgrading, be positioned at the storage unit outside wordline address interval, and then reduce DRAM at the power consumption of new model more.In addition, the present embodiment also can by judge storage unit in DRAM whether storage information to obtain a plurality of wordline addresses interval, so as to reaching, only need renewal to possess the object of the storage unit of data.
Beneficial effect of the present invention is, in sum, embodiments of the invention utilize the instruction of computer system or the result that DRAM detects the storage unit that possesses data voluntarily, obtain wordline address interval.Then when new model more, upgrade control module judgement and upgrade wordline address whether in above-mentioned wordline address interval, so as to the storage unit in wordline address interval is carried out to more new element, and stop upgrading, be positioned at the storage unit outside wordline address interval, and then reduce DRAM at the power consumption of new model more.In addition, the present embodiment also can by judge storage unit in DRAM whether storage information to obtain a plurality of wordline addresses interval, so as to reaching, only need renewal to possess the object of the storage unit of data.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the block scheme of known dynamic random access storage unit.
Fig. 2 is the oscillogram of the data-updating method of known dynamic random access storage unit.
Fig. 3 is the block scheme according to a kind of dynamic random access storage unit described in one embodiment of the invention.
Fig. 4 is the block scheme according to the memory array described in one embodiment of the invention.
Fig. 5 is the process flow diagram according to the data-updating method of one embodiment of the invention explanation dynamic random access storage unit.
Fig. 6 is the oscillogram according to the data-updating method of one embodiment of the invention explanation dynamic random access storage unit.
Fig. 7 is the block scheme according to the dynamic random access storage unit described in another embodiment of the present invention.
Wherein, description of reference numerals is as follows:
10,30: dynamic RAM (DRAM) unit
110: memory array
120: refresh clock pulse unit
130: wordline address counter
310: scheduler module
320: upgrade control module
330: temporary storage location
340: address section judging unit
410: memory block
420: wordline decoder
430: signal comparator module
710_1～710_P: banner word line address register
720_1～720_P: finish wordline address register
AR1, AR2: memory word line address section
BL1～BLM: bit line
S
ref: enter update signal
S
clk: refresh clock pulse signal
S
en: upgrade enable signal
WL: upgrade wordline address
WL1～WLN: word line
WLstart1～WlstartP: initial wordline address
WLstop1～WlstopP: finish wordline address
S510～S550: step
Embodiment
Please refer to Fig. 3, Fig. 3 is the block scheme according to a kind of dynamic RAM (DRAM) unit 30 described in one embodiment of the invention.DRAM unit 30 comprises memory array 110, scheduler module 310 and upgrades control module 320.The memory array 110 of the present embodiment has a plurality of storage unit, and as shown in Figure 4, Fig. 4 is the block scheme according to the memory array 110 described in one embodiment of the invention to its framework.
Please refer to Fig. 4, memory array 110 comprises memory block 410, wordline decoder 420 and signal comparator module 430 in the present embodiment.Memory block 410 comprises word line WL1～WLN and bit line BL1～BLM, and wherein N is the sum of word line WL1～WLN, and M is the corresponding storage unit number of each word line WL1～WLN.Word line WL1～WLN and the mutual square crossing of bit line BL1～BLM, and each point of crossing all possesses a storage unit (not shown), so as to storing the order information an of binary bit (that is " 0 " or " 1 "), memory array 110 can select corresponding M bit (M-bit) data to deposit in/to take out/to upgrade and wait action according to word line WL1～WLN wherein.Wordline decoder 420 receives also wordline address WL is decoded, with obtain corresponding wordline address WL word line WL1～WLN one of them.Signal comparator module 430 can receive refresh clock pulse signal S when new model more
clkwith time clock enable signal S
en, the selected M of a wordline address WL storage unit is stored to comparison and the data charging action of information.
Please continue to refer to Fig. 3, scheduler module 310 receives and enters update signal S
ref, so as to learning whether computer system allows DRAM unit 30 be arranged in more new model, and scheduler module 310 circulation when new model more produces and upgrades wordline address WL.In detail, scheduler module 310 comprises refresh clock pulse unit 120 and wordline address counter 130.Refresh clock pulse unit 120 produces refresh clock pulse signal S when new model more
clk.Address counter 130 is coupled to refresh clock pulse unit 120, and address counter 130 receives and according to refresh clock pulse signal S
clkthe accumulative total that circulates wordline address WL (also claiming to upgrade wordline address WL in the present embodiment).In other words, " circulation produces " of indication is that wordline address counter 130 is according to each refresh clock pulse signal S herein
clkeach pulse renewal wordline address WL is added to " 1 ", when being added to last wordline address of memory array 110, again by first wordline address of memory array 110, start accumulative total again, so as to the bit cell period in memory array 110 with data is carried out to Refresh Data.
The renewal control module 320 of Fig. 3 is coupled to memory array 110 and scheduler module 310.In the present embodiment, upgrade control module 320 and comprise temporary storage location 330 and address section judging unit 340.Temporary storage location 330 is in order to store initial wordline address WLstart1～WLstartP and to finish wordline address WLstop1～WLstopP, these initial wordline address WLstart1～WLstartP can form P memory word line address section with corresponding end wordline address WLstop1～WLstopP, wherein P is positive integer, and memory word line address section is mutually not overlapping.
In the present embodiment, the address section judging unit 340 of Fig. 3 is coupled to temporary storage location 330, and whether address section judging unit 340 is arranged in memory word line address section AR1, AR2 in order to judgement renewal wordline address WL.If when renewal wordline address WL is positioned at memory word line address section AR1, AR2, address section judging unit 340 will upgrade wordline address WL and upgrade enable signal S
enbe sent to memory array 110, correspondence is upgraded to the storage unit of wordline address WL, carry out data charging operations.In addition, in order to dwindle the circuit area of DRAM unit 30, the address section judging unit 340 of the present embodiment is usingd DLC (digital logic circuit) as its embodiment, but the present invention should be as limit.
In order to cause those skilled in the art can more understand the present invention, below describe data-updating method and the flow process of DRAM unit 30 in detail, examples illustrates it, as shown in Fig. 5 and Fig. 6, Fig. 5 is the process flow diagram according to the data-updating method of one embodiment of the invention explanation DRAM unit 30, and Fig. 6 is the oscillogram according to the data-updating method of one embodiment of the invention explanation DRAM unit 30.Please refer to Fig. 5, first in step S510, initial wordline address WLstart1～WLstartP and corresponding end wordline address WLstop1～WLstopP are obtained in DRAM unit 30 first, so as to forming memory word line address section AR1, AR2.In this hypothesis computer system, provide in advance 2 memory word line address section AR1, AR2 (that is P=2, and be illustrated on the memory block 410 of Fig. 4) to the renewal control module 320 of DRAM unit 30, the 1st memory word line address section AR1 is by WLstart1 (005
h) to WLstop1 (0FE
h) institute form, the 2nd memory word line address section AR2 is by WLstart2 (200
h) to WLstop1 (2FF
h) institute forms, wherein, DRAM unit 30 can be determined according to the capacity of temporary storage location for storage and the number of memory word line address section relatively.
In addition,, in the step S510 of the present embodiment, obtained initial wordline address WLstart1～WLstartP and end wordline address WLstop1～WLstopP can be preset by the special instruction of computer system.In other words, computer system can preset its required memory span, so as to allowing computer system only utilize memory word line address section AR1, AR2 to carry out access data.Or, in other embodiment, DRAM unit 30 voluntarily in detection of stored device array 110 its inside there is the storage unit of data, and the initial wordline address of memory word line address section AR1, AR2 is stored in temporary storage location 330 with finishing wordline address, to realize the object of upgrading the storage unit with data.
Please continue to refer to Fig. 5, when entering more new model, just perform step S520,310 circulations of scheduler module produce upgrades wordline address WL (as shown in Figure 6).Then in step S530, address section judging unit 340 receives and judges whether upgrade wordline address WL is positioned at memory word line address section AR1, AR2.When upgrading when wordline address WL is arranged in memory word line address section AR1, AR2, (for example upgrade wordline address WL and be positioned at 005
h～0FE
h, 200
h～2FF
hbetween), just entering step S540, address section judging unit 340 allows and upgrades enable signal S
enthe signal comparator module 430 (as shown in Figure 4) in memory array 110 is positioned at initiate potential (for example noble potential), so that can be carried out data charging operations to upgrading the corresponding storage unit of wordline address WL.
Relatively, when upgrading when wordline address WL is positioned at outside memory word line address section AR1, AR2, (for example upgrade wordline address WL and be positioned at 000
h～004
h, 0FF
h～1FF
hand 300
h～FFF
hbetween), just by step S530, entering step S540, address section judging unit 340 allows and upgrades enable signal S
enbe positioned at and close current potential (for example electronegative potential), so that signal comparator module 430 stops data charging operations.In addition,, after step S540 and step S550 finish, just get back to step S530 and upgrade wordline address WL and whether be arranged in memory word line address section AR1, AR2 to continue judgement.
In other embodiment according to the invention, as shown in Figure 7, Fig. 7 is the block scheme according to the DRAM unit described in another embodiment of the present invention.Please refer to Fig. 7, the present embodiment and above-described embodiment difference be, the temporary storage location of the present embodiment can utilize a plurality of banner word line address register 710_1～710_P and finish wordline address register 720_1～720_P as replacement.Each banner word line address register 710_i can store an initial wordline address WLstarti, and corresponding end wordline address register 720_i stores one and finish wordline address WLstopi, and wherein i is positive integer and 1≤i≤P.And other thin portion flow processs of the present embodiment have been included in the various embodiments described above with explanation, therefore do not repeat them here.
In sum, embodiments of the invention utilize the instruction of computer system or the result that DRAM detects the storage unit that possesses data voluntarily, obtain wordline address interval.Then when new model more, upgrade control module judgement and upgrade wordline address whether in above-mentioned wordline address interval, so as to the storage unit in wordline address interval is carried out to more new element, and stop upgrading, be positioned at the storage unit outside wordline address interval, and then reduce DRAM at the power consumption of new model more.In addition, the present embodiment also can by judge storage unit in DRAM whether storage information to obtain a plurality of wordline addresses interval, so as to reaching, only need renewal to possess the object of the storage unit of data.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention, any affiliated technical field technician, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion of defining depending on claim.
Claims (6)
1. a dynamic random access storage unit, comprising:
One memory array, it comprises a plurality of storage unit;
One scheduler module, be used to one more new model time circulation produce one and upgrade wordline address; And
One upgrades control module, be coupled to this memory array and this scheduler module, this renewal control module obtains at least one initial wordline address and corresponding at least one end wordline address, described initial wordline address forms at least one memory word line address section with corresponding described end wordline address, and this renewal control module judges that this renewal wordline address is positioned at described memory word line address section, so that the corresponding described storage unit of this renewal wordline address is carried out to a data charging operations, otherwise stop this data charging operations
Wherein this scheduler module comprises:
One refresh clock pulse unit, is used to this renewal mode producing one refresh clock pulse signal; And
One address counter, is coupled to this refresh clock pulse unit, and this address counter receives and circulates and add up this renewal wordline address according to this refresh clock pulse signal,
This dynamic random access storage unit automatically detects the described storage unit with storage data, to obtain and to store described initial wordline address and described end wordline address upgrades control module to this.
2. dynamic random access storage unit as claimed in claim 1, is characterized in that, this renewal control module comprises:
One temporary storage location, in order to store described initial wordline address and described end wordline address; And
One address section judging unit, be coupled to this temporary storage location, this address section judging unit forms described memory word line address section by described initial wordline address with corresponding described end wordline address, and judge whether this renewal wordline address is positioned at described memory word line address section, wherein when this renewal wordline address is positioned at described memory word line address section, this address section judging unit upgrades enable signal by this scheduler and and is sent to this memory cell array, carrying out this data charging operations to upgrading the described storage unit of wordline address.
3. dynamic random access storage unit as claimed in claim 2, is characterized in that, this temporary storage location comprises:
A plurality of banner word line address registers, each banner word line address register is in order to store one of described initial wordline address; And
A plurality of end wordline address registers, each finishes wordline address register in order to store one of described end wordline address, and wherein each initial wordline address finishes wordline address with corresponding each and forms described memory word line address section.
4. dynamic random access storage unit as claimed in claim 1, it is characterized in that, described memory word line address section is preset by a computer system, this computer system comprises this dynamic random access storage unit, and described memory word line address section is comprised of with corresponding described end wordline address described initial wordline address.
5. a data-updating method for dynamic random access storage unit, this dynamic random access storage unit comprises a memory array with a plurality of storage unit, the data-updating method of this dynamic random access storage unit comprises:
Obtain at least one initial wordline address and corresponding at least one end wordline address, wherein said initial wordline address forms at least one memory word line address section with corresponding described end wordline address;
In one, more during new model, provide a scheduler module, this scheduler module circulation produces one and upgrades wordline address; And
Judge that this renewal wordline address is positioned at described memory word line address section, so that the corresponding described storage unit of this renewal wordline address is carried out to a data charging operations, otherwise stop this data charging operations,
Wherein the step of this renewal wordline address of circulation generation comprises:
In this, more during new model, produce a refresh clock pulse signal; And
According to this refresh clock pulse signal, circulate and add up this renewal wordline address, and
Obtaining described initial wordline address comprises with the step of corresponding described end wordline address:
This dynamic random access storage unit detects the described storage unit with storage data automatically, to obtain and to store described initial wordline address and described end wordline address.
6. the data-updating method of dynamic random access storage unit as claimed in claim 5, is characterized in that, obtains described initial wordline address and comprises with the step of corresponding described end wordline address:
One computer system is provided, this computer system presets described memory word line address section, this computer system comprises this dynamic random access storage unit, and described memory word line address section is comprised of with corresponding described end wordline address described initial wordline address.
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| US11302383B2 (en) * | 2018-12-10 | 2022-04-12 | Etron Technology, Inc. | Dynamic memory with sustainable storage architecture |
| CN113470711B (en) | 2020-03-30 | 2023-06-16 | 长鑫存储技术有限公司 | Memory block and memory |
| CN111611119B (en) * | 2020-05-27 | 2023-04-07 | 合肥工大高科信息科技股份有限公司 | Method and system for realizing on-line self-check of RAM (random Access memory) under real-time operating system |
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