CN102376346A - Dynamic random access memory unit and its data update method - Google Patents
Dynamic random access memory unit and its data update method Download PDFInfo
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Abstract
The invention discloses a dynamic random access memory unit and its data update method. The dynamic random access memory unit comprises a memory array, an update address module and an update control module, wherein the memory array comprises a plurality of memory cells; the update address module cycles to generate an update word-line address during the updating mode; the update control module is coupled with the memory array and the update address module; the update control module acquires an initial word-line address and a corresponding end word-line address to form a memory word-line address area; the update control module determines and updates the word-line address to locate at memory word-line address area so as to carry out data charging operation on the corresponding memory cell of the update word-line address; otherwise, the data charging operation is stopped to reduce the consumption of electric energy during the updating mode.
Description
Technical field
The present invention relates to a kind of dynamic RAM (Dynamic Random Access Memory; Abbreviation DRAM) semiconductor memory component technology; And particularly upgrade the semiconductor memory component technology that (refresh) operates in the storage unit of specifying the word line address section, so as to reducing power consumption relevant for a kind of.
Background technology
Dynamic RAM (DRAM) is to utilize the number of capacitor memory accumulate lotus to represent " 1 " or " 0 " of a binary bit bit, so each storage unit of DRAM only needs an electric capacity and a switch (or transistor) to get final product.
During practical operation; Electric capacity among the DRAM has leaky; And cause the potential difference (PD) of electric capacity not enough; Make data that DRAM stored disappear, so DRAM must get into renewals (refresh) pattern and operate so that whole bit cell period property ground is upgraded (also can be described as data charging/Refresh Data), guarantee the correctness of canned data among the DRAM.Like Fig. 1 and shown in Figure 2, Fig. 1 is the block scheme of known dynamic random access storage unit 10, and Fig. 2 is the signal waveforms of the data-updating method of known dynamic random access storage unit 10.Please with reference to Fig. 1, dynamic random access storage unit 10 comprises memory array 110, refresh clock pulse unit 120 and wordline address counter 130.Memory array 110 comprises many word lines (word line) and multiple bit lines (bit line), the mutual square crossing of these word lines and bit line, and each point of crossing all possesses a storage unit, so as to storing the order information an of binary bit (that is " 0 " or " 1 ").
Refresh clock pulse unit 120 receives one and gets into (entry) update signal S
Ref, whether be arranged in more new model so as to learning DRAM unit 10.When new model more, refresh clock pulse unit 120 produces refresh clock pulse signal S
Clk(please with reference to Fig. 2), wordline address counter 130 is through refresh clock pulse signal S
ClkCome cycle calculations wordline address WL.In present embodiment, refresh clock pulse signal S
ClkEach pulse distance be 8 μ s, long and let storage error in data in the memory array 110 so as to avoiding the update cycle.In addition, the wordline address WL of memory array then is made up of three-figure 16 carry digits, and the wordline address WL interval of memory array 110 is then by 000
HTo FFF
H, so wordline address counter 130 is by 000
HCount up to FFF in regular turn
HAfter just again by 000
HBegin counting.Memory array 110 is in more continuing to receive refresh clock pulse signal S in the new model
ClkAnd wordline address WL, periodically all storage unit in the memory array 110 are upgraded.But when using DRAM, be not that all storage unit all have canned data, therefore the storage unit with canned data charged/when upgrading, will cause unnecessary charge consumption.
Whereby, the renewal technology that just derives multiple DRAM is to reduce the power consumption of DRAM when the new model more.In United States Patent (USP) the 6th; 590; But disclose the memory storage of a kind of self (self-refresh) in No. 822, the update instruction signal that this memory storage utilizes computer system to produce covers the one or more bits in (mask) wordline address data, provides the RAM memory block of part (for example 1/2,1/4,1/8 or 1/16 etc.) to store data and upgrade operation in advance; Other memory block is then closed (disable) and need not be used, so as to reducing power consumption.Yet; Above-mentioned memory storage only can be stored data to the fixedly multiplying power of memory span (as: 1/2,1/4,1/8 etc.); Excessive memory span can expend unnecessary electric energy in not storing the memory of data block when refresh data, do not use but too small memory span then is inconsistent computer system.Above-mentioned memory storage can't let computer system at length specify out the memory span of its required use, thereby reduces the application degree of freedom of computer system for DRAM.
Summary of the invention
To the problem that exists in the prior art; The object of the present invention is to provide a kind of dynamic random access storage unit; It upgrades the interval corresponding storage unit of the wordline address of appointment when new model more; Be positioned at the outer storage unit of designated word line address section and stop to upgrade, so as in new model more, reducing the consumption of electric energy.
In another angle; The present invention provides a kind of data-updating method of dynamic random access storage unit; It will specify the storage unit of word line address section to upgrade when new model more, and stop to upgrade and be positioned at the outer storage unit of designated word line address section, so as to reducing power consumption.
The present invention proposes a kind of dynamic random access storage unit, comprises memory array, scheduler module and upgrades control module.Memory array comprises a plurality of storage unit, and the scheduler module will circulate when new model more and produce one and upgrade wordline address.Upgrade control module and be coupled to memory array and scheduler module; And upgrade control module and at first obtain initial wordline address and corresponding end wordline address; Wherein, these initial wordline addresses can form storer word line address section with corresponding end wordline address.Upgrade control module and judge whether above-mentioned renewal wordline address is positioned at storer word line address section; Be positioned at storer word line address section if upgrade wordline address; Just carry out the data charging operations to upgrading the pairing storage unit of wordline address, otherwise just stop the data charging operations.
With another viewpoint; The present invention provides a kind of data-updating method of dynamic random access storage unit; And this dynamic random access storage unit comprises the memory array with a plurality of storage unit, and the data-updating method of dynamic random access storage unit comprises the following steps.Obtain initial wordline address and corresponding end wordline address, these initial wordline addresses can form storer word line address section with corresponding end wordline address.And, a scheduler module is provided when new model more, this scheduler module circulation produces upgrades wordline address.And, judge that above-mentioned renewal wordline address is positioned at storer word line address section, carrying out the data charging operations, otherwise just stop the data charging operations to upgrading the pairing storage unit of wordline address.
Based on above-mentioned, embodiments of the invention utilize the instruction of computer system or the result that DRAM detects the storage unit with data voluntarily, obtain the wordline address interval.Then when new model more; Upgrading control module judges and upgrades wordline address whether in above-mentioned wordline address interval; So as to the storage unit in the wordline address interval is carried out more new element; And stop to upgrade the storage unit that is positioned at outside the wordline address interval, and then reduce DRAM at the power consumption of new model more.In addition, present embodiment also can through judge among the DRAM storage unit whether canned data to obtain a plurality of wordline address interval, only need renewal to possess the purpose of the storage unit of data so as to reaching.
Beneficial effect of the present invention is that in sum, embodiments of the invention utilize the instruction of computer system or the result that DRAM detects the storage unit that possesses data voluntarily, obtain the wordline address interval.Then when new model more; Upgrading control module judges and upgrades wordline address whether in above-mentioned wordline address interval; So as to the storage unit in the wordline address interval is carried out more new element; And stop to upgrade the storage unit that is positioned at outside the wordline address interval, and then reduce DRAM at the power consumption of new model more.In addition, present embodiment also can through judge among the DRAM storage unit whether canned data to obtain a plurality of wordline address interval, only need renewal to possess the purpose of the storage unit of data so as to reaching.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended accompanying drawing to elaborate as follows.
Description of drawings
Fig. 1 is the block scheme of known dynamic random access storage unit.
Fig. 2 is the oscillogram of the data-updating method of known dynamic random access storage unit.
Fig. 3 is the block scheme according to the described a kind of dynamic random access storage unit of one embodiment of the invention.
Fig. 4 is the block scheme according to the described memory array of one embodiment of the invention.
Fig. 5 is the process flow diagram according to the data-updating method of one embodiment of the invention explanation dynamic random access storage unit.
Fig. 6 is the oscillogram according to the data-updating method of one embodiment of the invention explanation dynamic random access storage unit.
Fig. 7 is the block scheme according to the described dynamic random access storage unit of another embodiment of the present invention.
Wherein, description of reference numerals is following:
10,30: dynamic RAM (DRAM) unit
110: memory array
120: the refresh clock pulse unit
130: the wordline address counter
310: the scheduler module
320: upgrade control module
330: temporary storage location
340: the address section judging unit
410: memory block
420: wordline decoder
430: the signal comparator module
710_1～710_P: initial word line address register
720_1～720_P: finish the wordline address register
AR1, AR2: storer word line address section
BL1～BLM: bit line
S
Ref: get into update signal
S
Clk: the refresh clock pulse signal
S
En: upgrade enable signal
WL: upgrade wordline address
WL1～WLN: word line
WLstart1～WlstartP: initial wordline address
WLstop1～WlstopP: finish wordline address
S510～S550: step
Embodiment
Please with reference to Fig. 3, Fig. 3 is the block scheme according to the described a kind of dynamic RAM of one embodiment of the invention (DRAM) unit 30.DRAM unit 30 comprises memory array 110, scheduler module 310 and upgrades control module 320.The memory array 110 of present embodiment has a plurality of storage unit, and its framework is as shown in Figure 4, and Fig. 4 is the block scheme according to the described memory array 110 of one embodiment of the invention.
Please with reference to Fig. 4, memory array 110 comprises memory block 410, wordline decoder 420 and signal comparator module 430 in present embodiment.Memory block 410 comprises word line WL1～WLN and bit line BL1～BLM, and wherein N is the sum of word line WL1～WLN, and M then is the pairing storage unit number of each word line WL1～WLN.Word line WL1～WLN and the mutual square crossing of bit line BL1～BLM; And each point of crossing all possesses a storage unit (not shown); So as to storing the order information an of binary bit (that is " 0 " or " 1 "), memory array 110 can select corresponding M bit (M-bit) data to deposit in/to take out/to upgrade and wait action according to word line WL1～WLN wherein.Wordline decoder 420 receives and wordline address WL is decoded, with word line WL1～WLN of obtaining corresponding wordline address WL one of them.Signal comparator module 430 can receive refresh clock pulse signal S when new model more
ClkWith time clock enable signal S
En, move with the data charging that relatively reaches of the selected M of a wordline address WL storage unit being carried out canned data.
Please continue with reference to figure 3, scheduler module 310 receives and gets into update signal S
Ref, whether let DRAM unit 30 be arranged in more new model so as to learning computer system, and scheduler module 310 circulation when new model more produces and upgrades wordline address WL.In detail, scheduler module 310 comprises refresh clock pulse unit 120 and wordline address counter 130.Refresh clock pulse unit 120 produces refresh clock pulse signal S when new model more
ClkAddress counter 130 is coupled to refresh clock pulse unit 120, and address counter 130 receives and according to refresh clock pulse signal S
ClkThe accumulative total that circulates wordline address WL (in present embodiment, also claiming to upgrade wordline address WL).In other words, " circulation produces " of indication is that wordline address counter 130 is according to each refresh clock pulse signal S here
ClkEach pulse will upgrade wordline address WL and add " 1 "; When being added to last word line address of memory array 110; Again begin accumulative total by first wordline address of memory array 110 again, so as to the bit cell period property that has data in the memory array 110 is carried out Refresh Data.
The renewal control module 320 of Fig. 3 is coupled to memory array 110 and scheduler module 310.In present embodiment, upgrade control module 320 and comprise temporary storage location 330 and address section judging unit 340.Temporary storage location 330 is in order to store initial wordline address WLstart1～WLstartP and to finish wordline address WLstop1～WLstopP; These initial wordline address WLstart1～WLstartP can form P storer word line address section with corresponding end wordline address WLstop1～WLstopP; Wherein P is a positive integer, and storer word line address section is not overlapping each other.
In present embodiment, the address section judging unit 340 of Fig. 3 is coupled to temporary storage location 330, and address section judging unit 340 is in order to judge whether upgrade wordline address WL is arranged in storer word line address section AR1, AR2.If when renewal wordline address WL is positioned at storer word line address section AR1, AR2, address section judging unit 340 will upgrade wordline address WL and upgrade enable signal S
EnBe sent to memory array 110, carry out the data charging operations with the storage unit of correspondence being upgraded wordline address WL.In addition, in order to dwindle the circuit area of DRAM unit 30, as its embodiment, but the present invention should be as limit with DLC(digital logic circuit) for the address section judging unit 340 of present embodiment.
In order to cause those skilled in the art can understand the present invention more; Below specify the data-updating method and the flow process of DRAM unit 30; And illustrate it; Like Fig. 5 and shown in Figure 6, Fig. 5 is the process flow diagram according to the data-updating method of one embodiment of the invention explanation DRAM unit 30, and Fig. 6 then is the oscillogram according to the data-updating method of one embodiment of the invention explanation DRAM unit 30.Please with reference to Fig. 5, at first in step S510, initial wordline address WLstart1～WLstartP and corresponding end wordline address WLstop1～WLstopP are at first obtained in DRAM unit 30, so as to forming storer word line address section AR1, AR2.In this hypothesis computer system 2 storer word line address section AR1, AR2 (that is P=2 are provided in advance; And be illustrated on the memory block 410 of Fig. 4) to the renewal control module 320 of DRAM unit 30, the 1st storer word line address section AR1 is by WLstart1 (005
H) to WLstop1 (0FE
H) form, the 2nd storer word line address section AR2 is then by WLstart2 (200
H) to WLstop1 (2FF
H) form, wherein, DRAM unit 30 can supply to store with the number of relatively storer word line address section to be decided according to the capacity of temporary storage location.
In addition, in the step S510 of present embodiment, the initial wordline address WLstart1～WLstartP that is obtained and end wordline address WLstop1～WLstopP can be preestablished by the special instruction of computer system.In other words, computer system can preestablish its required memory span, so as to letting computer system only utilize storer word line address section AR1, AR2 to come access data.Perhaps; In other embodiment; DRAM unit 30 voluntarily in the detection of stored device array 110 its inside had the storage unit of data; And the initial wordline address of storer word line address section AR1, AR2 is stored in the temporary storage location 330 with finishing wordline address, to realize upgrading the purpose of storage unit with data.
Please continue with reference to figure 5, just execution in step S520 when getting into more new model, 310 circulations of scheduler module produce upgrades wordline address WL (as shown in Figure 6).Then in step S530, address section judging unit 340 receives and judges whether upgrade wordline address WL is positioned at storer word line address section AR1, AR2.(for example upgrade wordline address WL and be positioned at 005 when wordline address WL is arranged in storer word line address section AR1, AR2 when upgrading
H～0FE
H, 200
H～2FF
HBetween), just getting into step S540, address section judging unit 340 lets and upgrades enable signal S
EnThe signal comparator module 430 (as shown in Figure 4) in the memory array 110 is positioned at initiate potential (for example noble potential), so that can be carried out the data charging operations to upgrading the pairing storage unit of wordline address WL.
Relatively, (for example upgrade wordline address WL and be positioned at 000 when wordline address WL is positioned at outside storer word line address section AR1, the AR2 when upgrading
H～004
H, 0FF
H～1FF
HAnd 300
H～FFF
HBetween), just getting into step S540 by step S530, address section judging unit 340 lets and upgrades enable signal S
EnBe positioned at and close current potential (for example electronegative potential), so that signal comparator module 430 stops the data charging operations.In addition, after step S540 and step S550 end, just get back to step S530 to continue to judge whether upgrade wordline address WL is arranged in storer word line address section AR1, AR2.
In other embodiment according to the invention, as shown in Figure 7, Fig. 7 is the block scheme according to the described DRAM of another embodiment of the present invention unit.Please with reference to Fig. 7, present embodiment and the foregoing description difference are that the temporary storage location of present embodiment can utilize a plurality of initial word line address register 710_1～710_P and finish wordline address register 720_1～720_P as replacement.Each initial word line address register 710_i can store an initial wordline address WLstarti, and corresponding end wordline address register 720_i then stores one and finish wordline address WLstopi, and wherein i is positive integer and 1≤i≤P.And other thin portion flow processs of present embodiment have been included among above-mentioned each embodiment with explanation, so do not repeat them here.
In sum, embodiments of the invention utilize the instruction of computer system or the result that DRAM detects the storage unit that possesses data voluntarily, obtain the wordline address interval.Then when new model more; Upgrading control module judges and upgrades wordline address whether in above-mentioned wordline address interval; So as to the storage unit in the wordline address interval is carried out more new element; And stop to upgrade the storage unit that is positioned at outside the wordline address interval, and then reduce DRAM at the power consumption of new model more.In addition, present embodiment also can through judge among the DRAM storage unit whether canned data to obtain a plurality of wordline address interval, only need renewal to possess the purpose of the storage unit of data so as to reaching.
Though the present invention discloses as above with embodiment; Right its is not in order to qualification the present invention, and any affiliated person skilled is not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that claim defines.
Claims (10)
1. dynamic random access storage unit comprises:
One memory array, it comprises a plurality of storage unit;
One scheduler module, be used to one more new model time circulation produce one and upgrade wordline address; And
One upgrades control module; Be coupled to this memory array and this scheduler module; This renewal control module obtains at least one initial wordline address and corresponding at least one end wordline address; Said initial wordline address forms at least one storer word line address section with corresponding said end wordline address; And this renewal control module judges that this renewal wordline address is positioned at said storer word line address section, so that the pairing said storage unit of this renewal wordline address is carried out a data charging operations, otherwise stops this data charging operations.
2. dynamic random access storage unit as claimed in claim 1 is characterized in that, this scheduler module comprises:
One refresh clock pulse unit is used to this renewal mode producing one refresh clock pulse signal; And
One address counter is coupled to this refresh clock pulse unit, and this address counter receives and according to this refresh clock pulse signal this renewal wordline address of accumulative total that circulates.
3. dynamic random access storage unit as claimed in claim 1 is characterized in that, this renewal control module comprises:
One temporary storage location is in order to store said initial wordline address and said end wordline address; And
One address section judging unit; Be coupled to this temporary storage location; This address section judging unit forms said storer word line address section with said initial wordline address with corresponding said end wordline address; And judge whether this renewal wordline address is positioned at said storer word line address section; Wherein when this renewal wordline address was positioned at said storer word line address section, this address section judging unit upgraded enable signal with this scheduler and and is sent to this memory cell array, will the said storage unit that should upgrade wordline address being carried out this data charging operations.
4. dynamic random access storage unit as claimed in claim 3 is characterized in that, this temporary storage location comprises:
A plurality of initial word line address registers, each initial word line address register is in order to store one of said initial wordline address; And
A plurality of end wordline address registers, each finishes the wordline address register in order to store one of said end wordline address, and wherein each initial wordline address finishes wordline address with corresponding each and forms said storer word line address section.
5. dynamic random access storage unit as claimed in claim 1; It is characterized in that; Said storer word line address section is preestablished by a computer system; This computer system comprises this dynamic random access storage unit, and said storer word line address section is made up of with corresponding said end wordline address said initial wordline address.
6. dynamic random access storage unit as claimed in claim 1; It is characterized in that; This dynamic random access storage unit automatically detects the said storage unit with storage data, to obtain and to store said initial wordline address and said end wordline address upgrades control module to this.
7. the data-updating method of a dynamic random access storage unit, this dynamic random access storage unit comprises the memory array with a plurality of storage unit, the data-updating method of this dynamic random access storage unit comprises:
Obtain at least one initial wordline address and corresponding at least one end wordline address, wherein said initial wordline address forms at least one storer word line address section with corresponding said end wordline address;
In one more during new model, a scheduler module is provided, this scheduler module circulation produces one and upgrades wordline address; And
Judge that this renewal wordline address is positioned at said storer word line address section, so that the pairing said storage unit of this renewal wordline address is carried out a data charging operations, otherwise stop this data charging operations.
8. the data-updating method of dynamic random access storage unit as claimed in claim 7 is characterized in that, the step that circulation produces this renewal wordline address comprises:
More during new model, produce a refresh clock pulse signal in this; And
According to this refresh clock pulse signal circulate accumulative total this renewal wordline address.
9. the data-updating method of dynamic random access storage unit as claimed in claim 7 is characterized in that, obtains said initial wordline address and comprises with the step of corresponding said end wordline address:
One computer system is provided; This computer system preestablishes said storer word line address section; This computer system comprises this dynamic random access storage unit, and said storer word line address section is made up of with corresponding said end wordline address said initial wordline address.
10. the data-updating method of dynamic random access storage unit as claimed in claim 7 is characterized in that, obtains said initial wordline address and comprises with the step of corresponding said end wordline address:
This dynamic random access storage unit detects the said storage unit with storage data automatically, to obtain and to store said initial wordline address and said end wordline address.
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| CN105448321A (en) * | 2014-08-20 | 2016-03-30 | 华邦电子股份有限公司 | Memory access method |
| CN111583974A (en) * | 2018-12-10 | 2020-08-25 | 钰创科技股份有限公司 | Dynamic random access memory with maintained memory architecture |
| CN111611119A (en) * | 2020-05-27 | 2020-09-01 | 合肥工大高科信息科技股份有限公司 | Method and system for realizing on-line self-check of RAM (random Access memory) under real-time operating system |
| US11869578B2 (en) | 2020-03-30 | 2024-01-09 | Changxin Memory Technologies, Inc. | Memory bank and memory |
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| CN102376346B (en) | 2014-02-12 |
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