KR101660455B1 - Pre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power, and related systems and methods - Google Patents

Abstract

Embodiments disclosed herein include methods and apparatus for pre-charging bit lines of a static random access memory (SRAM) prior to data access to reduce leakage power. The memory access logic circuit receives a memory access request including a data entry address to be accessed in a first data access path of the SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided on a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of a memory access request to prevent pre-charging bit lines of the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit may enable pre-charge of the SRAM data array prior to data access so that the pre-charge circuit does not add latency to the first data access path.

Description

BACKGROUND OF THE INVENTION [0001] Pre-charging and related systems and methods of bit lines of static random access memory (SRAM) prior to data access to reduce leakage power are disclosed in U.S. Patent Application Serial No. 10 / REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS}

Priority Claim

[0001] This application claims the benefit of U.S. Provisional Patent Application serial number filed May 6, 2013, entitled " METHODS AND APPARATUS FOR PRE-CHARGING OF STATIC RANDOM ACCESS MEMORY (SRAM) DATA ARRAYS PRIOR TO ACCESS FOR SAVING POWER LEAKAGE " 61 / 819,744, which is hereby incorporated by reference in its entirety.

[0002] This application claims the benefit of U.S. Provisional Application No. 60 / 542,502, filed October 9, 2013, entitled "PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS" Patent application Ser. No. 14 / 049,312, which is hereby incorporated by reference in its entirety.

The technical field of the present disclosure

[0003] The present disclosure relates generally to computer memory, and more particularly to pre-charging bit lines of static random access memory (SRAM) for memory access.

[0004] A memory cell is the basic building block of a computer data store, also known as a "memory". A computer system may write data of different types into a memory and read data from the memory. For example, one type of memory is static random access memory (SRAM). By way of example, an SRAM may be utilized as a cache memory in a central processing unit (CPU) system. The SRAM cache may be comprised of a tag array and a data array. The tag array includes indices for memory addresses stored in the SRAM data array. The tag array receives a memory address as part of a memory access request from the CPU. The tag array uses the memory address to determine if the SRAM data array contains valid data for the memory address in the memory access request. If valid data is present, the data may be accessed directly from the SRAM data array as opposed to being accessed from higher level memory, such as higher level cache memory or main memory.

[0005] SRAM data arrays are comprised of rows and columns of SRAM bit cells. SRAM bit cells may store a single information bit, respectively. The memory access request for the SRAM data array typically includes selecting the entire row of SRAM bit cells to access the bits stored in each column of the selected row. In this regard, FIG. 1 illustrates an example of a standard 6-T (six transistor) SRAM bit cell 10 as an SRAM cell that may be provided to an SRAM to store a single information bit 12. A single information bit 12 is stored in two (2) cross-coupled inverters 14, 16 in a 6-T SRAM bit cell 10. The 6-T SRAM bit cell 10 has two stable states that are used to represent a single information bit 12 (e.g., logic state "1" or "0"). Two additional access transistors 18, 20 are provided to control access to the SRAM bit cell 10 during read and write operations. An access to the 6-T SRAM bit cell 10 is enabled by the word line signal 22 asserted on the word line 24 controlling the two (2) access transistors 18,20 . The assertion of the word line signal 22 on the word line 24 activates two (2) access transistors 18,20 so that the bit line 26 and the bit line complement 28 are connected in two (2) Of the cross-coupled inverters 14, 16 of the inverter. Thus, bit line 26 and bit line supplement 28 are used to transfer data for both read and write operations.

As an example, in a read operation, the activation of the access transistors 18, 20 may be controlled by a single bit of information 12 being applied by two (2) cross-coupled inverters 14, Line 26 and the bit line complement 28. [ A single information bit 12 is placed on bit line 26 and bit line complement 28 in the form of voltage or current levels. The sense amplifier 30 detects a different voltage between the bit line 26 and the bit line complement 28, representing one of the two logical states as discussed above. In a write operation, the input driver 32 places voltage 34 and voltage compensation 36 on bit line 26 and bit line complement 28, respectively. Voltage 34 and voltage compensation 36 placed on bit line 26 and bit line complement 28 by input driver 32 respectively represent a single stored information bit 12. Activation of the access transistors 18,20 by the word line 24 is accomplished by applying a voltage 34 and a voltage complement 36 on the bit line 26 and the bit line complement 28 to the two cross- To be stored or latched in the coupled inverters 14,16.

The bit line 26 and bit line complement 28 of the 6-T SRAM bit cell 10 of FIG. 1 are of a known stable voltage level (i.e., a logic high "1 " Can be pre-charged by bit line pre-charge signal 38 and bit line pre-charge signal complement 40, respectively, Pre-charging bit line 26 and bit line complement 28 allows sense amplifier 30 to efficiently interpret different voltage levels as a bit state and SRAM bit cell 10 is coupled to SRAM bit cell 10 Allows to start at a known condition to prevent cell chaos. The pre-charging of the bit line 26 and the bit line complement 28 is deactivated at the assertion of the word line 24 so that an initial known voltage level is applied to the two 2 by the cross-coupled inverters 14, 16 or by the input driver 32. After the read or write operation to the 6-T SRAM bit cell 10 is completed for a memory access request, the bit line 26 and the bit line complement 28 are written to this known pre-charge voltage Level < / RTI > again.

[0008] As discussed above, for SRAM designs that utilize pre-charge of the bit lines of the SRAM bit cell column, the memory address of the memory access request may include a particular row or column of SRAM bit cells accessed for pre- Can be used for identification. The memory access request utilizes a memory access request circuit to convert the memory address of the memory access request into a particular row or column that is accessed for pre-charging. However, providing this additional circuitry may add latency to memory access requests. To prevent this additional latency, SRAM designs may include pre-charging all rows or columns of SRAM bit cells after a read or write operation is completed to prepare SRAM bit cells for the next memory access request. Thus, additional circuitry for converting the memory address of the memory access request to a particular row or column of SRAM bit cells is not necessary. However, maintaining bit line pre-charge can increase leakage power during memory idle times when SRAM bit cells are not being accessed.

Thus, SRAM designs, including precharging all rows or columns of SRAM bit cells, consume more power than SRAM designs that identify specific rows or columns of SRAM bit cells as part of a memory access request . However, SRAM designs, including precharging all rows or columns of SRAM bit cells, do not include additional latency from the circuitry used to identify the particular row or column being accessed as part of the memory access request for pre-charging .

[0010] Embodiments disclosed herein include methods and apparatus for pre-charging bit lines of a static random access memory (SRAM) prior to data access to reduce leakage power. Embodiments for pre-charging the SRAM prior to data access may reduce leakage power without affecting read or write performance. SRAM may be included in the SRAM cache as one non-limiting example. In this regard, a memory access logic circuit may be provided in the first data access path of the SRAM. The memory access logic circuit receives a memory access request including a data entry address to be accessed in the SRAM data array of the SRAM. The memory access logic circuit converts the data entry address into a data index for indexing the data entry address of the SRAM data array. The SRAM also includes a pre-charge circuit provided on a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of a memory access request to prevent pre-charging bit lines of the SRAM data array during idle periods to reduce leakage power. However, by also providing a pre-charge circuit in the second data access path outside the first data access path, the pre-charge circuit can enable pre-charge of the SRAM data array prior to data access, Does not add a latency to the first data access path.

[0011] In order to further reduce leakage power, when the SRAM data array is comprised of, for example, sub-arrays, the pre-charge circuitry includes a specific data sub-array of SRAM data arrays containing data entry addresses And may also be configured to enable its pre-charge. In this manner, the data sub-arrays of the SRAM data array that do not include the data entry address do not pre-charge un-accessed data sub-arrays, thereby preventing additional leakage power. It is not enabled.

[0012] In this regard, in one embodiment, an SRAM is provided. The SRAM includes a memory access logic circuit provided in a first data access path. The memory access logic circuit is configured to receive the data entry address of the memory access request to address the data entry of the SRAM data array in the first data access path. The memory access logic circuitry further comprises means for indexing the SRAM data array to access a data entry of the SRAM data array corresponding to the received data entry address based on the received data entry address in the first data access path Index. The SRAM further includes a pre-charge circuit provided in a second data access path separate from the first data access path. Prior to accessing the data entry of the SRAM data array, the pre-charge circuit is configured to receive the data entry address in the second data access path. Charge circuit for at least a portion of the SRAM data array based on the received data entry address in the second data access path to pre-charge at least a portion of the SRAM data array means. Charge enable. ≪ / RTI >

[0013] In another embodiment, an SRAM is provided. The SRAM includes memory access logic circuit means provided in the first data access path means. The memory access logic circuit means is configured to receive the data entry address means for the memory access request means for addressing the data entry means of the SRAM data array means in the first data access path means. The memory access logic circuit means may further comprise means for storing the received data entry address in the first data access path means to index the SRAM data array means for accessing data entry means of the SRAM data array means corresponding to the data entry address means, Means for generating data index means based on the means. The SRAM further comprises pre-charge circuit means provided in a second data access path means separate from the first data access path means. Before the data entry means of the SRAM data array means is accessed, the pre-charge circuit means is configured to receive the data entry address means in the second data access path means. The pre-charge circuit means further comprises means for pre-charging at least a portion of the SRAM data array means in at least a portion of the SRAM data array means based on the received data entry address means in the second data access path means And to generate pre-charge enable means for the pre-charge.

[0014] In another embodiment, a method is provided for pre-charging an SRAM data array prior to accessing the SRAM data array. The method includes receiving a data entry address in a first data access path for a memory access request to address a data entry of the SRAM data array. The method further comprises generating a data index based on a data entry address received in the first data access path to index the SRAM data array for accessing a data entry of an SRAM data array corresponding to the data entry address . The method further comprises receiving a data entry address in a second data access path to pre-charge at least a portion of the SRAM data array. The method further includes generating a pre-charge enable for at least a portion of the SRAM data array based on a data entry address received in the second data access path to pre-charge at least a portion of the SRAM data array . The pre-charge enable is generated prior to accessing the data entry of the SRAM data array of the first data access path in the data index indicating the data entry address.

[0015] FIG. 1 is a schematic diagram of an exemplary six-transistor static random access memory (SRAM) memory cell for storing a single information bit.
[0016] FIG. 2 is a block diagram of a memory access logic circuit for indexing data entries in an SRAM data array for a memory access request and data in the SRAM data array for memory access requests to prevent or reduce latency in processing memory access requests Charge circuit for precharging the bit lines of the SRAM data array prior to accessing the entry.
[0017] FIG. 3 is a flow diagram illustrating an exemplary process for pre-charging bit lines of an SRAM data array of the SRAM of FIG. 2 prior to accessing data entries of the SRAM data array for a memory access request.
[0018] FIG. 4 is a timing diagram illustrating exemplary timings of signals involved in pre-charging bit lines of the SRAM data array of the SRAM of FIG. 2 prior to accessing the data entries of the SRAM data array for a memory access request .
[0019] FIG. 5 is a block diagram of a pre-charge circuit for precharging bit lines of an SRAM data array prior to accessing a data entry of the SRAM data array for a memory access request to reduce or prevent latency in processing a memory access request; Charge circuit and a memory array of a memory access logic circuit for indexing data entries in an SRAM data array for memory access requests.
[0020] FIG. 6 is a flow chart illustrating an exemplary process for pre-charging bit lines of the SRAM data array of the SRAM cache of FIG. 5, prior to accessing the data entry of the SRAM data array for a memory access request.
[0021] FIG. 7 illustrates an exemplary timing of the signals involved in pre-charging the bit lines of the SRAM data array of the SRAM cache of FIG. 5 before accessing the data entries of the SRAM data array for sequential memory access requests Fig.
[0022] FIG. 8 illustrates an example of the signals involved in pre-charging the bit lines of the SRAM data array of the SRAM cache of FIG. 5 before accessing the data entries of the SRAM data array for pipelined sequential memory access requests Fig.
[0023] FIG. 9 is a flow diagram illustrating the operation of SRAM data in the SRAM cache of FIG. 5 before accessing the data entries of the SRAM data array for pipelined sequential memory access requests including memory access requests for multiple banks of the SRAM cache. Lt; / RTI > is a timing diagram illustrating exemplary timing of signals involved in pre-charging the bit lines of the array.
[0024] FIG. 10 shows the bit lines of the SRAM data array of the SRAM cache of FIG. 5 prior to accessing the data entries of the SRAM data array to control word line assertion and pre- / RTI > is a timing diagram illustrating exemplary timing of signals involved in charging.
[0025] FIG. 11 is a schematic diagram of a bit line of the SRAM data array of the SRAM cache of FIG. 5, prior to accessing data entries of the SRAM data array to control word line assertion and pre-charge based on a selective self- Lt; / RTI > is an example timing diagram illustrating exemplary timing of the signals involved in pre-charging.
[0026] FIG. 12 illustrates a block diagram of an embodiment of the present invention, prior to accessing the data entries of the SRAM data array to control word line assertion and pre-charge based on a self- Lt; / RTI > is an example timing diagram illustrating exemplary timing of signals involved in precharging bit lines of an SRAM data array of an SRAM cache of FIG.
[0027] FIG. 13 is a block diagram of an example processor-based system including the SRAM of FIG. 2 and the generalized memory access logic circuit and pre-charge circuit of the SRAM cache of FIG.

[0028] The embodiments disclosed herein relate to methods and apparatus for pre-charging bit lines of a static random access memory (SRAM) prior to data access to reduce leakage power. Embodiments for pre-charging the SRAM prior to data access may reduce leakage power without affecting read or write performance. SRAM may be included in the SRAM cache as one non-limiting example. In this regard, a memory access logic circuit is provided in the first data access path of the SRAM. The memory access logic circuit receives a memory access request including a data entry address to be accessed in the SRAM data array of the SRAM. The memory access logic circuit converts the data entry address into an index for indexing the data entry address in the SRAM data array. The SRAM also includes a pre-charge circuit provided on a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of a memory access request to prevent pre-charging bit lines of the SRAM data array during idle periods to reduce leakage power. However, by also providing pre-charge circuitry in the second data access path outside the first data access path, the pre-charge circuitry can enable pre-charge of the SRAM data array prior to data access, Does not add a latency to the first data access path.

[0029] In order to further reduce leakage power, when the SRAM data array is comprised of, for example, sub-arrays, the pre-charge circuit also includes a data sub-array of SRAM data arrays And to enable its pre-charge. In this manner, the data sub-arrays of the SRAM data array that do not include the data entry address are pre-charged during the memory access request to prevent additional leakage power by not pre- Lt; / RTI >

2 is a schematic diagram of an exemplary SRAM 42 for indexing the data entry 44 of the SRAM data array 46 for a memory access request 48. [ The SRAM data array 46 is pre-charged prior to accessing the data entry 44 of the SRAM data array 46 for the memory access request 48, as discussed below. The SRAM data array 46 in this example is comprised of rows and columns of the 6-T SRAM bit cell 10 provided in FIG. The SRAM bit cell 10 of FIG. 1 will be referenced in FIG. 2 and will not be described again. The SRAM data array 46 may further comprise a plurality of SRAM data sub-arrays 50 (0) -50 (N).

2, the SRAM 42 includes two (2) data access paths (a first data access path 52 and a second data access path 54) as a non-limiting example, ). The first data access path 52 processes the memory access request 48 to generate an index for the SRAM data array 46 to access the data entry 44 corresponding to the memory access request 48. In this non-limiting example, the second data access path 54 includes a memory access request 48 (N) to identify only a particular one of the plurality of SRAM data sub-arrays 50 (0) -50 To request only the specific SRAM data sub-arrays 50 (0) -50 (N) to be accessed to pre-charge, thereby reducing the leakage power. In this example, the pre-charge of the particular SRAM data sub-arrays 50 (0) -50 (N) A second data access path 54 outside the first data access path 52 prior to accessing the data entry 44 of the first data access path 52 is provided as part of the data access path 52, ). In addition, SRAM 42 may pre-charge specific data entries 44 of SRAM data array 46 to be accessed so that non-accessed SRAM data sub-arrays 50 (0) -50 (N) Or the data entries 44, thereby reducing the leakage power in the SRAM 42 as well. The first data access path 52 of the SRAM 42 of FIG. 2 will now be described.

[0032] Referring to FIG. 2, a memory access logic circuit 56 is provided on a first data access path 52 and is configured to process the received memory access request 48. The processing of the memory access request 48 includes receiving the memory access request 48 and writing the data entry 48 of the memory access request 48 into the data index 60 for indexing the data entry 44 of the SRAM data array 46. [ Address < RTI ID = 0.0 > 58 < / RTI > The data index 60 is generated by translating the data entry address 58 of the memory access request 48 into an index corresponding to the location of the data entry 44 of the SRAM data array 46. In this example, data index 60 includes data entries 44 (N) of SRAM data sub-arrays 50 (0) -50 (N) of SRAM data array 46 containing data of data entry address 58 Quot;) < / RTI > Accessing the data entry 44 asserts the array enable 62 for the SRAM data array 46 to initiate an access event in the SRAM data array 46 based on the memory access request 48. [ . The SRAM data array 46 additionally receives the array enable 62 as an input. The array enable 62 indicates that there is a corresponding data index 60 output on the data index 60. In addition, the assertion of the array enable 62 initiates the access of the data entry 44 in the first data access path 52. Based on the asserted array enable 62, the SRAM data array 46 outputs the addressed data entry 44 as a data out 64 from the SRAM data array 46. Pre-charging is provided by identifying the SRAM data sub-arrays 50 (0) -50 (N) in the second data access path 54 based on the memory access request 48. Additionally, the pre-charge is not provided in the first data access path 52, as discussed below.

2, the second data access path 54 of the SRAM 42 includes a first data access path 52 and a second data access path 54 before accessing the data entry 44 in the first data access path 52. [0033] Arrays 50 (0) -50 (N) to be pre-charged outside the data access path 52. The SRAM data sub-arrays 50 (0) - 50 The pre-charge is provided to a second data access path 54 outside the first data access path 52 and thus the latency due to pre-charge is determined by accessing the data entry 44 of the SRAM data array 46 Is not provided as part of the first data access path 52 that is used for the < / RTI > The second data access path 54 will now be described.

[0034] Referring to FIG. 2, the second data access path 54 includes a pre-charge circuit 66. The pre-charge circuit 66 is configured to pre-charge the SRAM data array 46 on one or more of the plurality of SRAM data sub-arrays 50 (0) -50 (N) in the second data access path 54. [ Respectively. The pre-charge circuit 66 is also configured to receive a memory access request 48 of the second data access path 54. The pre-charge circuit 66 further includes a pre-charge index 68 for indexing the accessed SRAM data sub-arrays 50 (0) -50 (N), corresponding to the memory access request 48. [ . The pre-charge circuit 66 converts the received memory access request 48 into a pre-charge index 68 corresponding to the SRAM data sub-arrays 50 (0) -50 (N) Thereby generating an index 68. Fig. The pre-charge index 68 indicates which of the SRAM data sub-arrays 50 (0) -50 (N) is required to pre-charge. The pre-charge circuit 66 further includes a pre-charge circuit 66 that enables pre-charge of the SRAM data sub-arrays 50 (0) -50 (N) by the SRAM data array 46 in this example. (70).

2, the pre-charge enable 70 indicates to the SRAM data array 46 that the pre-charge index 68 has been provided to the SRAM data array 46. [0035] FIG. The generated pre-charge index 68 and pre-charge enable 70 are stored in the SRAM data array 54 in the second data access path 54 prior to accessing the data entry 44 in the first data access path 52. [ (46). The SRAM data array 46 is coupled to the pre-charge index 68 following the receipt of the pre-charge enable 70 without waiting for the processing of the memory access request 48 to complete in the first data access path 52 Charge of the SRAM data sub-arrays 50 (0) -50 (N) indicated by the data. As a non-limiting example, enabling pre-charging of SRAM data sub-arrays 50 (0) -50 (N) may be accomplished using SRAM data sub-arrays Only the bit line 26 and the bit line complement 28 shown in Figure 1 of Figure 5 (50 (0) -50 (N)). This is because the memory access request 48 is provided in the second data access path 54 and the pre-charge circuit 66 is enabled to write the specific SRAM data sub-arrays 50 (0) -50 N), as shown in FIG. Bit lines 26 and bit line complement 28 of SRAM data sub-arrays 50 (0) -50 (N) that are not accessed may be placed in a floating state or may remain in a floating state . The floating state indicates that the bit lines 26 and bit line complement 28 of the SRAM data sub-arrays 50 (0) -50 (N) that have not been accessed are in either a logic high or a logic low state Maintained or pre-charged.

2, bit lines 26 and bit line complement 28 of un-accessed SRAM data sub-arrays 50 (0) -50 (N) are logic high or logic Leakage may occur during memory idle periods pre-charged to a low state. The pre-charge circuit 66 is part of the memory access request 48 to prevent pre-charging of the bit lines 26, 28 of the SRAM data array 46 during idle periods to reduce leakage power And to enable pre-charging of the SRAM data array 42. However, by also providing the pre-charge circuit 66 to the second data access path 54 outside of the first data access path 52, the pre-charge circuit 66 can be configured such that the pre- May pre-charge the SRAM data array 42 prior to data access so as not to add latency to the data access path 52.

[0037] To further pre-charge the bit lines 26, 28 of the SRAM data array 46 and to access the memory access request 48 prior to accessing the data entry 44, do. FIG. 3 is a flow chart illustrating an exemplary process for processing a memory access request 48 of SRAM 42 of FIG. As discussed above, the processing of the memory access request 48 includes two (2) data access paths (a first data access path 52 and a second data access path 54). The processing of the memory access request 48 to access the data entry 44 of the SRAM data array 46 at the data entry address 58 of the memory access request 48 is performed by the data entry 44 of the SRAM data array 46 (Block 72) in a first data access path 52 for addressing the memory access request 48. The memory access request 48 is then sent to the first data access path 52 (block 72). The memory access logic circuit 56 of Figure 2 generates a data index 60 and an array enable 62 based on the memory access request 48 received at the first data access path 52 (block 74) . The memory access logic circuit 56 generates the data index 60 and the array enable 62 by converting the memory access request 48 that includes the data entry address 58. [ The data index 60 and the array enable 62 generated by the memory access logic circuit 56 are output to the SRAM data array 46. [ The SRAM data array 46 includes a received data index 60 and a plurality of arrays 46 for accessing the data entry 44 of the SRAM data array 46 corresponding to the memory access request 48 in the first data access path 52. [ An enable 62 is used (block 76).

3, the processing of the memory access request 48 of FIG. 2 further includes processing the bit lines 26, 28 of the SRAM data sub-arrays 50 (0) -50 (N) (48) in a second data access path (54) to pre-charge (block 78 of FIG. 3). The pre-charge circuit 66 includes a pre-charge index 68 and pre-charge enable 70 for the SRAM data sub-arrays 50 (0) -50 (N) corresponding to the memory access request 48 (Block 80 of FIG. 3). The generated pre-charge index 68 and pre-charge enable 70 are output by the pre-charge circuit 66 and received by the SRAM data array 46. The SRAM data array 46 includes a received pre-charge index 68 and a pre-charge index to pre-charge the SRAM data sub-arrays 50 (0) -50 (N) An enable 70 is used (block 82 of FIG. 3). The SRAM data array 46 of Figure 2 thus waits for the memory access logic circuit 56 to complete the translation of the memory access request 48 and the access of the data entry 44 in the first data access path 52 Can pre-charge the SRAM data sub-arrays 50 (0) -50 (N). In this manner, the SRAM data sub-arrays 50 (0) -50 (N) comprising the data entry 44 corresponding to the memory access request 48 enable the SRAM data array 46 to access memory access requests 48 Pre-charged before accessing the data entry 44 corresponding to the data entry 44. [

Referring to FIG. 2, pre-charging the SRAM data array 46 is enabled in the second data access path 54 outside the first data access path 52. Pre-occupying the bit lines 26, 28 of the SRAM data sub-arrays 50 (0) -50 (N) including the data entry 44 to be accessed in this manner is accomplished by a first data access path 52 do not rely on data entry 44 access enabled. The pre-charge circuitry 66 is configured to use at least a portion of the data entry address 58 of the memory access request 48 sufficient to identify the SRAM data sub-arrays 50 (0) -50 (N) It is possible to enable pre-charging of SRAM data sub-arrays 50 (0) -50 (N) including data entries 44 to be accessed prior to accessing data entry 44, if possible. In this regard, the pre-charge circuit 66 is coupled to the data entry address 58 of the memory access request 48 sufficient to identify the SRAM data sub-arrays 50 (0) -50 (N) And is configured in the second data access path 54 to receive at least a portion thereof. The pre-charge circuit 66 is operable to receive the received data entry address (s) to identify the SRAM data sub-arrays 50 (0) -50 (N) of the SRAM data array 46 containing the data entry 44 to be accessed 58) or a portion thereof. Thus, the pre-charge circuit 66 pre-charges the data prior to accessing the data entry 44 of the SRAM data sub-arrays 50 (0) -50 (N) and independently of the first data access path 52 May enable pre-charging of the SRAM data sub-arrays 50 (0) -50 (N) determined to include the entry 44.

To reduce or prevent leakage power during memory idle times, all bit lines 26 and bit line complement 28 of FIG. 1 will not be pre-charged. Thus, as a non-limiting example, in contrast to all bit lines 26 of SRAM data sub-arrays 50 (0) -50 (N), SRAM data Only bit line 26 and bit line complement 28 of sub-arrays 50 (0) -50 (N) may be pre-charged. Bit lines 26 and bit line complement 28 of SRAM data sub-arrays 50 (0) -50 (N) that are not accessed as part of the memory access request 48 additionally provide leakage power It can be left floating in order to prevent it. In this manner, the latency of the pre-charge circuit 66 is not provided as part of the first data access path 52 for accessing the data entry 44 of the SRAM data sub-array 50. Additionally, the SRAM 42 may pre-charge the data entry 44 of the accessed SRAM data sub-array 50, while also reducing the leakage power in the SRAM 42.

[0041] In this regard, FIG. 4 illustrates a timing diagram 84 of exemplary signals associated with two (2) events (pre-charge event 86 and access event 88). Figure 4 shows a pre-charge event 86 for pre-charging the bit lines 26, 28 of the SRAM data array 46 in the second data access path 54 to the first data access path 52, Lt; RTI ID = 0.0 > 88 < / RTI > The pre-charge event 86 for pre-charging the SRAM data sub-arrays 50 (0) -50 (N) causes the pre-charge circuit 66 to precharge the memory accesses As a result of processing the request 48. The access event 88 for accessing the data entry 44 occurs as a result of the memory access logic circuit 56 processing the memory access request 48 of the first data access path 52. Exemplary signals of the events of two (2) will now be described.

[0042] Continuing to refer to FIG. 4, SRAM 42 is a synchronous circuit; The clock signal 90 is thus provided to the SRAM 42 to control the clocking of the circuits that control the memory access request 48. As discussed above, the pre-charge circuit 66 generates a pre-charge enable 70 as shown in FIG. The pre-charge enable 70, which indicates that the pre-charge index 68 has been provided by the pre-charge circuit 66 to the SRAM data array 46, And is asserted by the pre-charge circuit 66 following generation of the charge index 68. [ The assertion of the bit line pre-charge signal 38 by the SRAM data array 46 is followed by the assertion of the pre-charge enable 70 by the pre-charge circuit 66 followed by the rising edge of the clock signal 90 Transition (hereinafter referred to as "rising edge"). As illustrated in FIG. 4, the array enable 62 is not generated by the memory access logic circuit 56 based on the pre-charge enable 70. Rather, the array enable 62 is asserted by the memory access logic circuit 56 based on the generation of the data index 60 by the memory access logic circuitry 56 of FIG. The array enable 62 indicating that the data index 60 has been provided to the SRAM data array 46 by the memory access logic circuit 56 follows the creation of the data index 60 by the memory access logic circuit 56. [ Is asserted by the memory access logic circuit 56. The assertion of the word line signal 22 by the SRAM data array 46 is followed by the assertion of the array enable 62 by the memory access logic circuit 56 as a non-limiting example, It is based on the rising edge. The assertion of the word line signal 22 by the SRAM data array 46 may also be based on a falling edge or transition of the clock signal 90 (hereinafter referred to as "falling edge"). The pre-charge enable 70 is also enabled by the SRAM data array 46 based on the rising edge of the clock signal 90 following the assertion of the array enable 62 by the memory access logic circuit 56 - It is de-asserted. The additional latency of the pre-charge circuitry 66 is controlled by accessing the data entry 44 of the SRAM data sub-array 50 by precharging the SRAM data sub-array 50 in the second data access path 54 As part of the latency of the first data access path 52 for < / RTI > However, it should be noted that the SRAM 42 should be designed such that the array enable 62 is not consumed prior to the end of the pre-charge enable 70 pre-charging the SRAM data sub-array 50. Otherwise, the accessed SRAM data sub-array 50 may not be pre-charged upon access.

[0043] A CPU cache is a cache memory used by a CPU system of a computer to reduce the average time required to access the memory. The CPU cache is a smaller, faster memory that stores copies of data from frequently used main memory locations. The more memory accesses that use cached memory locations, the closer the average memory accesses of memory accesses will be to the cache latency than to the main memory latency. Cache latency can therefore be a significant factor in the performance of the CPU's memory. SRAM 42 is one type of memory that can be used in a computer system as a cache memory. Pre-charging in a previous clock cycle before all memory access signals are ready reduces the latency of the SRAM 42 and thereby accelerates the performance of the SRAM 42 as described above.

In this regard, FIG. 5 is a schematic diagram of an exemplary SRAM cache 42 'for indexing the data entry 44 of the SRAM data array 46 for a memory access request 48. The SRAM data array 46 is pre-charged prior to accessing the data entry 44 of the SRAM data array 46 for the memory access request 48, as will be described below. The SRAM data array 46 consists of the rows and columns of the 6-T SRAM bit cell 10 provided in this example in FIG. For clarity, the elements of Figure 1, which are referred to in describing Figure 5, will not be described again. The SRAM data array 46 may be further configured with a plurality of SRAM data sub-arrays 50 (0) -50 (N).

Still referring to FIG. 5, the SRAM cache 42 'includes two (2) data access paths (a first data access path 52' and a second data access path 54 ') in this example, ). The first data access path 52'provides processing of the memory access request 48 to index the SRAM data array 46 for access to the data entry 44 corresponding to the memory access request 48. [ The second data access path 54 'is a non-limiting example in which only the specific SRAM data sub-arrays 50 (0) -50 (N) to be accessed are required to require pre-charge to reduce leakage power Is provided to identify a particular one or more of a plurality of SRAM data sub-arrays 50 (0) -50 (N) to be accessed. In this example, pre-charging of the SRAM data sub-arrays 50 (0) -50 (N) is performed prior to accessing the data entry 44 in the first data access path 52 ' Occurs in a second data access path 54 'outside of the second data access path 52'. The first data access path 52 'of the SRAM cache 42' of FIG. 5 will now be described.

[0046] Referring to FIG. 5, the SRAM cache 42 'further comprises a memory access logic circuit 56' configured to process the received memory access request 48. The memory access logic circuit 56 'is configured to process the memory access request 48 of the first data access path 52'. The processing of the memory access request 48 includes receiving a data access request 48 from the data index 44 for indexing the data entry 44 that is located in the SRAM data array 46 corresponding to the memory access request 48, 60 into a data entry address (58). The data index 60 is generated by translating the data entry address 58 of the memory access request 48 into an index corresponding to the location of the data entry 44 of the SRAM data array 46.

[0047] In this example of the SRAM cache 42 ', the memory access logic circuit 56' is comprised of a tag array 92 and a comparator circuit 94. The tag array 92 receives a memory access request 48 as input. The tag array 92 utilizes a memory access request 48 provided to validate the data entry 44 stored in the SRAM data array 46 that represents the data entry address 58 of the memory access request 48. A valid data entry 44 is a coherent representation of the data of the data entry address 58 with the data stored in the memory. If the data entry 44 is valid, the tag array 92 provides the tag output 96 to the comparator circuit 94 as valid output. The comparator circuit 94 receives the memory access request 48 as the first input 97 and the tag output 96 as the second input 98. The comparator circuit 94 makes a comparison between the memory access request 48 and the tag output 96 and generates the data index 60 provided as an output to the SRAM data array 46.

[0048] With continued reference to FIG. 5, the SRAM data array 46 receives the data index 60 generated as an input. In this example, the data index 60 indicates which data entry 44 of the SRAM data sub-arrays 50 (0) -50 (N) of the SRAM data array 46 is the data of the data entry address 58 Or < / RTI > Accessing the data entry 44 includes providing the array enable 62 to the SRAM data array 46 used to initiate the memory access of the SRAM data array 46 based on the memory access request 48 do. The SRAM data array 46 additionally receives the array enable 62 as an input. The array enable 62 indicates that there is a corresponding data index 60 output by the memory access logic circuit 56 'and thus access of the data entry 44 can proceed. The data index 60 and the array enable 62 are output to the SRAM data array 46 for use in accessing the data entry 44 of the SRAM data array 46 in the first data access path 52 ' . When the array enable 62 is asserted, the SRAM data array 46 outputs the addressed data entry 44 as the data output 64 from the SRAM data array 46. For clarity, the elements of FIG. 1, which are referred to to describe FIG. 5, will not be described again.

[0049] Still referring to FIG. 5, the second data access path 54 'includes a pre-charge circuit 66. The pre-charge circuit 66 is configured to enable pre-charging of the SRAM data array 46 or the SRAM data sub-arrays 50 (0) -50 (N) in the second data access path 54 ' . The pre-charge circuit 66 is configured to receive a memory access request 48. The pre-charge circuit 66 further includes a pre-charge index 68 for indexing the accessed SRAM data sub-arrays 50 (0) -50 (N), corresponding to the memory access request 48 Respectively. The pre-charge circuit 66 is coupled to a memory 68 that is received in the pre-charge index 68 corresponding to the SRAM data sub-arrays 50 (0) -50 (N) to be accessed in the first data access path 52 ' And generates a pre-charge index 68 by transforming the access request 48. [ The pre-charge index 68 indicates which of the SRAM data sub-arrays 50 (0) -50 (N) requires pre-charge and the pre-charge index 68 indicates all index bits You do not have to. Thus, only a portion of the index bits are needed in the previous clock cycle prior to memory accesses. The pre-charge circuit 66 further includes a pre-charge circuit 66 that enables pre-charge of the SRAM data sub-arrays 50 (0) -50 (N) by the SRAM data array 46 in this example Able 70. < / RTI >

5, the pre-charge enable 70 indicates to the SRAM data array 46 that the pre-charge index 68 has been provided to the SRAM data array 46. [ The generated pre-charge index 68 and pre-charge enable 70 are stored in the second data access path 54 'prior to accessing the data entry 44 in the first data access path 52' And is received by the data array 46. The SRAM data array 46 is operative to receive the pre-charge enable 70 independently of the processing of the memory access request 48 in the first data access path 52 ' It is possible to proceed with pre-charging of the indicated SRAM data sub-arrays 50 (0) -50 (N). Additionally, the generated pre-charge index 68 may include, for example, only a portion of all the index bits for proceeding pre-charging of the SRAM data sub-arrays 50 (0) -50 (N) . ≪ / RTI > As a non-limiting example, the pre-charging of the SRAM data sub-arrays 50 (0) -50 (N) may be performed using SRAM data sub-arrays 50 (0) 50 < / RTI > (N) of the bit lines 26 and bit line complement 28 of FIG. The bit lines 26 and bit line complement 28 of the SRAM data sub-arrays 50 (0) -50 (N) that are not accessed may be placed in a floating state or may remain in a floating state, Thereby reducing leakage power.

5, the leakage power is determined by the bit lines 26 and bit line complement 28 of the SRAM data sub-arrays 50 (0) -50 (N) Or memory-idle periods pre-charged to either of the two states. The data entry 44 accessed by the memory access request 48 may be used to reduce the leakage power experienced by the precharge of the bit lines 26 and bit line complement 28 of the SRAM data array 46. [ Only the bit lines 26 and bit line complement 28 of the SRAM data sub-array 50 including the bit line complement 28 are pre-charged. Bit lines 26 and bit line complement 28 of SRAM data sub-arrays 50 (0) -50 (N) that are not accessed may be left floating to reduce leakage power. Also, enabling pre-charging of the SRAM data sub-arrays 50 (0) -50 (N) in the second data access path 54 'is advantageous because the memory access logic circuit 56' May occur while processing the memory access request 48 in the access path 52 '. The data entry 44 of the accessed SRAM data array 46 is pre-charged prior to being accessed based on the pre-charge index 68 received in the second data access path 54 '. In this manner, the pre-charge circuit 66 is enabled to receive a memory access request 48 (i. E., To avoid pre-charging the bit lines 26,28 of the SRAM data array 46 during idle periods to reduce leakage power) Charge of the bit lines 26, 28 of the SRAM data array 42 'as part of the SRAM data array 42'. However, by also providing the pre-charge circuit 66 to the second data access path 54 'outside of the first data access path 52', the pre-charge circuit 66 can pre-charge the SRAM data array Charging of the first data access path 52 'so that the pre-charge circuit 66 does not add latency to the first data access path 52'. As will be discussed in greater detail below, an optional self-timing clock circuit 100 is provided in the SRAM data array 46. The optional self-timing clock circuit 100 provides an alternative means for asserting or de-asserting both the word line signal 22 and / or the bit line pre-charge signal 38.

[0052] To further illustrate pre-charging of SRAM data array 46 prior to memory access request 48 and data entry 44 access, FIG. 6 is provided. 6 is a flow chart illustrating an exemplary process for processing a memory access request 48 in the SRAM cache 42 'of FIG. The processing of the memory access request 48 includes two (2) data access paths (a first data access path 52 'and a second data access path 54'). The processing of the memory access request 48 for accessing the data entry 44 of the SRAM data array 46 is performed by the first data access path 52 'to address the data entry 44 of the SRAM data array 46. [ (Block 102). ≪ / RTI > The memory access logic circuit 56 'generates a tag output 96 based on the memory access request 48 received at the first data access path 52' (block 104). The comparator circuit 94 compares the received memory access request 48 with the tag output 96 to determine if the data entry 44 is stored in the SRAM data array 46 (block 106). The memory access logic circuit 56 'generates the data index 60 and the array enable 62 based on the result of the comparison from the comparator circuit 94 and the tag output 96. The data index 60 and the array enable 62 generated by the memory access logic circuit 56 'are output to the SRAM data array 46. [ The SRAM data array 46 includes a received data index 60 and a received data index 44 to access the data entry 44 of the SRAM data array 46 corresponding to the memory access request 48 in the first data access path 52 ' Array enable 62 is used (block 108).

6, the processing of the memory access request 48 may further include processing the second data to pre-charge one or more of the SRAM data sub-arrays 50 (0) -50 (N). [0053] And receiving a memory access request 48 on the access path 54 '. The memory access request 48 is transferred by the pre-charge circuitry 66 to the SRAM data array 48 by pre-charge circuitry 66 to pre-charge the SRAM data sub-arrays 50 (0) -50 (N) (Block 110) in a second data access path 54 'to pre-charge the bit lines 26, 28 of the memory cell array 46. The pre-charge circuit 66 includes a pre-charge index 68 and pre-charge enable 70 for the SRAM data sub-arrays 50 (0) -50 (N) corresponding to the memory access request 48 (Block 112). The generated pre-charge index 68 and pre-charge enable 70 are output by the pre-charge circuit 66 and received by the SRAM data array 46. The SRAM data array 46 includes a received pre-charge index 68 and a pre-charge index to pre-charge the SRAM data sub-arrays 50 (0) -50 (N) Enable 70 is used (block 114). Thus, the SRAM data array 46 is independent of the memory access logic circuit 56 'generating the translation of the memory access request 48 in the first data access path 52', and the SRAM data sub-array 50 (0) -50 (N)). In this manner, the SRAM data sub-arrays 50 (0) -50 (N) comprising the data entry 44 corresponding to the memory access request 48 enable the SRAM data array 46 to access memory access requests 48 May be pre-charged prior to accessing the data entry 44 corresponding to the data entry 44. < RTI ID = 0.0 >

[0054] Still referring to FIG. 6, pre-charge may be performed on the second data access path 54 'outside the first data access path 52' so that the pre-charge function is independent of the data entry 44 access Occurs. By providing the pre-charge circuit 66 in the second data access path 54 'outside the first data access path 52', the pre-charge circuit 66 is enabled in the first data access path 52 ' Can pre-charge the SRAM data sub-arrays 50 (0) -50 (N) independently of the data entry 44 access of the SRAM data sub-arrays. Thus, the pre-charge circuit 66 precharges the SRAM data sub-array (not shown) prior to accessing the data entry 44 in the SRAM data sub-arrays 50 (0) -50 (N) of the data entry address 58 50 (0) -50 (N)). To reduce or prevent leakage power during memory idle times, not all bit lines 26 will be pre-charged. Thus, as a non-limiting example, in contrast to all bit lines 26 and bit line complement 28 of SRAM data array 46, SRAM data sub-arrays < RTI ID = 0.0 > Only the bit line 26 and bit line complement 28 of FIG. 1 of the word line 50 (0) -50 (N) may be pre-charged. The bit lines 26 and bit line complement 28 of SRAM data sub-arrays 50 (0) -50 (N) that are not accessed as part of the memory access request 48 additionally provide leakage power It can be left floating in order to reduce it. In this manner, the latency of the pre-charge circuit 66 is limited by the first data access path 52 'to access the data entry 44 of the SRAM data sub-arrays 50 (0) -50 (N) Lt; / RTI > The SRAM cache 42'can pre-charge the data entries 44 of the particular SRAM data sub-arrays 50 (0) -50 (N) being accessed thereby reducing the leakage power in the SRAM cache 42 ' .

[0055] In this regard, the data entry 44 (N) of the SRAM data sub-arrays 50 (0) -50 (N) corresponding to the received plurality of memory access requests 48 A timing diagram 116 for illustrating the timing of exemplary signals associated with accessing and pre-charging is provided in FIG. For clarity, the elements referenced in Figure 7 will be described in Figures 1 and 2 and will not be described again. Figure 7 illustrates a precharge event 86 for enabling pre-charging of bit lines 26 and 28 of SRAM data array 46 in a second data access path 54, RTI ID = 0.0 > 88 < / RTI > for accessing the SRAM data array 46 in the memory 52. Thus, the pre-charge enable 70 may be asserted separately and prior to the array enable 62 being asserted. The processing of memory access requests 48 (1) -48 (M) will remain the same individually and will not be described again.

[0056] Still referring to FIG. 7, the SRAM 42 may receive a plurality of memory access requests ((48) (1) -48 (M)). Figure 7 illustrates the timing of signals for processing of memory access requests (48 (1) -48 (M)) in the SRAM cache 42 '. The additional memory access request 48 processing is the same as the processing of the memory access request 48 as described above in FIG. The memory access request 48 (2) in FIG. 7 is processed on the next rising clock edge of the clock signal 90 following the timing signal describing the memory access request 48 (1).

[0057] Figure 7 illustrates that memory access requests (48) (1) -48 (M) are processed sequentially. To increase the performance of the SRAM 42, the SRAM 42 may also process a plurality of memory access requests (48) (1) -48 (M) in a pipelined manner. The processing of pipelined memory access requests (48) (1) -48 (M) allows overlapping execution of a plurality of memory access requests (48) (1) -48 (M) . In this regard, FIG. 8 shows a pre-charge event 86 for enabling pre-charge of the SRAM data array 46 and two (2) received memory access requests 48 Timing diagrams of exemplary signals associated with an access event 88 for accessing the data entry 44 of the SRAM data sub-arrays 50 (0) -50 (N) corresponding to the SRAM data sub-arrays 50 (1), 48 (118). However, Figure 8 additionally illustrates the processing of two (2) memory access requests 48 (1), 48 (2) in a pipelined manner. The individual signals illustrated in Fig. 8 are shown in Fig. 2 and will not be described again. The processing of each of the two (2) memory access requests 48 (1), 48 (2) will remain the same individually and will not be described again. It should be noted that more than two (2) memory access requests 48 (1), 48 (2) may be received and processed. In this manner, FIG. 8 shows that the SRAM cache 42 is able to access the SRAM data array 48 (2) for the memory access request 48 (2) while accessing the SRAM data array 46 corresponding to the memory access request 48 (46). ≪ / RTI >

[0058] Still referring to FIG. 8, the bit line pre-charge signal 38 is asserted by the SRAM data array 46 at a second time for a memory access request 48 (2). The bit line pre-charge signal 38 is applied to the rising edge of the clock signal 90 used by the SRAM data array 46 to assert the word line signal 22 for the memory access request 48 (1) Is asserted at the second time, based on the rising edge of the same clock signal (90) as the clock signal (90). As discussed above, the rising edge of the clock signal 90 used by the SRAM data array 46 to assert the word line signal 22 also causes the bit corresponding to the memory access request 48 (1) And de-asserts line pre-charge signal 38. The de-assertion of the bit line pre-charge signal 38 by the SRAM data array 46, corresponding to the memory access request 48 (1), indicates that the bit line pre- To prevent access of the SRAM data array 46 by the memory access request 48 (1), as described in the discussion above. However, in this example, the SRAM 42 is configured to receive the word line signal 22 from the SRAM data array 46 by re-asserting the bit line pre-charge signal 38 by the SRAM data array 46, - Use the next rising edge of the clock signal 90 following the assertion. In this manner, the SRAM 42 is enabled to re-assert the bit line pre-charge signal 38 by the SRAM data array 46 while the word line signal 22 is asserted by the SRAM data array 46. [ , Which may cause interference and erroneous results in the memory access request 48 (1). Thus, the SRAM 42 is able to access memory access requests 48 (1) and memory access requests 48 (1) in a shorter time period than would normally be possible with the sequential scheme illustrated in FIG. 7, 48 (2). ≪ / RTI > SRAM 42 may be comprised of a plurality of SRAM data sub-arrays 50 (0) -50 (N) (not shown in FIG. 8). Each of the two (2) memory access requests 48 (1), 48 (2) in FIG. 8 may address the same or different data entries 44. Each of the data entries 44 may also be located in the same or different ones of the plurality of SRAM data sub-arrays 50 (0) -50 (N).

In this regard, FIG. 9 shows eight (8) memories for addressing the data entries 44 of the plurality of SRAM data sub-arrays 50 (0) -50 (N) in a pipelined manner. Is a timing diagram 120 illustrating exemplary signals associated with processing access requests 48 (1) -48 (8). The signals illustrated in Figure 9 are shown in Figures 1 and 2 and will not be described again. Similar to Figure 8, the pre-charge event 86 for enabling pre-charging of the SRAM data array 46 in the second data access path 54 is transferred to the SRAM data array 52 in the first data access path 52, Lt; RTI ID = 0.0 > 88 < / RTI > The processing of each of the eight (8) memory access requests 48 (1) -48 (8) will remain the same individually and will not be described again. Figure 9 illustrates the processing of a plurality of memory access requests 48 (1) -48 (8) in a pipelined manner similar to Figure 8, but Figure 9 additionally illustrates processing of a plurality of SRAM data sub-arrays 50 (0) -50 (N). ≪ / RTI >

[0060] With continuing reference to FIG. 9, the pre-charge index 68 of FIG. 2 shows, as a non-limiting example, which of the plurality of SRAM data sub-arrays 50 (0) -50 (N) To be pre-charged on the next rising edge of the clock signal 90. The plurality of SRAM data sub-arrays 50 (0) -50 (N) are configured such that the pre-charge of the SRAM data sub-arrays 50 (0) -50 (N) Can also be pre-charged on the falling edge of signal 90. In this example, the memory access request 48 (1) includes pre-charge circuit 66 (1) to access the data entry 44 corresponding to the data entry address 58 of the memory access request 48 Not shown). In this non-limiting example, the pre-charge circuit 66 generates a pre-charge index 68 of three bits. The three-bit pre-charge index 68 allows one of the eight (8) SRAM data sub-arrays 50 (0) -50 (7) to be pre- . In this example, the memory access request 48 (1) includes a data entry address 58 that is located in the SRAM data sub-array 50 (7), so that the pre-charge index 68 And all bits are asserted by the pre-charge circuit 66. The pre-charge index 68 of the three bits asserted by all the bits generates a binary value of "111 " as the pre-charge index 68. Converting this binary value to a decimal value of "7" indicates that the SRAM data sub-array 50 (7) will be pre-charged by the SRAM data array 46. The pre-charge index 68 is provided, while the pre-charge enable 70 is asserted by the pre-charge circuit 66. The pre-charge enable 70 indicates to the SRAM data array 46 that the pre-charge index 68 has been output by the pre-charge circuit 66. As described above, based on the assertion of the pre-charge enable 70, the SRAM data array 46 is coupled to the SRAM data sub-array 50 (7) on the next rising clock edge of the clock signal 90 And asserts the bit line pre-charge signal 38 to activate pre-charge for the bit line. In this example, each rising edge of the clock signal 90 is coupled to a bit line pre-charge by the SRAM data array 46 in one of the plurality of SRAM data sub-arrays 50 (0) -50 (N) The assertion of the charge signal 38 can be initiated.

9, the assertion of the word line signal 22 by the SRAM data array 46 corresponding to the SRAM data sub-arrays 50 (0) -50 (M) - de-assert the charge signal 38 and activate access to the data entry 44 corresponding to the memory access request 48 (1) -48 (8). The word line signal 22 may be de-asserted by the SRAM data array 46 based on several clocking schemes. In this example, each rising edge of the clock signal 90 is also coupled to an assertion of the bit line pre-charge signal 38 corresponding to a different memory access request 48 for the different SRAM data sub- At the same time, an assertion of the word line signal 22 by the SRAM data array 46 at the other of the plurality of SRAM data sub-arrays 50 (0) -50 (N) may be initiated. The de-assertion of the word line signal 22 may be performed by the optional self-timing clock circuit 100 (not shown) in a plurality of clocking schemes or by the SRAM data array 46.

In this regard, FIG. 10 illustrates an access event (not shown) associated with the control of the word line signal 22 assertion by the SRAM data array 46 (so called phase-based clocking scheme) based on the rising edge of the clock signal 90 Lt; / RTI > is a timing diagram 122 illustrating an exemplary timing of the signals for signal 88 in Fig. In this example, only the word line signal 22 assertion by the SRAM data array 46 in the first data access path 52 of the single memory access request 48 is illustrated. The illustrated scheme for controlling the word line signal 22 assertion by the SRAM data array 46 of FIG. 10 may be used in each of the timing examples described above. In the phase-based clocking scheme, through the array enable 62 asserted by the memory access logic circuit 56, the SRAM data array 46 asserts the word line signal 22 and outputs the clock signal 90, Will pre-charge the bitline pre-charge signal 38 on the same rising clock edge of the bitline pre-charge signal 38. The bitline pre-charge signal 38 is de-asserted by the SRAM data array 46 so as not to interfere with the access of the data entry 44 by the SRAM data array 46 as described above. The access to the SRAM data array 46 will remain active until the de-assertion of the word line signal 22 by the SRAM data array 46. [ The de-assertion of the word line signal 22 by the SRAM data array 46 in a phase-based clocking manner occurs on the next falling edge of the clock signal 90 following the assertion of the word line signal 22. The bit line pre-charge signal 38 is de-asserted by the SRAM data array 46 when the word line signal 22 is asserted by the SRAM data array 46 and the bit line pre- The memory 38 may remain in a de-asserted state, otherwise called a floating state, until the next memory access request 48. [ The phase-based clocking scheme allows the falling edge of the clock signal 90 to instruct or control the SRAM data array 46 to de-assert the word line signal 22. [

In designs where the clock signal 90 is operating at a frequency faster than that specified for the operation of the SRAM 42, the SRAM data array 46 is independent of the falling edge of the clock signal 90, It is possible to control the line signal 22. In this regard, FIG. 11 illustrates exemplary timing of signals for an access event 88 associated with control of the word line signal 22 assertion by the SRAM data array 46 based on a selective self-timing control scheme Timing diagram 124. FIG. An exemplary technique for controlling the word line signal 22 assertion by the SRAM data array in FIG. 11 can be used in each of the timing examples described above. In an optional self-timing control scheme, the SRAM data array 46 de-asserts the word line signal 22 and generates a bit line pre-charge signal 38 based on pre- Timing clock circuit 100 (not shown) of Fig. 5 to re-assert the self-timing clock signal. The optional self-timing clock circuit 100 is activated by the SRAM data array 46 with the assertion of the word line signal 22 by the SRAM data array 46. The optional self-timing clock circuit 100 allows sufficient time to properly access the data entry 44 of the SRAM data array 46 prior to de-asserting the word line signal 22. [ The optional self-timing clock circuit 100 optionally includes a bit line pre-charge signal (not shown) by the SRAM data array 46 when a subsequent memory access request 48 requests access to the SRAM data array 46 38). The optional self-timing clock circuit 100 is configured to provide the clock signal 90 with a very fast frequency so that sufficient time is available to access the data entry 44 of the SRAM data array 46 corresponding to the memory access request 48. [ Can be provided.

[0064] Clock periods shorter than the total time required to access the data entry 44 of the SRAM data array 46 and re-assert the bit line pre-charge signal 38 by the SRAM data array 46 It may also be required to provide an associated clock signal 90 frequency. In this regard, FIG. 12 illustrates an example of an access event (FIG. 12) associated with the control of the word line signal 22 assertion by the SRAM data array 46 based on a selective self-timing, self-reset control scheme across multiple clock cycles 88). ≪ / RTI > The illustrated scheme for controlling the word line signal 22 assertion by the SRAM data array 46 of FIG. 12 can be used in each of the timing examples described above. In an optional self-timing, self-reset control scheme, the SRAM data array 46 de-asserts the word line signal 22 based on a pre-set or programmed value and generates a bit line pre-charge signal 38 Timing clock circuit 100 (not shown) of FIGURE 5 to selectively re-assert the clock signal < RTI ID = 0.0 > The optional self-timing self-reset control scheme is provided when the optional self-timing clock circuit 100 can not be reset as fast enough to allow a subsequent memory access request 48 of the SRAM data array 46 . This means that the access by the SRAM data array 46 occurs over a number of clock cycles and the time period sufficient to access the data entry 44 of the SRAM data array 46 corresponding to the memory access request 48 Lt; RTI ID = 0.0 > and / or < / RTI > Similar to the self-clocking scheme described above, there must be sufficient time to access the SRAM data array 46 from one access to the next and also to pre-charge the bit line 26 and bit line supplement 28 . However, the optional self-timing, self-reset clock scheme allows the SRAM data array 46 to de-assert the word line signal 22 and to generate a bit line pre-charge signal (" Timing clock circuit 100 itself upon reset-assertion of the self-timing clock circuitry 38 of FIG. The optional self-timing clock circuit 100 itself resets, in contrast to the optional self-timing clock circuit 100, which is reset by the SRAM data array 46.

[0065] Pre-charging the bit lines of the SRAM prior to data access to reduce leakage power in accordance with the embodiments disclosed herein and related systems and methods are provided in or integrated into any processor- . Examples include, without limitation, a set top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a mobile telephone, a cellular telephone, a computer, a portable computer, a desktop computer, a personal digital assistant , A computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disk (DVD) player, and a portable digital video player.

[0066] In this regard, FIG. 13 may utilize systems and methods that pre-occupy the SRAM data array prior to data entry access to reduce leakage power in the SRAM 42 and SRAM 42 'disclosed herein Lt; RTI ID = 0.0 > 128 < / RTI > In this example, the processor-based system 128 includes one or more CPUs 130, each of which includes one or more processors 132. The CPU (s) 130 have a cache memory 134 coupled to the processor (s) 132 for quick access to the temporarily stored data. The CPU (s) 130 may couple the master and slave devices coupled to the system bus 136 and included in the processor-based system 128 to each other. As is well known, the CPU (s) 130 communicate with these other devices by exchanging address, control, and data information over the system bus 136. For example, the CPU (s) 130 may communicate bus transaction requests to the memory controller 138 as an example of a slave device. Although not illustrated in FIG. 13, a number of system buses 136 may be provided, where each system bus 136 constitutes a different circuit.

[0067] Other master and slave devices may be coupled to the system bus 136. As illustrated in Figure 13, these devices include, by way of example, memory system 140, one or more input devices 142, one or more output devices 144, one or more network interface devices 146, And display controllers 148. [ The input device (s) 142 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. Output device (s) 144 may include any type of output device, including, but not limited to, audio, video, other visual indicators, The network interface device (s) 146 may be any device configured to allow exchange of data to and from the network 150. [ The network 150 may be any type of network including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wide local area network (WLAN) have. The network interface device (s) 146 may be configured to support any type of communication protocol desired. Memory system 140 may include one or more memory units 152 (0-N).

The CPU (s) 130 may also be configured to access the display controller (s) 148 via the system bus 136 to control information transmitted to the one or more displays 154 . Display controller 148 transmits information to be displayed to display (s) 154 via one or more video processors 156 that process the information to be displayed into a format suitable for display (s) 154 . Display (s) 154 include any type of display including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, can do.

[0069] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits and algorithms described in connection with the embodiments disclosed herein may be implemented within a computer-readable medium such as a memory, Or instructions executed by the device, or combinations of the two. The master devices and slave devices described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip as an example. The memories disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How this functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0070] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field- Gate Array) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented in a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0071] The embodiments disclosed herein may be implemented in hardware and stored in hardware, for example, in a random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art . An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integrated into the processor. The processor and the storage medium may reside within an ASIC. The ASIC may reside within the remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0072] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described may be performed in a number of different sequences besides the sequences illustrated. Further, the operations described in the single operation step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. It will be appreciated that the operating steps illustrated in the flowcharts can be made by a number of different modifications as will be readily apparent to those skilled in the art. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may refer to voltages, currents, electromagnetic waves, , Light fields or particles, or any combination thereof.

[0073] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Accordingly, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (30)

A static random access memory (SRAM)
A memory access logic circuit provided in a first data access path; And
And a pre-charge circuit provided in a second data access path separate from the first data access path,
The memory access logic circuit comprising:
Receive a data entry address of a memory access request to address a data entry of the SRAM data array in the first data access path; And
And to generate a data index based on the received data entry address in the first data access path to index the SRAM data array to access a data entry of the SRAM data array corresponding to the received data entry address,
The pre-charge circuit, prior to accessing the data entry of the SRAM data array,
Receive a data entry address in the second data access path; And
A pre-charge enable for at least a portion of the SRAM data array based on the received data entry address in the second data access path to pre-charge at least a portion of the SRAM data array Lt; / RTI >
SRAM. The method according to claim 1,
The SRAM data array includes:
A plurality of SRAM data sub-arrays,
SRAM. 3. The method of claim 2,
The pre-charge circuit comprises:
And generate a pre-charge enable for each of the plurality of SRAM data sub-arrays based on the received data entry address.
SRAM. 3. The method of claim 2,
The pre-charge circuit comprises:
And to generate a pre-charge index as an output indicative of an SRAM data sub-array location from the plurality of SRAM data sub-arrays based on the received data entry address.
SRAM. The method according to claim 1,
Charge signal for the SRAM data array based on an assertion of a word line signal,
SRAM. The method according to claim 1,
The memory access logic circuit may further comprise:
And a tag array for indexing the data entry based on the received data entry address.
SRAM. The method according to claim 6,
The SRAM data array includes a plurality of SRAM data sub-arrays.
SRAM. The method according to claim 6,
The pre-charge circuit comprises:
And to generate a pre-charge enable for each of a plurality of SRAM data sub-arrays based on the received data entry address.
SRAM. The method according to claim 6,
The pre-charge circuit comprises:
And to generate a pre-charge index as an output indicative of an SRAM data sub-array location from a plurality of SRAM data sub-arrays based on the received data entry address.
SRAM. The method according to claim 6,
Charge signal for the SRAM data array based on assertion of a word line signal,
SRAM. The method according to claim 6,
A clock signal for the memory access request and a bit line pre-charge signal upon assertion of the pre-charge enable,
SRAM. 12. The method of claim 11,
The pre-charge circuit comprises:
To pre-charge the SRAM data array for at least a portion of the SRAM data array based on a received data entry address for a first memory access request of the second data access path, And to receive a data entry address for a second memory access request as a second input for addressing a second data entry of the SRAM data array in the first data access path,
SRAM. 13. The method of claim 12,
The pre-charge circuit comprises:
Charge signal to generate the bit line pre-charge signal at the time of assertion of the pre-charge enable and to pre-charge at least a portion of the SRAM data array, Charge enable for the second memory access request for at least a portion of the SRAM data array based on a received data entry address for a second memory access request.
SRAM. The method according to claim 6,
Integrated within the integrated circuit,
SRAM. The method according to claim 6,
A personal digital assistant (PDA), a monitor, a computer monitor, a personal digital assistant (PDA), a personal digital assistant (PDA) Which is incorporated in a device selected from the group consisting of a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disk (DVD) player,
SRAM. The method according to claim 1,
A clock signal for the memory access request and a bit line pre-charge signal upon assertion of the pre-charge enable,
SRAM. 17. The method of claim 16,
The pre-charge circuit comprises:
To pre-charge the SRAM data array for at least a portion of the SRAM data array based on a received data entry address for a first memory access request of the second data access path, And to receive a data entry address for a second memory access request as a second input for addressing a second data entry of the SRAM data array in the first data access path,
SRAM. 18. The method of claim 17,
The pre-charge circuit comprises:
Charge signal to generate the bit line pre-charge signal at the time of assertion of the pre-charge enable and to pre-charge at least a portion of the SRAM data array, Charge enable for the second memory access request for at least a portion of the SRAM data array based on a received data entry address for a second memory access request.
SRAM. The method according to claim 1,
Integrated within the integrated circuit,
SRAM. The method according to claim 1,
A personal digital assistant (PDA), a monitor, a computer monitor, a personal digital assistant (PDA), a personal digital assistant (PDA) Which is incorporated in a device selected from the group consisting of a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disk (DVD) player,
SRAM. A static random access memory (SRAM)
Memory access logic circuit means provided in the first data access path means; And
And pre-charge circuit means provided in a second data access path means separate from the first data access path means,
Wherein the memory access logic circuit means comprises:
To receive data entry address means for memory access request means for addressing data entry means of SRAM data array means in said first data access path means; And
In the first data access path means for indexing the SRAM data array means to access the data entry means of the SRAM data array means corresponding to the data entry address means, ≪ / RTI >
The pre-charge circuit means, prior to accessing the data entry means of the SRAM data array means,
To receive the data entry address means from the second data access path means; And
To generate pre-charge enable means for at least a portion of the SRAM data array means based on the received data entry address means in the second data access path means for pre-charging at least a portion of the SRAM data array means Lt; / RTI >
SRAM. A method of pre-charging an SRAM data array prior to accessing a static random access memory (SRAM) data array,
Receiving a data entry address in a first data access path for a memory access request for addressing a data entry of the SRAM data array;
Generating a data index based on the received data entry address in the first data access path to index the SRAM data array to access a data entry of the SRAM data array corresponding to the data entry address;
Receiving a data entry address in a second data access path to pre-charge at least a portion of the SRAM data array; And
Generating a pre-charge enable for at least a portion of the SRAM data array based on the received data entry address in the second data access path to pre-charge at least a portion of the SRAM data array ,
Wherein the pre-charge enable is generated prior to accessing the data entry of the SRAM data array of the data index indicating the data entry address in the first data access path,
A method for pre-charging an SRAM data array prior to accessing the SRAM data array. 23. The method of claim 22,
Generating a bit line pre-charge signal for a memory access request for at least a portion of the SRAM data array based on the received data entry address in the second data access path
Further comprising:
Wherein the bitline pre-charge signal is generated prior to accessing a data entry of an SRAM data array of a data index representing the data entry address in the first data access path,
A method for pre-charging an SRAM data array prior to accessing the SRAM data array. 23. The method of claim 22,
Receiving a data entry address in the first data access path for a memory access request for addressing a data entry of the SRAM data array,
The SRAM data array includes a plurality of SRAM data sub-arrays.
A method for pre-charging an SRAM data array prior to accessing the SRAM data array. 23. The method of claim 22,
Charge signal based on a clock signal for the memory access request and an assertion of the pre-charge enable;
A method for pre-charging an SRAM data array prior to accessing the SRAM data array. 26. The method of claim 25,
A pre-charge enable for at least a portion of the SRAM data array based on the received data entry address for a first memory access request of the second data access path to pre-charge at least a portion of the SRAM data array Receiving a data entry address for a second memory access request as a second input for addressing a second data entry of the second data access path to pre-charge at least a portion of the SRAM data array,
≪ / RTI >
A method for pre-charging an SRAM data array prior to accessing the SRAM data array. 27. The method of claim 26,
To generate a bit line pre-charge signal based on an assertion of a clock signal for the first memory access request and an assertion of a pre-charge enable, to pre-charge at least a portion of the SRAM data array Generating a pre-charge enable for a second memory access request for at least a portion of the SRAM data array based on the received data entry address in the path
≪ / RTI >
A method for pre-charging an SRAM data array prior to accessing the SRAM data array. 23. The method of claim 22,
Wherein the step of generating a data index in the first data access path to index a data entry of the SRAM data array comprises:
Receiving the data index by a tag array to index a data entry based on the received data index;
≪ / RTI >
A method for pre-charging an SRAM data array prior to accessing the SRAM data array. 23. The method of claim 22,
Generating a bit line pre-charge signal based on the assertion of the pre-charge enable and the assertion of the clock signal;
A method for pre-charging an SRAM data array prior to accessing the SRAM data array. 30. The method of claim 29,
Wherein the generating the bit line pre-charge signal comprises disabling the assertion of the array enable and the assertion of the clock signal,
A method for pre-charging an SRAM data array prior to accessing the SRAM data array.

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