JP2001319479A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device in which the power consumption required for pre-charge is less. SOLUTION: Before a processor 400 performs memory access, a bit line to be pre-charged is predicted by a bit line variation predicting circuit 120 based on variation of an address signal 10, pre-charge is performed for only a bit line predicted by an output signal 121 of the bit line variation predicting circuit, the power consumption is reduced without delaying access time to a memory by performing no pre-charge for the other bit lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a memory device having a precharge function.

[0002]

2. Description of the Related Art <Background of the Invention> In a normal memory circuit,
Every bit line in the memory circuit is precharged every time the memory is accessed. Therefore, power consumption is large because unused bit lines are precharged. As a memory circuit for solving this problem and reducing power consumption, there is JP-A-7-230691.

<Conventional Example> FIG. 6 shows an example of a conventional memory circuit. This memory circuit is connected to the address signal 10. The address signal 10 is connected to a precharge control circuit 100, a word line selection circuit 220, and a bit line selection circuit 230. The data of the memory cell in the memory cell array 250 selected by the word line selection circuit 220 and the bit line selection circuit 230 is transferred to the sense amplifier 2.
Read from 40. At this time, the bit line to be precharged is selected by the precharge control circuit 100, and the precharge circuit 210 performs the precharge.

FIG. 7 shows details of a conventional precharge control circuit. The input address signal passes through the address buffer 110 and passes through the latch circuit 150 and the comparison circuit 160.
To enter. The latch circuit operates by the clock 302. The comparison circuit 160 compares the portion of the output of the address buffer 110 and the output of the latch circuit 150 related to bit line selection. If the comparison results are equal, the bit line accessed last time and the bit line accessed this time are It is determined that they are equal, otherwise, it is determined that the bit lines used in the previous time and this time are different, and the information of the bit lines to be precharged is output to the precharge circuit 210. In this patent, power consumption is reduced by appropriately selecting a bit line to be precharged from an address signal and precharging only necessary bit lines.

<Main Defects in the Related Art> In the related art, since the address signal is compared with a specific value at the time of memory access, it takes time to select a bit line to be precharged. <Reason for causing the above-mentioned disadvantage> That is, in the above-described conventional example, it takes time to select a bit line to be precharged in order to compare address signals after starting memory access.

[0006]

SUMMARY OF THE INVENTION In view of the above-mentioned disadvantages of the prior art, the present invention reduces the power consumption required for precharging and reduces the time required for selecting a bit line to be precharged. It is an object of the present invention to provide a memory device which can be used.

[0007]

A memory device according to the present invention, which achieves the above object, comprises: (1) predicting a bit line to be precharged before a processor accesses a memory, and only predicting the bit line during memory access. By precharging and not precharging other bit lines,
The power consumption is reduced without delaying the access time to the memory. 2: Before a microcomputer or signal processor having a structure in which an instruction memory and a data memory are separated from each other performs a memory access in address order, selects a word line of an address signal for memory access to a bit line to be precharged. Prediction is performed based on bits, and at the time of memory access, only the predicted bit line is precharged, and other bit lines are not precharged.
The power consumption is reduced without delaying the access time to the memory. 3: Before a microcomputer or a signal processing processor having a structure in which an instruction memory and a data memory are separated from each other, select a word line of an address signal for accessing a bit line to be precharged before performing a memory access in an address order. Predict by comparing the bit with a specific value, and at the time of memory access, only the predicted bit line is precharged, and the other bit lines are not precharged, so that the memory access time is not delayed Power consumption is reduced. 4: In the prediction, when all the bits for selecting the word line of the current address signal are at the same level, it is predicted that the bit line used in the next memory access is different from the bit line used in the current memory access. And otherwise,
The bit line used in the current memory access is predicted to be equal to the bit line used in the previous memory access. 5: The same level is a high level. 6: When a branch instruction or an interrupt occurs, all bit lines are precharged. 7: A plurality of word lines, a plurality of bit lines, a memory cell array including a plurality of memory cells connected to the word lines and the bit lines, and a plurality of the bit lines prior to reading data from the memory array. A precharge circuit for precharging; a sense amplifier for amplifying data read from the memory array; and one of the plurality of word lines based on an address signal.
A word line selection circuit for selecting one of the word lines and a bit line selection circuit for selectively connecting the plurality of bit lines to the sense amplifier based on the address signal. A memory circuit from which data of a memory cell connected to the bit line is read, an address signal for accessing the memory circuit,
A read control signal), an interrupt control signal output when a branch and an interrupt occur, and a processor that captures data read from the memory circuit, a precharge selection circuit, a precharge timing generation circuit, A memory device that precharges the bit line before the processor performs a memory access, wherein a bit line to be precharged before the processor performs a memory access is predicted based on a change in an address signal. A bit line change prediction circuit and a signal for precharging only the bit line predicted by an output signal of the bit line change prediction circuit, and outputting a signal for preventing other bit lines from performing precharge to the precharge circuit. A precharge control signal generation circuit for A recharge selection circuit is provided to predict a bit line to be precharged before the processor performs a memory access, and at the time of a memory access, only the predicted bit line is precharged, and other bit lines are not precharged. By doing
The power consumption is reduced without delaying the access time to the memory. 8: The bit line change prediction circuit compares a bit for selecting the word line of the current address signal with a specific value, and when all the bits match, a signal allowing all bit lines to be precharged. Is output to the precharge control signal generation circuit, and when they do not match, a signal allowing precharge of the bit line used in the previous memory access is output to the precharge control signal generation circuit. Be characterized. 9: The specific value is at a high level. 10: When the processor outputs a branch instruction and an interrupt control signal output when an interrupt occurs, all bit lines are precharged. 11: A plurality of bank memory circuits including the memory circuits are provided, and outputs of the plurality of bank memory circuits are selected by a multiplexer based on the address signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on examples. 1 to 4 show embodiments of the present invention,
FIG. 5 shows another embodiment of the present invention. The present invention predicts the selection of the bit line to be precharged from the address signal used in the previous memory access, and at the start of the memory access, the state in which the selection of the bit line to be precharged has already been completed. A memory access that precharges only necessary bit lines without taking time for bit line selection can be performed. In a processor such as a microcomputer or a signal processing processor (DSP) having a structure in which the instruction memory and the data memory are separated, the instruction memory storing the processor instructions is stored in the address memory in the order of addresses except when there is a branch instruction and an interrupt. to access.
Therefore, the address used in the next memory access can be easily predicted from the address information used in the previous memory access. When a branch or an interrupt occurs, it is only required that any address can be selected. Hereinafter, embodiments of the present invention will be described with reference to FIGS.

<Structure of Embodiment> FIG. 1 shows an embodiment of the present invention. The processor 400 outputs the address signal 10 and the read control signal 30, accesses a predetermined address of the memory circuit 200, and inputs data from the signal 241. In addition, the processor 400 outputs the H level to the control signal 20 when a branch or an interrupt occurs, and outputs the L level to the control signal 20 otherwise to control the precharge control circuit 100.

The precharge control circuit 100 comprises a bit line change prediction circuit 120 and a precharge control signal generation circuit 170. Bit line change prediction circuit 120
Is connected to the address signal 10 output from the processor 400, predicts a change in the bit line used in the next memory access from the bit line used in the current memory access, and changes the bit line used in the next memory access. If so, an H level is output to the precharge control signal generation circuit 170 otherwise.

The precharge control signal generation circuit 170
The precharge control signal is connected to the address signal 10 of the output of the processor 400, the control signal 20 of the output of the processor 400, the output 301 of the precharge timing generation circuit 300, and the output signal 121 of the bit line change prediction circuit 120. It is generated and output to the memory circuit 200.

The memory circuit 200 includes an address signal 10 output from the processor 400, a read control signal 30 output from the processor 400, outputs 165 to 168 from the precharge control circuit 100, and an output 301 from the precharge timing generation circuit 300. , And precharges only the bit line specified by the precharge control circuit 100, and transfers the data at the specified address to the processor 40.
Output to 0.

FIG. 2 is a detailed diagram of the precharge control circuit 100. The bit line change prediction circuit 120 is connected to the address signal 10 at the output of the processor 400 in FIG.
From the value of the address signal 10 output from the processor 400 in FIG. 1, the H level is set when the bit line used in the next memory access can be expected to change from the bit line used in the current memory access, and otherwise the L level is set. Output to the precharge control signal generation circuit 170.

The precharge control signal generation circuit 170
A bit line selection circuit 130, latch circuits 151 to 154,
It is composed of OR gates 141 to 144 and 161 to 164.

The bit line selection circuit 130 is connected to the address signal 10 output from the processor 400 in FIG.
A bit line to be precharged is selected according to the value of the address signal 10 output from the processor 400, and is output to the OR gates 141 to 144.

The OR gates 141 to 144 are connected to the outputs 131 to 134 of the bit line selection circuit 130 and the output 121 of the bit line change prediction circuit 120. When the output 121 of the bit line change prediction circuit 120 is at H level, When all the bit lines are set to the H level, the output 1 of the bit line change prediction circuit 120 is output.
When the signal 21 is at the L level, only the signal selected by the bit line selection circuit 130 is output at the H level, and the other signals are output at the L level to the latch circuits 151 to 154.

The latch circuits 151 to 154 are connected to the outputs 145 to 148 of the OR gates 141 to 144 and the output 301 of the precharge timing generation circuit 300, and output latched signals to the OR gates 161 to 164.

The OR gates 161 to 164 are connected to the control signal 20 output from the processor 400 of FIG.
1 to 154 are connected to outputs 155 to 158. When the control signal 20 of the output of the processor 400 of FIG. 1 is at H level, the output of the OR gates 161 to 164 outputs the signal of H level regardless of the state of the latch circuits 151 to 154. Output control signal 20
Is L level, the signals latched by the latch circuits 151 to 154 are output to the memory circuit 200 in FIG.

FIG. 3 is a detailed diagram of the bit line change prediction circuit 120. The bit line change prediction circuit 120 includes a comparison circuit 122 that compares the value of the address signal 10 output from the processor 400 in FIG. 1 with a specific value (the comparison data shown in FIG. 3 and usually “H”). The comparison circuit 122 outputs an H-level signal to the precharge control signal generation circuit 170 if the data to be compared match, otherwise outputs an L-level signal.

FIG. 4 is a detailed diagram of the memory circuit 200. The AND gates 201 to 204 are connected to the outputs 165 to 168 of the precharge control circuit 100 of FIG. 1 and the output 301 of the precharge timing generation circuit 300 of FIG. 1, respectively. Only the bit line specified by the signal generation circuit 100 is H
A signal that becomes a level is generated and output to the precharge circuit 210.

The precharge circuit 210 is connected to the outputs 205 to 208 of the AND gates 201 to 204, and outputs bit lines 211 to 214 and inverted bit lines 215 to 218.
Are precharged to a designated bit line pair.

The word line selection circuit 220 is connected to the address signal 10 output from the processor 400 in FIG. Address signal 10 at the output of processor 400 in FIG.
The word lines 221 to 222 are selected according to the value of. The memory cells 251 to 258 include bit line pairs 211 to 218
And the value of the word lines 221 to 222 so that one cell is selected. The bit line selection circuit 230 is connected to the address signal 10 output from the processor 400 in FIG. 1 and the bit lines 211 to 218. Address signal 10 at the output of processor 400 in FIG.
The bit line is selected according to the value of the bit line and output to the sense amplifier 240.

The sense amplifier 240 is connected to the read control signal 30 of the output of the processor 400 of FIG. 1 and the output 231 of the bit line selection circuit 230. When the read control signal 30 of the output of the processor 400 of FIG. 1 becomes active, the data of the bit line selected by the bit line selection circuit 230 is read, and the data is transferred to the processor 400 of FIG.
Output to

<Explanation of the Operation of the Embodiment> Next, the operation of the embodiment will be described with reference to FIGS. For the sake of explanation, the memory circuit 200 in FIG. 1 has a circuit configuration in which a bit line is selected by 5 bits of an address signal and 2 high-order bits, and a word line is selected by 3 low-order bits. Further, in the next memory access in which the lower three bits of the address signal 10 of the output of the processor 400 in FIG. 1 are all at H level, a different bit line is used.
Therefore, the bit line change prediction circuit 120 of FIG. 1 changes the H level when all the lower 3 bits of the address signal 10 of the output of the processor 400 of FIG.
Otherwise, an L level is output.

When the processor 400 of FIG. 1 is performing continuous memory access, the address information of the data read by the processor 400 is the address signal 10 of the output of the processor 400, and the precharge selection circuit 100 of FIG.
Is input to the memory circuit 200 of FIG. 1. The processor 400 of FIG. 1 input to the precharge control circuit 100 of FIG.
2 are input to the bit line selection circuit 130 shown in FIG. Processor 4 of FIG.
The output 131 to 1 of the bit line selection circuit 130 in FIG.
34 are output to the latch circuits 151 to 154 when one of them is selected and the H level is output, and the other three signals are the L level signals.

The address signal 10 of the output of the processor 400 of FIG. 1 input to the precharge control circuit 100 of FIG.
The lower three bits of the bit line change prediction circuit 120 of FIG.
To enter. Address signal 1 of output of processor 400
If all the lower three bits of 0 are not H level, the bit line change prediction circuit 120 determines that the bit line used in the next memory access is equal to the bit line used in the current memory access, and Output a signal. In this case, the information of the bit line selected by the bit line selection circuit 130 of FIG. 2 is latched by the latch circuits 151 to 154 of FIG. 2, and at the next memory access, the latched signal becomes the signal of FIG. The signal passes through the OR gates 161 to 164 and is output to the memory circuit 200 in FIG.

When all the lower 3 bits of the address signal 10 output from the processor 400 of FIG. 1 are at the H level, it is predicted that the bit line used in the next memory access is different from the bit line used in the current memory access. Therefore, the bit line change prediction circuit 120 of FIG. 1 outputs an H level signal. In this case, the bit line selection circuit 13 shown in FIG.
OR gates 141 to 14 in FIG.
4 outputs an H-level signal, all of the latch circuits 151 to 154 in FIG.
At the time of the next memory access, the latched signal passes through the OR gates 161 to 164 in FIG. 2 and is output to the memory circuit 200 in FIG. The latch circuits 151 to 151 in FIG.
Reference numeral 154 denotes the bit line selection signal selected and latched at the time of the previous memory access and output at the current memory access.

If the bit line change prediction circuit 120 in FIG. 1 outputs an L level signal in the previous memory access, the bit line used in the current memory access and the bit line used in the previous memory access are used. The bit lines are equal, so that a selection signal for precharging only the bit line previously selected by the bit line selection circuit 130 in FIG. 2 is output.

If the bit line change prediction circuit 120 shown in FIG. 1 outputs an H level signal in the previous memory access, the bit line used in the current memory access is the bit selected in the previous memory access. Since these lines are different from the lines, all the latch circuits 151 to 154 in FIG. 2 output H-level signals and output control signals for precharging all the bit lines.

The output control signal 20 of the processor 400 shown in FIG. 1 is a signal used when a branch or an interrupt occurs. If the output control signal 20 of the processor 400 is at H level, the latch signal shown in FIG. Regardless of the outputs of the circuits 151 to 154, a signal for selecting all bit lines is output to the memory circuit 200 of FIG. When a branch or an interrupt occurs, the address to be used in the next memory access is unknown, so it is unknown which bit line is used. Therefore, by setting the control signal 20 of the output of the processor 400 of FIG. 1 to the H level and precharging all the bit lines, it is possible to cope with the occurrence of the branch and the interruption.

When the control signal 20 output from the processor 400 in FIG. 1 is at L level, the latch circuits 151 to 1 in FIG.
The output of the bit line 54 is output to the memory circuit 200 of FIG. 1 through the OR gates 161 to 164 of FIG. 2, and only the selected bit line is precharged by the precharge circuit 210 of FIG. No precharge is performed on the line.

<Another Embodiment of the Invention> FIG. 5 shows another embodiment of the present invention. The memory circuit 200 includes two bank memory circuits 280 and 282, and outputs the outputs of the two bank memory circuits 280 and 282 to a multiplexer 290.
The circuit configuration is selected by. In other respects, the circuit configuration is the same as that of the above embodiment. The processor 400 outputs the address signal 10 and the read control signal 30, accesses a predetermined address of the memory circuit 200, and inputs data from the signal 241. Further, the processor 400 outputs an H level signal to the control signal 20 when a branch and an interrupt occur, and otherwise outputs an L level signal to the control signal 20 to control the precharge control circuit 100.

The precharge control circuit 100 includes a bit line change prediction circuit 120 and a precharge control signal generation circuit 170. Bit line change prediction circuit 120
Is connected to the address signal 10 output from the processor 400, predicts a change in the bit line used in the next memory access from the bit line used in the current memory access, and sets the bit line used in the next memory access to H level if it can be expected to be different from the bit line used this time,
Otherwise, an L-level signal is output to precharge control signal generation circuit 170.

The precharge control signal generation circuit 170
The address signal 10 of the output of the processor 400, the control signal 20 of the output of the processor 400, the output 301 of the precharge timing generation circuit 300, and the output 121 of the bit line change prediction circuit 120 are connected to generate a precharge control signal. Then, the data is output to the memory circuit 200.

The memory circuit 200 includes a bank 0 memory circuit 280 and a bank 1 memory circuit 282.
The bank is selected by the most significant bit of the address signal 10. The bank 0 memory circuit 280 and the bank 1 memory circuit 282 provide the address signal 1 of the output of the processor 400.
0 and the read control signal 30 of the output of the processor 400
And outputs 180 and 181 of the precharge control circuit 100
And the output 30 of the precharge timing generation circuit 300
1, precharges only the bit line specified by the precharge control circuit 100, and outputs data of the specified address to the multiplexer 290.

The multiplexer 290 is connected to the processor 40
0 address signal 10 and the bank 0 memory circuit 2
80 and an output 283 of the bank 1 memory circuit 282. A bank is selected according to the value of the most significant bit of the address signal 10 output from the processor 400, and data is output to the processor 400.

The precharge control circuit 100 is the same as the precharge control circuit shown in FIG. Each of the bank memory circuits 280 and 282 is the same as that shown in FIG.
Is the same as the memory circuit of FIG. The operation of this embodiment is the same as that of the previous embodiment except that a multiplexer 290 is used for selecting a bank. As described above, the present invention can be used even in a memory having a structure in which banks are separated.

[0038]

Since the selection of the bit line to be precharged has been completed before the start of the memory access, it does not take much time to select whether or not to perform the precharge. By doing
A memory circuit for reducing power consumption is configured. In addition, in the conventional example, it takes time to select the bit line to be precharged in order to compare the address signals after starting the memory access. However, in the present invention, the comparison of the address signals is not performed, and the comparison of the address signals is not performed. Lower 3 of signal
When all the bits are at the H level, the bit line used in the next memory access is predicted to be different from the bit line used in the current memory access, so that the time required for selecting the bit line to be precharged can be reduced.

<Reason why power can be reduced by selecting precharge> In the memory circuit, in order to reduce the memory cell size per bit, a minute voltage difference is detected by a sense amplifier to determine 1 or 0. The wiring (bit line) from the memory cell to the sense amplifier has a stray capacitance, and since the stray capacitance is slightly different due to manufacturing variations, an operation precharge that charges the stray capacitance before detecting a minute voltage difference. A charging operation is required. The power required for the precharge operation depends on the stray capacitance of the bit line, and increases as the memory size increases. In the present invention , by selectively performing the precharge operation, the number of bit lines at the time of the precharge operation is reduced, and the power for charging the stray capacitance is reduced. For the sake of explanation, the address signal is 5 bits, the bit line selection is the upper 2 bits, and the word line selection is the lower 3 bits. What is the number of bits of the address signal, the number of bits of the word line, and the number of bits of the bit line? It can be done in combination.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a memory device according to the present invention.

FIG. 2 is a detailed diagram of a precharge control circuit according to the embodiment of the present invention.

FIG. 3 is a detailed diagram of a bit line change prediction circuit according to the embodiment of the present invention.

FIG. 4 is a detailed diagram of a memory circuit according to an embodiment of the present invention.

FIG. 5 shows another embodiment of the memory device of the present invention.

FIG. 6 shows a conventional memory circuit.

FIG. 7 shows a precharge control circuit of a conventional memory circuit.

[Explanation of symbols]

 141-144, 161-164 OR gate 201-204 AND gate 211-218 Bit line 221-222 Word line 251-258 Memory cell

Claims (11)

[Claims] 1. A processor predicts a bit line to be precharged before performing a memory access, and precharges only the predicted bit line and does not precharge other bit lines during a memory access. Without delaying the access time to memory
Memory device characterized by reduced power consumption 2. A word line of an address signal for memory-accessing a bit line to be precharged before a microcomputer or a signal processing processor having a structure in which an instruction memory and a data memory are separated performs memory access in address order. Power consumption without delaying the memory access time by precharging only the predicted bit lines and not precharging other bit lines during memory access. Memory device characterized by reduced noise 3. A word line of an address signal for making a memory access to a bit line to be precharged before a microcomputer or a signal processing processor having a structure in which an instruction memory and a data memory are separated performs memory access in address order. By comparing the bit to select with a specific value, at the time of memory access, only the predicted bit line is precharged, and the other bit lines are not precharged, thereby delaying the memory access time. Memory device characterized by reduced power consumption without performing 4. The prediction is performed when all bits for selecting a word line of the current address signal are at the same level.
It is predicted that the bit line used in the next memory access will be different from the bit line used in the current memory access. Otherwise, the bit line used in the current memory access and the bit line used in the previous memory access will be 4. The memory device according to claim 2, wherein the lines are predicted to be equal. 5. The memory device according to claim 4, wherein the same level is a high level. 6. The memory device according to claim 1, wherein when a branch instruction or an interrupt occurs, all bit lines are precharged. 7. A plurality of word lines, a plurality of bit lines,
A memory cell array including a plurality of memory cells connected to the word lines and the bit lines; a precharge circuit for precharging the plurality of bit lines prior to reading data from the memory array; A sense amplifier for amplifying the read data; a word line selection circuit for selecting any one of the plurality of word lines based on an address signal; and a plurality of bit lines based on the address signal. A bit line selection circuit for selectively connecting to the sense amplifier; a memory circuit from which data of a memory cell connected to a selected word line and a selected bit line is read; An address signal for access;
A read control signal), an interrupt control signal output when a branch and an interrupt occur, and a processor that captures data read from the memory circuit, a precharge selection circuit, a precharge timing generation circuit, A memory device that precharges the bit line before the processor performs a memory access, wherein a bit line to be precharged before the processor performs a memory access is predicted based on a change in an address signal. A bit line change prediction circuit and a signal for precharging only the bit line predicted by an output signal of the bit line change prediction circuit, and outputting a signal for preventing other bit lines from performing precharge to the precharge circuit. A precharge control signal generation circuit for A recharge selection circuit is provided to predict a bit line to be precharged before the processor performs a memory access, and at the time of a memory access, only the predicted bit line is precharged, and other bit lines are not precharged. By doing
A memory device having reduced power consumption without delaying access time to a memory. 8. The bit line change prediction circuit compares a bit for selecting a word line of the current address signal with a specific value, and when all the bits match, precharges all the bit lines. An allowable signal is output to the precharge control signal generation circuit, and if they do not match, a signal allowing the precharge of the bit line used in the previous memory access is output to the precharge control signal generation circuit. The memory device according to claim 7, wherein the memory device is configured. 9. The memory device according to claim 8, wherein the specific value is at a high level. 10. The memory device according to claim 6, wherein when the processor outputs a branch instruction and an interrupt control signal output when an interrupt occurs, all the bit lines are precharged. 11. The memory device according to claim 7, wherein a plurality of bank memory circuits each including said memory circuit are provided, and outputs of said plurality of bank memory circuits are selected by a multiplexer based on said address signal. .