CN201845782U - Metal-oxide semiconductor (MOS) transistor and complementary metal-oxide semiconductor (CMOS) image sensor - Google Patents
Metal-oxide semiconductor (MOS) transistor and complementary metal-oxide semiconductor (CMOS) image sensor Download PDFInfo
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- CN201845782U CN201845782U CN2010205756544U CN201020575654U CN201845782U CN 201845782 U CN201845782 U CN 201845782U CN 2010205756544 U CN2010205756544 U CN 2010205756544U CN 201020575654 U CN201020575654 U CN 201020575654U CN 201845782 U CN201845782 U CN 201845782U
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Abstract
The utility model discloses a metal-oxide semiconductor (MOS) transistor and a complementary metal-oxide semiconductor (CMOS) image sensor. The MOS transistor comprises a semiconductor substrate, wherein a grid electrode is arranged on the semiconductor substrate, the grid electrode comprises a grid oxide layer and a grid conduction layer positioned on the grid oxide layer, and a source electrode region and a drain electrode region are arranged in the semiconductor substrate arranged at both sides of the grid electrode. The MOS transistor is characterized in that the grid oxide layer comprises a nitrogenous silicon oxide layer and a nitrogen-free silicon oxide layer, and the nitrogen-free silicon oxide layer is positioned between the nitrogenous silicon oxide layer and the semiconductor substrate. Thereby, the stability of the MOS transistor is improved, and the precision of the image sensor is higher.
Description
Technical field
The utility model relates to technical field of manufacturing semiconductors, particularly MOS transistor and cmos image sensor.
Background technology
At present, there is multiple noise in imageing sensor, and these noises will be exported together with signal, thereby has caused the image quality decrease of output.Wherein, noise source comprises: fixed pattern noise, flicker noise and optical noise.Fixed pattern noise generally can be eliminated by signal is carried out filtering, and optical noise can reach the purpose that weakens by adjusting and dielectric attenuate of rear end metal, yet flicker noise can't be removed by subsequent conditioning circuit.
Flicker noise claims 1/f noise again, at CCD (Charge-coupled Device, charge coupled cell) in the structure of transducer, because a row CCD has only the such amplifying device of a source follower (being generally a MOS transistor), it is very big that thereby the area of source follower MOS transistor can be done, along with the increase of area can make flicker noise reduce greatly.Advantages such as cmos image sensor has the integrated level height for ccd image sensor, low in energy consumption, and cost is low have obtained application more and more widely.Yet for cmos image sensor, the design of pixel has a variety of structures, generally comprises n transistor, and each transistor is realized different functions.The cmos image sensor pixel is modal to be 3T and 4T structure.Be illustrated in figure 1 as the schematic diagram of the pixel of 1 3T structure of cmos image sensor, the 3T structure promptly has three transistors in pixel, be respectively reset transistor RST, source follower SF and row gating switch pipe SEL (4T has increased a transfer tube on the basis of 3T), in each pixel, a photodiode PD is all arranged, be used for light signal is changed into the signal of telecommunication, thereby reach the purpose of sensitization.No matter 3T still is the pixel of 4T structure, and each pixel all needs an independent source follower (being generally a MOS transistor).Increase along with number of pixels in the cmos image sensor, for the area that guarantees CMOS graphical sensory device does not increase, just need reduce elemental area, the area of source follower MOS transistor just need reduce like this, therefore flicker noise itself can reduce along with the area of source follower MOS transistor and increase, one of stack can't be by the noise of subsequent conditioning circuit removal when the existence of flicker noise made picture signal output, make final output image can seem more crude, signal noise ratio (snr) of image descends, and has had a strong impact on the quality of cmos image sensor.In addition, in the cmos image sensor, the flicker noise that transmission mos transistor brings also can be brought bigger influence to cmos image sensor.
In the manufacturing technology of existing MOS transistor, usually at first on Semiconductor substrate, form grid oxide layer, on grid oxide layer, form grid conductive layer, form grid by etching grid conductive layer and grid oxide layer then, then the substrate intermediate ion in the grid both sides injects and forms source area and drain region, thereby forms MOS transistor.Wherein, described grid oxide layer utilizes oxide to form usually, for example silicon dioxide (SiO
2) or doped silica.In the manufacture process of MOS transistor, ion injects when forming source area and drain region, and the P type or N type ion break-through (boron) grid of injection arranged simultaneously, enters grid oxide layer.The ion that described break-through enters can cause MOS transistor to produce leakage current or negative bias temperature stability (NBTI) variation.
In order to solve the problem of described leakage current, in the manufacturing process of existing MOS device, can utilize in nitrogenous atmosphere usually and anneal, thereby in grid oxide layer, introduce nitrogen-atoms, can hinder N type ion like this or P type ion enters grid oxide layer.Figure 2 shows that the flicker noise comparison diagram of the MOS device that nitrogenous grid oxide layer and nonnitrogenous grid oxide layer form, wherein curve S 1 is the flicker noise of the MOS device of nitrogenous grid oxide layer formation, and curve S 2 is the flicker noise of the MOS device of nonnitrogenous grid oxide layer formation.From Fig. 2 as seen, than the grid oxide layer of nitrating, silicon and silicon dioxide interface not the grid oxide layer flicker noise of nitrating have the order of magnitude other reduce.
In the Chinese patent literature of notification number " CN100369209C ", disclose the method for a kind of formation gate dielectric layer (grid oxide layer), having comprised: on Semiconductor substrate, formed silicon oxide layer; And use the plasma that contains inert gas and nitrogen that this silicon oxide layer is carried out first and second nitrating step, to form gate dielectric layer, wherein this second nitrating step in comparison, the power of this first nitrating step is lower, pressure is lower, but inert gas/nitrogen is than higher.
But in the above-mentioned grid oxide layer owing to introduce nitrogen-atoms, make a large amount of nitrogen-atoms (account for total atom number 2.5%) be present in silicon substrate and grid oxide layer at the interface, and the existence of nitrogen-atoms has increased the scattering at charge carrier and above-mentioned interface, make the fluctuation of electric current under the low frequency situation in the MOS transistor raceway groove strengthen, make the bad stability of MOS transistor.
Thereby above-mentioned MOS transistor is used in the cmos image sensor, serve as the source follower MOS transistor and can cause the flicker noise of cmos image sensor to increase.
The utility model content
In order to address the above problem, the utility model provides MOS transistor, makes the stability of MOS transistor improve.
The utility model also provides a kind of cmos image sensor, makes that the accuracy of imageing sensor is higher.
Wherein, a kind of MOS transistor comprises:
Semiconductor substrate, on described Semiconductor substrate, has grid, described grid comprises grid oxide layer and the grid conductive layer that is positioned on the grid oxide layer, have source area and drain region in the Semiconductor substrate of described grid both sides, described grid oxide layer comprises nitrogenous silicon oxide layer and the unazotized silicon oxide layer between nitrogenous silicon oxide layer and Semiconductor substrate.
Optionally, describedly contain the thickness of silicon oxynitride layer and the thickness ratio of unazotized silicon oxide layer is 1: 9 to 3: 7.
Optionally, the thickness of described grid oxide layer is 60 to 70 dusts.
Optionally, described silica is a silicon dioxide.
A kind of cmos image sensor comprises the photodiode, source follower transistor, reset transistor and the row gating switch transistor that are used to gather light intensity;
Described source follower transistor is described MOS transistor.
Optionally, described reset transistor is described MOS transistor.
Optionally, described capable gating switch transistor is described MOS transistor.
Optionally, also comprise transmission transistor, described transmission transistor is described MOS transistor.
Compare with prior art, advantage of the present utility model is:
Change into by grid oxide layer structure and to comprise nitrogenous silicon oxide layer and at the nitrogenous silicon oxide layer and the lamination layer structure of the unazotized silicon oxide layer between the Semiconductor substrate with MOS transistor, utilize nitrogenous silicon oxide layer to overcome the problem of the ion break-through of mixing like this, utilize unazotized silicon oxide layer to overcome the bad problem of interfacial state that nitrogen-atoms causes, thereby promptly reduced the leakage current of metal-oxide-semiconductor, the stability of MOS transistor also is provided, further this MOS transistor is used for CMOS graphical sensory device, reduced the flicker noise of imageing sensor, the accuracy of imageing sensor is provided.
Description of drawings
Fig. 1 is the circuit diagram of a kind of cmos image sensor of the prior art;
Fig. 2 is the flicker noise comparison diagram of the MOS device of nitrogenous grid oxide layer and the formation of nonnitrogenous grid oxide layer;
Fig. 3 is the structural representation of a kind of MOS transistor of the present utility model;
Fig. 4 is the flow chart of manufacture method one embodiment of MOS transistor of the present utility model;
Fig. 5-Figure 10 is the schematic diagram of manufacture method of an embodiment of MOS transistor of the present utility model;
Figure 11 is the image element circuit figure of cmos image sensor one embodiment of the present utility model;
Figure 12 is the image element circuit figure of another embodiment of cmos image sensor of the present utility model.
Embodiment
As seen the reference background technology in order to reduce the break-through problem of dopant ion, can introduce nitrogen-atoms in grid oxide layer, cause to make a large amount of nitrogen-atoms (account for total atom number 2.5%) be present in silicon substrate and grid oxide layer at the interface.Like this,, make the fluctuation increasing of electric current under the low frequency situation in the MOS transistor raceway groove, make the bad stability of MOS transistor because the existence of nitrogen-atoms has increased the scattering at charge carrier and above-mentioned interface.Thereby above-mentioned MOS transistor is used in the cmos image sensor, serve as the source follower MOS transistor and can cause the flicker noise of cmos image sensor to increase.
The utility model provides a kind of MOS transistor, change into by grid oxide layer structure and to comprise nitrogenous silicon oxide layer and in the structure of nitrogenous silicon oxide layer and the unazotized silicon oxide layer between the Semiconductor substrate with MOS transistor, utilize nitrogenous silicon oxide layer to overcome the problem of the ion break-through of mixing like this, utilize unazotized silicon oxide layer to overcome the bad problem of interfacial state that nitrogen-atoms causes, thereby promptly reduced the leakage current of metal-oxide-semiconductor, also improved the stability of MOS transistor, further this MOS transistor is used for CMOS graphical sensory device, reduce the flicker noise of imageing sensor, improved the accuracy of imageing sensor.
Fig. 3 is the structural representation of a kind of MOS transistor of the present utility model.As shown in Figure 3, comprise: Semiconductor substrate 100, on described Semiconductor substrate 100, has grid 108, described grid 108 comprises grid oxide layer and the grid conductive layer 106 that is positioned on the grid oxide layer, in the Semiconductor substrate of described grid both sides, have source area 110 and drain region 112, it is characterized in that described grid oxide layer comprises nitrogenous silicon oxide layer 102 and the unazotized silicon oxide layer 104 between nitrogenous silicon oxide layer 102 and Semiconductor substrate.Can also have gate lateral wall layer 105 in the grid both sides.Described grid conductive layer 106 is positioned on described nitrogenous silicon oxide layer 102 surfaces.
Wherein optional, the thickness of described nitrogenous silicon oxide layer and the thickness ratio of unazotized silicon oxide layer are 1: 9 to 3: 7.
Wherein optional, the thickness of described grid oxide layer is 60 to 70 dusts.
Wherein optional, described silica is a silicon dioxide.
Fig. 4 is the flow chart of manufacture method one embodiment of MOS transistor of the present utility model.
As shown in Figure 4, the manufacture method of MOS transistor of the present utility model comprises the following steps:
S110: Semiconductor substrate is provided;
S120: on Semiconductor substrate, form nitrogenous silicon oxide layer;
S130: form unazotized silicon oxide layer in the Semiconductor substrate under described nitrogenous silicon oxide layer, described nitrogenous silicon oxide layer and unazotized silicon oxide layer constitute grid oxide layer;
S140: on described grid oxide layer, form grid conductive layer;
S150: described grid conductive layer of etching and grid oxide layer form grid;
S160: in the Semiconductor substrate of grid both sides, form source area and drain region.
Fig. 5-Figure 10 is the schematic diagram of the manufacture method embodiment of MOS transistor of the present utility model.Below in conjunction with Fig. 4-Figure 10 embodiment of the present utility model is described in detail.
At first execution in step S110 with reference to figure 5, provides semi-conductive substrate 100, and described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon; Described Semiconductor substrate 100 also can be silicon, germanium, GaAs or silicon Germanium compound; This Semiconductor substrate 100 can also have epitaxial loayer or insulating barrier silicon-on; Described Semiconductor substrate 100 can also be other semi-conducting material, enumerates no longer one by one here.
In described Semiconductor substrate 100, can have the P trap, described P trap can form with those skilled in the art's method known, for example, on Semiconductor substrate 100, define the zone that forms the P trap by photoetching process earlier, carrying out ion then injects, form the P trap, the ion of injection is P type ion, for example boron ion.
Then, execution in step S120 with reference to figure 6, forms nitrogenous silicon oxide layer 102 on Semiconductor substrate 100.Silicon oxide layer 102 can be earth silicon material.Silicon oxide layer 102 utilizes the method for thermal oxide growth or deposit to produce in the present embodiment.Because this silicon oxide layer 102 plays the effect of electric insulation, and, need this silicon oxide layer 102 very thin, therefore adopt the mode of thermal oxide growth can obtain high-quality silicon oxide layer 102 along with the reducing of process.For example this step can be specially:
Clean Semiconductor substrate 100 earlier, remove the contamination and the oxide layer on surface, then Semiconductor substrate 100 is put into oxidation furnace, aerating oxygen, the silicon oxide layer 102 at the earth silicon material of one deck 6 dust to 18 dusts is given birth on Semiconductor substrate 100 surfaces between 700 degrees centigrade to 900 degrees centigrade.Preferably, in this process, can also feed nitrogen, can also introduce nitrogen-atoms simultaneously as buffer gas.
Silicon oxide layer to described growth is annealed in the atmosphere of oxygen and nitrogenous gas then.For example, stop in oxidation furnace, to feed nitrogen, the substitute is and feed nitric oxide, nitrogen dioxide or its mist.And continuation aerating oxygen, between 800 degrees centigrade to 1000 degrees centigrade of temperature, anneal, thereby in silicon oxide layer 102, introduce nitrogen-atoms, in the present embodiment, the time of annealing is 10s to 60s, concrete annealing time depends on the nitrogen atom concentration in the silica that needs form, and the time, long more nitrogen atom concentration was big more.The temperature of this step annealing is higher than the temperature of oxidation growth silicon oxide layer 102, and for example the temperature of growing silicon oxide layer 102 is 800 degrees centigrade, and then the temperature of this annealing is 900 degrees centigrade.Thereby annealing after with nitrogen atom doping in silicon oxide layer 102, promptly silicon oxide layer 102 becomes nitrogenous silicon oxide layer.And this nitrogenous silicon oxide layer 102 accounts for 10% to 30% of grid oxide layer gross thickness, for example is specially 6 to 18 dusts.
In another embodiment, nitrating can also adopt Rapid Thermal nitriding (RTN) in silicon oxide layer 102, nitriding in the stove, remote plasma nitriding (RPN) or decoupled plasma nitriding modes such as (DPN).For example specifically can adopt decoupled plasma nitriding (DPN) method, can be doped into the N ion that dosage is 2E15～6E15 at silicon oxide layer 102.
Then, execution in step S130 with reference to figure 7, forms unazotized silicon oxide layer 104 in the Semiconductor substrate 100 under described nitrogenous silicon oxide layer 102, and described nitrogenous silicon oxide layer 102 and unazotized silicon oxide layer 104 constitute grid oxide layers.Concrete, the Semiconductor substrate 100 with nitrogenous silicon oxide layer 102 can be put into oxidation furnace, aerating oxygen in oxidation furnace.Because nitrogenous silicon oxide layer is very thin, oxygen can pass the pasc reaction of the Semiconductor substrate of nitrogenous silicon oxide layer 102 and its below, growing silicon oxide layer below nitrogenous silicon oxide layer 102, in the growth course of this silicon oxide layer, owing to do not introduce nitrogen-atoms, therefore the silicon oxide layer 104 that generates is unazotized silicon oxide layer, and concrete material can be silicon dioxide.This unazotized silicon oxide layer 104 and nitrogenous silicon oxide layer 102 constitute grid oxide layer.The thickness of unazotized silicon oxide layer accounts for 70% to 90% of grid oxide layer thickness.In the present embodiment, the thickness of described grid oxide layer is 60 to 70 dusts.
Then, execution in step S140 with reference to figure 8, forms grid conductive layer 106 at grid oxide layer.The material of grid conductive layer 106 can be polysilicon.For example grid conductive layer 106 can adopt chemical vapor deposition to form, and comprises normal pressure chemical vapor deposition (APCVD), low-pressure chemical vapor phase deposition (LPCVD), plasma auxiliary chemical vapor deposition etc.Because LPCVD has good step covering power.Therefore the forming process at grid conductive layer 106 adopts LPCVD in the present embodiment.Those skilled in the art can determine the thickness that grid conductive layer 106 is required according to manufacturing process.
Then, execution in step S150, with reference to figure 9, etching grid conductive layer 106 and grid oxide layer form grid.This step can be adopted method well known to those skilled in the art, for example applies photoresist layer earlier, carries out photoetching and etching then, forms grid 108.
Then, execution in step S160 with reference to Figure 10, forms source area 110 and drain region 112 in the Semiconductor substrate 100 of grid 108 both sides.This step can be adopted method well known to those skilled in the art, the mode that for example adopts ion to inject is injected P type ion to the Semiconductor substrate with grid, boron ion for example just forms the source area 110 and the drain region 112 of high concentration in the Semiconductor substrate of grid both sides.On the side that can also be included in grid 108 before formation source area and the drain region, form side wall layer.
MOS transistor of the present utility model forms the nitrogenous silicon oxide layer 102 of one deck by the method for nitrating in the surface that grid oxide layer contacts with grid conductive layer 106, thereby can reduce the later stage ion and inject the process intermediate ion break-through that forms source area and drain region, can reduce the electric leakage of metal-oxide-semiconductor like this, improve NBTI (negative bias temperature stability).And form unazotized silicon oxide layer 104 in the surface that contacts with substrate 100 of grid oxide layer, this layer silicon oxide layer is because nonnitrogenous like this, therefore can there be the scattering of charge carrier that the nitrogen unit causes at substrate and grid oxide layer interface, therefore reduce the fluctuation of channel current under the low frequency situation, improved the stability of metal-oxide-semiconductor.
In another embodiment of the present utility model, also provide a kind of cmos image sensor, for example the pixel of this imageing sensor can be the 3T structure, as shown in figure 11, comprise the photodiode PD that is used to gather light intensity, source follower transistor SF, reset transistor RST and row gating switch transistor SEL, the plus earth of described photodiode PD, negative pole couples the source electrode of reset transistor RST, the drain electrode of reset transistor RST meets power vd D, the grid of source follower transistor SF couples the source electrode of reset transistor RST, the drain electrode of source follower transistor SF meets power vd D, the source electrode of source follower transistor SF couples the drain electrode of capable gating switch transistor SEL, and the source electrode of row gating switch transistor SEL is the output of pixel.Wherein, described source follower transistor SF is the MOS transistor in the foregoing description.The flicker noise that source follower transistor is brought in cmos image sensor has the greatest impact to figure, therefore adopt MOS transistor of the present utility model can reduce flicker noise greatly, make the flicker noise result and the grid oxide layer noise of nitrating not, for example curve S 2 is basic identical among Fig. 2.
Further, reset transistor RST in the cmos image sensor pixel and/or row gating switch transistor SEL also can also be adopted the MOS transistor in the foregoing description, further all MOS transistor in the cmos image sensor all can also be replaced with the MOS transistor in the foregoing description, make all MOS transistor can adopt identical manufacturing process like this, therefore saved technical process, also farthest reduce flicker noise, improved the accuracy of cmos image sensor.
The utility model also provides a kind of imageing sensor of pixel of the 4T of having structure, with reference to Figure 12, the plus earth of photodiode PD, negative pole couples the source electrode of transmission transistor TX, the drain electrode of transmission transistor TX couples the source electrode of reset transistor RST, the drain electrode of reset transistor RST meets power vd D, the grid of source follower transistor SF couples the source electrode of reset transistor RST, the drain electrode of source follower transistor SF meets power vd D, the source electrode of source follower transistor SF couples the drain electrode of capable gating switch transistor SEL, and the source electrode of row gating switch transistor SEL is the output of pixel.This shows, the pixel difference of the pixel of 4T structure and 3T structure is many transmission transistors TX, therefore wherein except source follower transistor SF, reset transistor RST and row gating switch transistor SEL are replaced with the above-mentioned MOS transistor, transmission transistor can also be replaced with the MOS transistor in the foregoing description.
In addition, MOS transistor of the present utility model can also be used for other imageing sensor, adopts identical principle to reduce flicker noise.
Though the utility model with preferred embodiment openly as above; but it is not to be used for limiting the utility model; any those skilled in the art are not in breaking away from spirit and scope of the present utility model; can make possible change and modification, therefore protection range of the present utility model should be as the criterion with the scope that the utility model claim is defined.
Claims (8)
1. MOS transistor comprises:
Semiconductor substrate, on described Semiconductor substrate, has grid, described grid comprises grid oxide layer and the grid conductive layer that is positioned on the grid oxide layer, in the Semiconductor substrate of described grid both sides, have source area and drain region, it is characterized in that described grid oxide layer comprises nitrogenous silicon oxide layer and the unazotized silicon oxide layer between nitrogenous silicon oxide layer and Semiconductor substrate.
2. MOS transistor as claimed in claim 1 is characterized in that, describedly contains the thickness of silicon oxynitride layer and the thickness ratio of unazotized silicon oxide layer is 1: 9 to 3: 7.
3. MOS transistor as claimed in claim 2 is characterized in that, the thickness of described grid oxide layer is 60 to 70 dusts.
4. MOS transistor as claimed in claim 2 is characterized in that, described silica is a silicon dioxide.
5. a cmos image sensor comprises the photodiode, source follower transistor, reset transistor and the row gating switch transistor that are used to gather light intensity;
It is characterized in that described source follower transistor is any described MOS transistor in the claim 1 to 4.
6. cmos image sensor according to claim 5 is characterized in that, described reset transistor is any described MOS transistor in the claim 1 to 4.
7. cmos image sensor according to claim 5 is characterized in that, described capable gating switch transistor is any described MOS transistor in the claim 1 to 4.
8. cmos image sensor according to claim 5 is characterized in that, also comprises transmission transistor, and described transmission transistor is any described MOS transistor in the claim 1 to 4.
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| CN2010205756544U CN201845782U (en) | 2010-10-19 | 2010-10-19 | Metal-oxide semiconductor (MOS) transistor and complementary metal-oxide semiconductor (CMOS) image sensor |
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| CN2010205756544U CN201845782U (en) | 2010-10-19 | 2010-10-19 | Metal-oxide semiconductor (MOS) transistor and complementary metal-oxide semiconductor (CMOS) image sensor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219348A (en) * | 2012-01-18 | 2013-07-24 | 佳能株式会社 | Photoelectric conversion apparatus, image pickup system, and method for manufacturing photoelectric conversion apparatus |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219348A (en) * | 2012-01-18 | 2013-07-24 | 佳能株式会社 | Photoelectric conversion apparatus, image pickup system, and method for manufacturing photoelectric conversion apparatus |
| US9412773B2 (en) | 2012-01-18 | 2016-08-09 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus, image pickup system, and method for manufacturing photoelectric conversion apparatus |
| CN103219348B (en) * | 2012-01-18 | 2016-08-10 | 佳能株式会社 | The manufacture method of photoelectric conversion device, image picking system and photoelectric conversion device |
| US10103186B2 (en) | 2012-01-18 | 2018-10-16 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus, image pickup system, and method for manufacturing photoelectric conversion apparatus |
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