CN102427079B - CMOS image sensor - Google Patents

Abstract

The invention discloses a CMOS image sensor. The photosensitive structure includes a PIN junction and a polysilicon gate. The PIN junction is composed of three doped regions arranged laterally, the second doped region is the I-type region of the PIN junction, the polysilicon gate is formed above the second doped region, and the polysilicon gate and the second doped region are separated by a gate oxide layer. The polysilicon gate can bend the energy band of the I-type region, thereby increasing the transfer ability of the photo-generated charges in the I-type region. When the length of the I-type region exceeds the diffusion length of photo-generated electrons or photo-generated holes, it can also make photo-generated electrons Or the photo-generated holes are effectively transferred to the N-type region or the P-type region, thereby reducing the recombination probability of the transfer of photo-generated charges during the transfer process, increasing the transfer efficiency of photo-generated charges in the photosensitive region, and increasing the length of the photosensitive region and The effective photosensitive area can improve the photoresponsivity.

Description

CMOS image sensor

technical field

The invention relates to an image sensor, in particular to a CMOS image sensor.

Background technique

Existing CMOS image sensors are composed of photosensitive pixels, that is, pixel unit circuits and CMOS circuits. Compared with CCD image sensors, CMOS image sensors have better integration because they use CMOS standard manufacturing processes, and can be integrated with other digital-analog operations and control The circuit is integrated on the same chip, which is more suitable for future development.

According to the number of transistors contained in the pixel unit circuit of the existing CMOS image sensor, it is mainly divided into 3T structure and 4T structure. A pixel unit circuit of an existing CMOS image sensor includes a photosensitive structure and a CMOS pixel readout circuit. For a 3T structure, the CMOS pixel readout circuit is a 3T pixel circuit, including a reset transistor, an amplifier transistor, and a selection transistor, and the photosensitive structure is locally interconnected with the reset transistor and the amplifier transistor. For the 4T type structure, the CMOS pixel readout circuit is a 4T type pixel circuit, including a reset transistor, an amplifier transistor, a selection transistor and a transfer transistor, and the photosensitive structure is locally interconnected with the transfer transistor.

The photosensitive structure of an existing CMOS image sensor is generally a photodiode, and the existing photodiode is generally formed in a bulk silicon material, and the P-type region and the N-type region of the photodiode are a vertical structure.

However, in some fields, stronger anti-interference ability is required, so that the photosensitive diode needs to be formed on a silicon substrate (SOI) material with a buried insulating layer, and the SOI material includes a top layer of silicon from top to bottom. , insulating layer, supporting silicon. The reason is that the buried insulating layer is generally a buried oxide layer, which can eliminate the common latch-up effect in the bulk silicon CMOS structure, suppress substrate current interference, and provide a stronger isolation effect.

When fabricating a CMOS image sensor on an SOI material, because the top silicon layer of the SOI material is too thin, the existing vertical photodiode process cannot obtain a sufficient depletion region in the vertical direction. Therefore, the existing photosensitive structure usually adopts a horizontal PIN structure.

As shown in Figure 1, it is a schematic structural diagram of an existing 3T type SOI CMOS image sensor. The existing 3T type SOI CMOS image sensor includes:

The SOI material includes, from top to bottom, a top layer of silicon, an insulating layer 102 , and a supporting substrate, that is, a silicon substrate 101 .

The PIN junction is composed of three doped regions arranged laterally, the second doped region 104 is the I-type region of the PIN junction; the first doped region 103 is a P-type region, located in the second doped region 104 One side of the first doped region 103 and the second doped region 104 are in contact with each other; the third doped region 105 is an N-type region located on the other side of the second doped region 104, the The third doped region 105 is in contact with the second doped region 104 .

The 3T CMOS pixel readout circuit includes a reset transistor 106 , an amplifier transistor 107 , and a selection transistor 108 , and the PIN junction is locally interconnected with the reset transistor 106 and the amplifier transistor 107 .

The first doped region 103 and the third doped region 105 are doped with a high concentration, the second doped region 104 is doped with a low concentration, and the second doped region 104 is completely depleted, being photosensitive area. When light shines on the second doped region 102, the generated electron-hole pairs are respectively transferred to the third doped region 105 and the first doped region 103, and finally read out by the CMOS pixel readout circuit.

The existing CMOS image sensor technology including the horizontal PIN structure as shown in FIG. 1 has the following disadvantages:

Limited by the carrier diffusion length of the I-type region, that is, the second doped region 104, the holes generated near the N-type region, that is, the third doped region 105, are transferred to the P-type region, that is, the first doped region. 103 is easily recombined by electrons transferred to the N-type region. Therefore, when the length of the I-type region exceeds the diffusion length, increasing the length of the I-type region cannot improve the photoresponsivity, thus limiting the effective photosensitive area of the photosensitive region.

Contents of the invention

The technical problem to be solved by the present invention is to provide a CMOS image sensor that can increase the transfer efficiency of photogenerated charges in the photosensitive region, thereby increasing the length and effective photosensitive area of the photosensitive region and improving the photoresponsive rate.

In order to solve the above technical problems, the CMOS image sensor provided by the present invention is formed on a semiconductor substrate. The pixel unit circuit of the CMOS image sensor includes a photosensitive structure and a CMOS pixel readout circuit; the photosensitive structure includes a PIN junction and a polysilicon gate.

The PIN junction is composed of three doped regions arranged laterally, the second doped region is the I-type region of the PIN junction; the first doped region is a P-type region, located in one of the second doped regions side, the first doped region and the second doped region are contacted and connected; the third doped region is an N-type region located on the other side of the second doped region, and the third doped region contacting and connecting with the second doped region;

The polysilicon gate is formed above the second doped region, and a gate oxide layer is used to isolate the polysilicon gate from the second doped region.

A further improvement is that the polysilicon gate is N-type doped, or the polysilicon gate is P-type doped.

A further improvement is that the P-type impurity concentration of the first doped region is 1E17CM ^-3 ~ 1E21CM ^-3 , and the N-type impurity concentration of the third doped region is 1E17CM ^-3 ~ 1E21CM ^-3 .

A further improvement is that the second doped region is P-type doped with a concentration of 1E10CM ^-3 to 1E16CM ^-3 , which is lower than the doping concentration of the first and third doped regions; or, the second doped region The second doping region is N-type doped with a concentration of 1E10CM ^-3 to 1E16CM ^-3 , which is lower than the doping concentration of the first and third doping regions.

A further improvement is that the CMOS pixel readout circuit is a 3T pixel circuit, including a reset transistor, an amplifier transistor, and a selection transistor, and the photosensitive structure is locally interconnected with the reset transistor and the amplifier transistor.

A further improvement is that the CMOS pixel readout circuit is a 4T pixel circuit, including a reset transistor, an amplifier transistor, a selection transistor and a transfer transistor, and the photosensitive structure is locally interconnected with the transfer transistor.

A further improvement is that the silicon material is a silicon substrate with an insulating buried layer, and the silicon substrate with an insulating buried layer includes a top layer of silicon, an insulating layer, and a supporting substrate from top to bottom; the CMOS image Sensors are formed on the top silicon.

A further improvement is that the CMOS image sensor is a back-illuminated structure.

The photosensitive structure of the CMOS image sensor of the present invention adopts a horizontal PIN junction, which enables the CMOS image sensor of the present invention to be formed on the top layer silicon of the SOI material, thereby enabling the CMOS image sensor of the present invention to have strong anti-interference ability.

The photosensitive structure of the present invention also includes a polysilicon gate formed on the I-type region of the PIN junction. The I-type region is the photosensitive region, and the polysilicon gate can bend the energy band of the I-type region, thereby increasing the transfer ability of the photo-generated charge in the I-type region. When the length of the I-type region exceeds the diffusion length of photo-generated electrons or photo-generated holes At the same time, the photogenerated electrons or photogenerated holes can also be effectively transferred to the N-type region or the P-type region, thereby reducing the recombination probability of the photogenerated charge transfer during the transfer process, and can increase the transfer efficiency of the photogenerated charge in the photosensitive region. The length of the photosensitive area and the effective photosensitive area can be increased, and the photoresponsive rate can be improved.

The CMOS image sensor of the present invention adopts a back-illuminated structure, that is, adopts back-illuminated lighting. Since the polysilicon gate is formed on the front of the CMOS image sensor, the CMOS image sensor of the present invention improves photon absorption efficiency.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

Fig. 1 is a structural schematic diagram of an existing 3T type SOI CMOS image sensor;

2 is a schematic structural diagram of a CMOS image sensor according to an embodiment of the present invention;

3-7 are structural schematic diagrams in each step of the manufacturing method of the CMOS image sensor according to the embodiment of the present invention.

Detailed ways

FIG. 2 is a schematic structural diagram of a CMOS image sensor according to an embodiment of the present invention. In the embodiment of the present invention, the CMOS image sensor is formed on the top layer silicon 03 of a silicon substrate (SOI) with an insulating buried layer, and the silicon substrate with an insulating buried layer includes the top layer silicon 03, insulating layer from top to bottom. Layer 02, the supporting substrate, that is, the silicon substrate 01.

The pixel unit circuit of the CMOS image sensor includes a photosensitive structure and a CMOS pixel readout circuit; the photosensitive structure includes a PIN junction and a polysilicon gate 07 .

The PIN junction is composed of three doped regions arranged laterally.

The second doped region 06 is an I-type region of the PIN junction. The second doped region is P-type doped with a concentration of 1E10CM ^-3 to 1E16CM ^-3 ; or, the second doped region is N-type doped with a concentration of 1E10CM ^-3 to 1E16CM ^-3 .

The first doped region 04 is a P-type region, located on one side of the second doped region 06 , and the first doped region 04 and the second doped region 06 are connected in contact. The P-type impurity concentration of the first doped region 04 is 1E17CM ⁻³ to 1E21CM ⁻³ .

The third doped region 05 is an N-type region located on the other side of the second doped region 06 , and the third doped region 05 and the second doped region 06 are connected in contact. The N-type impurity concentration of the third doped region 05 is 1E17CM ⁻³ to 1E21CM ⁻³ . Of course, the positions of the first doped region 04 and the third doped region 05 can be interchanged.

From the doping concentration of the first doping region 04, the third doping region 05 and the second doping region 06, it can be seen that the doping concentration of the second doping region 06 is low and will be completely depleted, the second doped region 06 is a photosensitive region. The CMOS image sensor is a back-illuminated structure, and light is incident from the back of the second doped region 06 , that is, from the direction from the insulating layer 02 to the second doped region 06 .

The polysilicon gate 07 is formed above the second doped region 06 , and a gate oxide layer is isolated between the polysilicon gate 07 and the second doped region 06 . The polysilicon gate 07 is N-type doped, or the polysilicon gate is P-type doped.

The CMOS pixel readout circuit is a 3T pixel circuit, including a reset transistor 08 , an amplifier transistor 09 , and a selection transistor 10 . The photosensitive structure is locally interconnected with the reset transistor 08 and the amplifier transistor 09 . Of course, the CMOS pixel readout circuit can also be a 4T pixel circuit.

As shown in FIG. 3 to FIG. 7 , they are structural schematic diagrams in each step of the manufacturing method of the CMOS image sensor according to the embodiment of the present invention. The manufacturing method of the CMOS image sensor in the embodiment of the present invention includes the following steps:

As shown in FIG. 3 , an SOI substrate is prepared, and the SOI substrate includes the top layer of silicon 03 , an insulating layer 02 , and a supporting substrate that is a silicon substrate 01 from top to bottom.

Three laterally aligned doped regions forming a PIN junction. Including the following sub-steps:

As shown in Figure 4, a P-type ion implantation process or diffusion process is performed at the position of the P-type region where the PIN junction needs to be formed to form the first doped region 04, and the P-type impurity concentration of the first doped region 04 is ^{1E17CM- 3} ~ 1E21CM ^-3 .

As shown in FIG. 5, an N-type ion implantation process or a diffusion process is performed at the position of the N-type region where the PIN junction needs to be formed to form a third doped region 05, and the N-type impurity concentration of the third doped region 05 is ^{1E17CM- 3} ~ 1E21CM ^-3 . Of course, the positions of the first doped region 04 and the third doped region 05 are interchangeable.

As shown in FIG. 6 , an ion implantation process or a diffusion process is performed at the position where the I-type region of the PIN junction needs to be formed to form the second doped region 06 . The second doped region 06 is located between the first doped region 04 and the third doped region 05 and is in contact with the first doped region 04 and the third doped region 05 respectively. The impurity ion-implanted into the second doped region 06 is P-type, and the doping concentration is 1E10CM ^-3 ~ 1E16CM ^-3 ; or, the impurity ion-implanted into the second doped region 06 is N-type, and doped The concentration is 1E10CM ^-3 ~ 1E16CM ^-3 .

As shown in FIG. 7, a polysilicon gate 07 is formed. The polysilicon gate 07 is located above the second doped region 06, and a gate oxide layer is isolated between the polysilicon gate 07 and the second doped region 06; the PIN junction and the polysilicon gate 07 form a photosensitive structure.

As shown in FIG. 2, a CMOS pixel readout circuit is formed. After the photosensitive structure is formed, the top layer silicon 03 around the photosensitive structure is first etched away, and then the CMOS pixel readout circuit is fabricated in the top layer silicon 03 in the region of the CMOS pixel readout circuit, In FIG. 2 , the CMOS pixel readout circuit is a 3T pixel circuit, including a reset transistor 08 , an amplifier transistor 09 , and a selection transistor 10 . Of course, the CMOS pixel readout circuit can also be a 4T pixel circuit.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (7)

1. a cmos image sensor, be formed on Semiconductor substrate, it is characterized in that: the pixel unit circuit of cmos image sensor comprises photosensitive structure, cmos pixel reading circuit; Described photosensitive structure comprises PIN knot and a polysilicon gate;

Described PIN knot is comprised of three transversely arranged doped regions, the I type district that the second doped region is described PIN knot; The first doped region is p type island region, be positioned at a side of described the second doped region, described the first doped region and described the second doped region contact are connected; The 3rd doped region WeiNXing district, the opposite side that is positioned at described the second doped region, described the 3rd doped region and described the second doped region contact are connected;

Described polysilicon gate is formed at isolation between described the second doped region top and described polysilicon gate and described the second doped region gate oxide;

Described Semiconductor substrate is the silicon substrate with insulating buried layer, and the described silicon substrate with insulating buried layer comprises top layer silicon, insulating barrier, support substrates from top to bottom; Described cmos image sensor is formed on described top layer silicon.

2. cmos image sensor as claimed in claim 1 is characterized in that: described polysilicon gate is that N-type doping or described polysilicon gate are the doping of P type.

3. cmos image sensor as claimed in claim 1 is characterized in that: described the second doped region is the doping of P type, and its doping content is less than described the first, the 3rd doped region doping content.

4. cmos image sensor as claimed in claim 1 is characterized in that: described the second doped region is that N-type doping and its doping content are less than described the first, the 3rd doped region doping content.

5. cmos image sensor as claimed in claim 1, it is characterized in that: described cmos pixel reading circuit is 3T type image element circuit, comprises reset transistor, amplifier tube, selection pipe, described photosensitive structure and described reset transistor and amplifier tube Interconnected.

6. cmos image sensor as claimed in claim 1, it is characterized in that: described cmos pixel reading circuit is 4T type image element circuit, comprises reset transistor, amplifier tube, selection pipe and transfer pipeline, described photosensitive structure and described transfer pipeline Interconnected.

7. cmos image sensor as claimed in claim 1, it is characterized in that: described cmos image sensor is the back-illuminated type structure.

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