CN201844765U - Time-delay exploder - Google Patents
Time-delay exploder Download PDFInfo
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- CN201844765U CN201844765U CN201020591323XU CN201020591323U CN201844765U CN 201844765 U CN201844765 U CN 201844765U CN 201020591323X U CN201020591323X U CN 201020591323XU CN 201020591323 U CN201020591323 U CN 201020591323U CN 201844765 U CN201844765 U CN 201844765U
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Abstract
The embodiment of the utility model provides a time delay exploder, including time base oscillation frequency division circuit, on-off state latch circuit, two central processing unit detection control circuit, multichannel signal control auto-power-off circuit, battery voltage comparison circuit, high-pressure comparison circuit, contravariant boost circuit, high-pressure charge-discharge circuit, energy storage element residual capacity bleeder circuit and self-checking circuit, time base oscillation frequency division circuit produces the time base pulse and supplies two central processing unit detection control circuit measure the oscillation cycle in step; the double-CPU detection control circuit synchronously measures the timing counting time-base pulse from the time-base oscillation frequency division circuit, and the mutual test measurement result is realized through the butt joint of two port lines. The delayed detonator has two functions of delayed automatic initiation and instant automatic initiation, can greatly reduce the using amount of the initiation detonating tube, and provides enough safe evacuation time for instrument operators.
Description
Technical field
The utility model relates to Geotechnical Engineering explosion field, relates in particular to a kind of delay initiator.
Background technology
At present, in mining and other Geotechnical Engineering blasting process, generally need to adopt blasting cap initiation, the method for ignition can adopt blasting cap method, electric detonator initiation method and the detonator method etc. of detonating of detonating.On July 1st, 2008 played blasting cap and bans use of in China, and the range of application that detonator is detonated is more extensive.
Detonator in the prior art scheme excites equipment mostly to be high-voltage capacitance formula initiator, and the initiator of each manufacturer production all is used for manually detonating at a distance, so makes to lay the line longlyer, and the cost that detonates is higher.
Summary of the invention
The utility model embodiment provides a kind of delay initiator, have time-delay self-cocking action and instant two kinds of functions of self-cocking action, can significantly reduce the use amount of the detonator that detonates, and need be near under the condition at explosion scene, for the instrumentation personnel provide the enough safe escape time at initiator.
The utility model embodiment provides a kind of delay initiator, comprise described delay initiator time-base oscillation frequency dividing circuit, on off state latch cicuit, two CPU detect control circuit, multiple signals control automatic shutdown circuitry, cell voltage comparison circuit, high pressure comparison circuit, inversion step-up circuit, high pressure charge-discharge circuit, energy-storage travelling wave tube remaining capacity leadage circuit and self-checking circuit, wherein:
Main pulse swung the cycle for the vibration measuring of described pair of CPU detection control circuit synchronometer when described time-base oscillation frequency dividing circuit produced;
The described pair of CPU detect control circuit synchronously to from the timer counter of described time-base oscillation frequency dividing circuit the time main pulse carry out instrumentation, and realize testing the instrumentation result mutually by two mouth lines butt joints, the time-delay of detonating accurately is provided.
By the on off operating mode of the described inversion step-up circuit of three tunnel signal controlling, and utilize described pair of CPU to detect control circuit on off operating mode is carried out the short period detection, prevent the logical potential safety hazard that causes of misconnection of described inversion step-up circuit.
Described time-base oscillation frequency dividing circuit produces the signal of two-way different frequency, one the tunnel supplies described pair of CPU to detect control circuit detects, relatively also counts, and another road supplies this pair CPU to detect the power supply that control circuit detects, relatively also described inversion step-up circuit is controlled in participation.
Described on off state latch cicuit produces the two-way output signal, and one the tunnel is that switch state signal detects, compares for described pair of CPU detection control circuit; Control circuit detects, relatively also conduct enables control for the on off state latch signal detects for described pair of CPU on another road.
Described multiple signals control automatic shutdown circuitry comprises the gate circuit sum counter, wherein:
When described pair of CPU detection control circuit normally moved, described multiple signals control automatic shutdown circuitry output active off signal was to cut off the complete machine power supply;
When described pair of CPU detection control circuit broke down, information exchange can not normally be carried out, and causes described counter not reset as scheduled, and count pulse makes the upset of output level to realize shutdown.
Described high pressure charge-discharge circuit detects described pair of CPU under the control of control circuit, and the change-over switch state is connected the charge or discharge loop to finish the charge and discharge process in good time.
The working power of described inversion step-up circuit is subjected to described pair of CPU to detect control circuit and enables the common control of level;
Behind power connection, produce the alternation high pressure by oscillator, transistor and step-up transformer and after rectification, charge to energy-storage travelling wave tube.
Described energy-storage travelling wave tube remaining capacity leadage circuit comprises energy-storage travelling wave tube, discharge resistance and the switch of releasing, wherein:
After electrion finished, described energy-storage travelling wave tube of the described switch connection of releasing and described discharge resistance formed the loop, and the remaining capacity in the described energy-storage travelling wave tube is released by described discharge resistance.
Described self-checking circuit comprises cell voltage comparison circuit, charge and discharge switch on off operating mode testing circuit and the energy-storage travelling wave tube remaining capacity testing circuit of releasing; Wherein:
Before the operation start that detonates, described pair of CPU detects control circuit described self-checking circuit output level state detected, judges to do the processing operation of shutdown or continuation performing a programme.
By the above-mentioned technical scheme that provides as can be seen, comprise described delay initiator time-base oscillation frequency dividing circuit, on off state latch cicuit, two CPU detect control circuit, multiple signals control automatic shutdown circuitry, cell voltage comparison circuit, high pressure comparison circuit, inversion step-up circuit, high pressure charge-discharge circuit, energy-storage travelling wave tube remaining capacity leadage circuit and self-checking circuit, and wherein: main pulse swung the cycle for the vibration measuring of described pair of CPU detection control circuit synchronometer when described time-base oscillation frequency dividing circuit produced; The described pair of CPU detect control circuit synchronously to from the timer counter of described time-base oscillation frequency dividing circuit the time main pulse carry out instrumentation, and realize testing the instrumentation result mutually by two mouth lines butt joints, the time-delay of detonating accurately is provided.This delay initiator has time-delay self-cocking action and instant two kinds of functions of self-cocking action, can significantly reduce the use amount of the detonator that detonates, and needs near under the condition at explosion scene, for the instrumentation personnel provide the enough safe escape time at initiator.
Description of drawings
Fig. 1 provides the overall structure schematic diagram of delay initiator for the utility model embodiment;
The time-base oscillation frequency dividing circuit schematic diagram that Fig. 2 provides for the utility model embodiment;
The on off state latch cicuit schematic diagram that Fig. 3 provides for the utility model embodiment;
Fig. 4 detects the control circuit schematic diagram for two CPU that the utility model embodiment provides;
The relay drive circuit schematic diagram that Fig. 5 provides for the utility model embodiment;
The inversion step-up circuit schematic diagram that Fig. 6 provides for the utility model embodiment;
The high pressure charge-discharge circuit schematic diagram that Fig. 7 provides for the utility model embodiment;
The cell voltage comparison circuit schematic diagram that Fig. 8 provides for the utility model embodiment;
The window comparator circuit schematic diagram that Fig. 9 provides for the utility model embodiment;
The multiple signals control shutdown circuit schematic diagram that Figure 10 provides for the utility model embodiment.
The specific embodiment
The utility model embodiment provides a kind of delay initiator, have time-delay self-cocking action and instant two kinds of functions of self-cocking action, can significantly reduce the use amount of the detonator that detonates, and need be near under the condition at explosion scene, for the instrumentation personnel provide the enough safe escape time at initiator.
For better describing the utility model embodiment, now in conjunction with the accompanying drawings the specific embodiment of the present utility model is described, Fig. 1 provides the overall structure schematic diagram of delay initiator for the utility model embodiment, delay initiator comprises among the figure: time-base oscillation frequency dividing circuit, on off state latch cicuit, two CPU detect control circuit, multiple signals control automatic shutdown circuitry, cell voltage comparison circuit, high pressure comparison circuit, inversion step-up circuit, high pressure charge-discharge circuit, energy-storage travelling wave tube remaining capacity leadage circuit and self-checking circuit, wherein:
Main pulse swung the cycle for the vibration measuring of described pair of CPU detection control circuit synchronometer when described time-base oscillation frequency dividing circuit produced.This time-base oscillation frequency dividing circuit produces the signal of two-way different frequency, one the tunnel supplies described pair of CPU to detect control circuit detects, relatively also counts, and another road supplies this pair CPU to detect the power supply that control circuit detects, relatively also described inversion step-up circuit is controlled in participation.
Described on off state latch cicuit for the described pair of CPU detects that control circuit provides immediately, delay function selector switch state so that program carry out by selected function; The level state that described cell voltage comparison circuit is exported is detected synchronously by described pair of CPU detection control circuit and judges with the do continuation and carry out detonate operation or shutdown processing; The level state of described high pressure comparison circuit output detects control circuit detection synchronously by described pair of CPU and judges and indicate for charged state; Described inversion step-up circuit obtains working power and charges to energy-storage travelling wave tube under the common control of correct level that enables level and the output of described pair of CPU detection control circuit that described time-base oscillation frequency dividing circuit produces; Thereby described high pressure charge-discharge circuit connection charge or discharge switch under the common control of level that enables level and the output of described pair of CPU detection control circuit of described time-base oscillation frequency dividing circuit generation is finished charge or discharge and is operated; Thereby described energy-storage travelling wave tube remaining capacity leadage circuit is connected discharge switch realization remaining capacity and is released under the level control of described pair of CPU detection control circuit output.
In the specific implementation process, this time-base oscillation frequency dividing circuit is made up of the counter of active crystal oscillator and multi-disc cascade, be illustrated in figure 2 as time-base oscillation frequency dividing circuit schematic diagram, among Fig. 2: active crystal oscillator produces the rectilinear oscillation pulse, its output links to each other with the counter clock end, the recurrent pulse of gained is introduced the port bit line of the same name of two CPU behind the multistage frequency division, detect, relatively and counting for CPU as time base, its porch is carried out simultaneously operating for two CPU.Continue frequency division and produce the pulse period that adapts with the time-delay of detonating, this output signal participates in control inversion boosting power supply relay, before the low level of half period do not allow to connect the inversion step-up circuit power supply, only level that could be by CPU output between the high period in later half cycle is via driving relay with door; RST1 connects electrify restoration circuit in the circuit, and RST2 connects the reversed-phase output of the trigger of the starting switch circuit that detonates.
Above-mentioned on off state latch cicuit produces the two-way output signal, and one the tunnel is that switch state signal detects, compares for described pair of CPU detection control circuit; Control circuit detects, relatively also conduct enables control for the on off state latch signal detects for described pair of CPU on another road.In the specific implementation process, the on off state latch cicuit as shown in Figure 3, among Fig. 3: switch double-duty comprises the functional select switch and detonate and start to confirm switch of detonating immediately; The output of phase inverter is detected by CPU in the enough time that switch is pressed.If select to detonate immediately function, the time of then pressing this switch needs the several seconds, and purpose is to prevent from arbitrarily to detonate immediately to guarantee safety; Trigger upset and latch output level during Push switch, its Q end output is used separately as control inversion boosting power supply and enable counter shutdown function.
The above-mentioned pair of CPU detect control circuit synchronously to from the timer counter of described time-base oscillation frequency dividing circuit the time main pulse carry out instrumentation, and realize testing the instrumentation result mutually by two mouth lines butt joints, the time-delay of detonating accurately is provided.In the specific implementation process, the structure that this pair CPU detects control circuit as shown in Figure 4: to arbitrary input signal, two CPU detect simultaneously; The input signal that detects comprise self-test signal, the time main pulse, the detonate Status Flag of functional switch state, the starting switch state that detonates, inversion boosting power supply, inversion boosting power enable signal (the 11st pin of U12D among Fig. 2), high tension voltage and the output of another CPU immediately.The signal of output is controlled self check relay, inversion boosting power supply relay, high pressure respectively and is discharged and recharged relay, storage capacitor remaining capacity release relay, status indicator lamp and shutdown circuit and as the Status Flag that is detected by another CPU, and the relay drive circuit that the utility model adopted as shown in Figure 5.
In addition, during specific implementation, by the on off operating mode of the described inversion step-up circuit of three tunnel signal controlling, and utilize described pair of CPU to detect control circuit on off operating mode is carried out the short period detection, prevent the logical potential safety hazard that causes of misconnection of described inversion step-up circuit.In case this kind situation occurs, CPU is controlled power supply relay immediately and cut off the complete machine power supply, and is wrong even a certain CPU detects, and another CPU also can be carried out shutdown in case quick-fried phenomenon early takes place.
Above-mentioned high pressure charge-discharge circuit detects described pair of CPU under the control of control circuit, and the change-over switch state is connected the charge or discharge loop to finish the charge and discharge process in good time.In the specific implementation process, the structural representation of this high pressure charge-discharge circuit as shown in Figure 7, among the figure: JCF is expressed as the common port that discharges and recharges relay and Chang Kai, normally-closed contact, JXF is expressed as energy-storage capacitor remaining capacity the release common port of relay and Chang Kai, normally-closed contact, and resistance VR1, VR35 and R21 do discharge and the self check dividing potential drop is used.The JCF normally-closed contact is in the connection attitude during charging, and the JXF normally-closed contact is in off-state, and high pressure charges to storage capacitor CHV from the HV end; The JCF normally opened contact is connected when detonating, and energy-storage capacitor inner high voltage energy produces electric spark from igniter head T abrupt release, and the JXF normally-closed contact is connected remaining capacity in the vent discharge container then.Diode D6 plays clamping action among the figure, prevents that the branch pressure voltage of capacitor inner high voltage from damaging its detecting element.
The working power of above-mentioned inversion step-up circuit is subjected to described pair of CPU to detect control circuit and enables the common control of level; Behind power connection, produce the alternation high pressure by oscillator, transistor and step-up transformer and after rectification, charge to energy-storage travelling wave tube.In the specific implementation process, by CPU the time main pulse of time-base oscillation frequency dividing circuit output is counted, when count value reached the setting value that adapts with time-delay, its output level and inversion boosting power enable level provided power supply by driving relay with door for inversion step-up circuit.The structural representation of this inversion step-up circuit as shown in Figure 6, wherein: oscillating circuit is made up of resistance, electric capacity and phase inverter, energising back phase inverter U13F and U13E export anti-phase square wave, control the break-make of dc source as switch element with FET, make DC voltage alternately be added to the elementary of transformer B, thus can be at the secondary alternating voltage that obtains of transformer B; Through diode VD1, VD2 and capacitor VC1, VC2 rectifying and wave-filtering output high direct voltage, thereby charge to obtain enough energy for storage capacitor CHV; Before the discharge, cut off the power supply of inversion step-up circuit.
In addition, above-mentioned cell voltage comparison circuit as shown in Figure 8, among the figure: for the cell voltage comparison circuit, reference voltage connects the operational amplifier in-phase input end, cell voltage inserts inverting input behind electric resistance partial pressure, when cell voltage is not enough, and operational amplifier output high level; This signal is detected by CPU behind electrification reset.When detecting storage capacitor two ends high voltage, reference voltage connects inverting input, and high pressure inserts in-phase input end behind electric resistance partial pressure, surpasses setting value as high pressure, then exports high level, and is luminous by the central processing unit controls indicator lamp.
Above-mentioned energy-storage travelling wave tube remaining capacity leadage circuit comprises energy-storage travelling wave tube, discharge resistance and the switch of releasing, wherein: after electrion finishes, described energy-storage travelling wave tube of the described switch connection of releasing and described discharge resistance form the loop, and the remaining capacity in the described energy-storage travelling wave tube is released by described discharge resistance.
In addition, above-mentioned self-checking circuit comprises cell voltage comparison circuit, charge and discharge switch on off operating mode testing circuit and the energy-storage travelling wave tube remaining capacity testing circuit of releasing; Wherein before the operation start that detonates, described pair of CPU detects control circuit described self-checking circuit output level state detected, judges to do the processing operation of shutdown or continuation performing a programme.In the specific implementation process, when detection discharges and recharges relay, adopted the window comparator circuit of forming by two level comparison circuit, as shown in Figure 9, above-mentioned Fig. 9 and Fig. 7 just form this self-checking circuit.Wherein: between the upper and lower limit reference voltage, then the comparator output low level shows that detected loop state is normal as if tested voltage; Otherwise comparator output high level shows that tested loop breaks down, and instrument is difficult to reliably to carry out high pressure and discharges and recharges operation.The upper limit value and lower limit value of reference voltage be according to discharge and recharge relay J CF normally-closed contact when closed VR1 and VR35 in parallel use and normally opened contact when closed VR1 do not insert and detect the loop and determine by the obtained different magnitudes of voltage of R21 dividing potential drop.
All locate closure state between two line end points of JGL between detection period and JXF two relays, the selection of JJC and JCF relay closes contact should guarantee that when detecting circuit place closure state is beneficial to detect respectively that JCF often opens, the closed situation of normally-closed contact.When discharging and recharging relay J CF normally-closed contact can not be closed the time, because of VR35 fails to insert the loop tested voltage is reduced, and make comparator output high level; If normally opened contact can not be closed, then VR1 and VR35 all can not insert the loop and make the detection loop be in off-state, and tested voltage is lower than the lower limit a reference value and exports high level.
In addition, above-mentioned multiple signals control automatic shutdown circuitry comprises the gate circuit sum counter, wherein: when described pair of CPU detection control circuit normally moved, described multiple signals control automatic shutdown circuitry output active off signal was to cut off the complete machine power supply; When described pair of CPU detection control circuit broke down, information exchange can not normally be carried out, and causes described counter not reset as scheduled, and count pulse makes the upset of output level to realize shutdown.In the specific implementation process, the structural representation of this multiple signals control automatic shutdown circuitry as shown in figure 10, among the figure: the complete machine on/off is controlled by relay, start needs the operation hand switch, power-off operation is automatically performed by programme-control under normal condition, but also can execute by hand switch at any time.
When system's operate as normal, CPU1 that two CPU are exported respectively and CPU2 signal all keep low level, the CLK pin of counter U7B and U11B is the input of timer counter clock, its reset terminal MR alternately makes counter Q2 end always be in low level state under the control at the high-low level of CPU output, four tunnel low levels are passed through or door, behind the door non-, and its high level drives relay gets complete machine.When normally shutting down automatically, CPU makes CPU1 and CPU2 end be high level; If when faults such as CPU appearance deadlock can not replace reset counter by U1-U2, the U2-U1 end pulse of Fig. 4, then counter turn-offed relay with cut-out complete machine power supply to clock pulse count until one of them Q2 end output high level.The detonate Q end output of starting switch circuit triggers device of RSTC termination, RSTC was for low before starting switch was pressed
Below based on the formation of the described circuit of the foregoing description, the course of work of this delay initiator is elaborated:
At first, under the normal condition, when circuitry did not obtain power supply, storage capacitor remaining capacity bleed-off circuit was connected by the normally-closed contact of relay J CF and JXF, do not have high pressure, thereby discharge end is safe.Manually after the start, the power supply relay adhesive, the electrification reset system resets circuit system, then CPU is carried out self check by preset program, content comprises cell voltage, inversion boosting power supply relay state, charge and discharge switch, the remaining capacity element of releasing, and therefore directly influence safe, the reliable execution of operation of detonating of these factors as long as have a testing result undesired, instrument is shutdown automatically all, but according to state indication situation failure judgement reason.
After self check finishes, CPU touring detection in certain time-delay detonate the immediately functional select switch and the starting switch state that detonates, as detonating immediately, then need manually to press the functional select switch several seconds of detonating immediately earlier, press starting switch more within a certain period of time, CPU is promptly carried out the auto charge and discharge program; Detonate if delay time, then only need to press within a certain period of time starting switch, CPU promptly to carry out and count up to predetermined time-delay, finish auto charge and discharge operation and shutdown afterwards.Fail Push switch in certain time-delay, instrument shuts down automatically, and purpose is in order to reduce unnecessary battery power consumption.
Simultaneously, CPU is carried out instrumentation to counting the time-base oscillation cycle in time-delay counting process, and in time transmits the testing result sign between two CPU and carry out mutual verification to guarantee time-delay accurately, avoids quick-fried by mistake.CPU also periodically detects inversion boosting power supply relay state and inversion step-up circuit power enable level, avoids producing height and holds up charge-carrying belt and come potential safety hazard, in case occur unusually, instrument is shutdown automatically at once.
When time-delay finished or detonate the operation beginning immediately, Fig. 7 repeat circuit JGL and JXF got electric, cut off normally-closed contact; Then inversion step-up circuit gets electricly, and the high pressure of generation charges to capacitor CHV through the JCF normally-closed contact; Relay JCF gets electric disconnection charge circuit after several seconds, connects discharge loop, and igniter head electrion produces electric spark; Relay J XF dead electricity is to connect the normally-closed contact remaining capacity in the CHV of releasing afterwards; After a charge and discharge process is finished, instrument will cut off the complete machine power supply automatically.
In sum, this delay initiator has time-delay self-cocking action and instant two kinds of functions of self-cocking action, can significantly reduce the use amount of the detonator that detonates, and need near under the condition at explosion scene, for the instrumentation personnel provide the enough safe escape time at initiator; Control under the situation of detonating at nobody simultaneously, the operation of detonating is finished after correct time-delay automatically by instrument, has high reliability.
The above; it only is the preferable specific embodiment of the utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of claims.
Claims (9)
1. delay initiator, it is characterized in that, comprise described delay initiator time-base oscillation frequency dividing circuit, on off state latch cicuit, two CPU detect control circuit, multiple signals control automatic shutdown circuitry, cell voltage comparison circuit, high pressure comparison circuit, inversion step-up circuit, high pressure charge-discharge circuit, energy-storage travelling wave tube remaining capacity leadage circuit and self-checking circuit, wherein:
Main pulse swung the cycle for the vibration measuring of described pair of CPU detection control circuit synchronometer when described time-base oscillation frequency dividing circuit produced;
The described pair of CPU detect control circuit synchronously to from the timer counter of described time-base oscillation frequency dividing circuit the time main pulse carry out instrumentation, and realize testing the instrumentation result mutually by two mouth lines butt joints, the time-delay of detonating accurately is provided.
2. delay initiator as claimed in claim 1, it is characterized in that, on off operating mode by the described inversion step-up circuit of three tunnel signal controlling, and utilize described pair of CPU to detect control circuit on off operating mode is carried out the short period detection, prevent the logical potential safety hazard that causes of misconnection of described inversion step-up circuit.
3. delay initiator as claimed in claim 1, it is characterized in that, described time-base oscillation frequency dividing circuit produces the signal of two-way different frequency, one the tunnel supplies described pair of CPU to detect control circuit detects, relatively also counts, and another road supplies this pair CPU to detect the power supply that control circuit detects, relatively also described inversion step-up circuit is controlled in participation.
4. delay initiator as claimed in claim 1 is characterized in that, described on off state latch cicuit produces the two-way output signal, and one the tunnel is that switch state signal detects, compares for described pair of CPU detection control circuit; Control circuit detects, relatively also conduct enables control for the on off state latch signal detects for described pair of CPU on another road.
5. delay initiator as claimed in claim 1 is characterized in that, described multiple signals control automatic shutdown circuitry comprises the gate circuit sum counter, wherein:
When described pair of CPU detection control circuit normally moved, described multiple signals control automatic shutdown circuitry output active off signal was to cut off the complete machine power supply;
When described pair of CPU detection control circuit broke down, information exchange can not normally be carried out, and causes described counter not reset as scheduled, and count pulse makes the upset of output level to realize shutdown.
6. delay initiator as claimed in claim 1 is characterized in that, described high pressure charge-discharge circuit detects described pair of CPU under the control of control circuit, and the change-over switch state is connected the charge or discharge loop to finish the charge and discharge process in good time.
7. delay initiator as claimed in claim 1 is characterized in that, the working power of described inversion step-up circuit is subjected to described pair of CPU to detect control circuit and enables the common control of level;
Behind power connection, produce the alternation high pressure by oscillator, transistor and step-up transformer and after rectification, charge to energy-storage travelling wave tube.
8. delay initiator as claimed in claim 1 is characterized in that, described energy-storage travelling wave tube remaining capacity leadage circuit comprises energy-storage travelling wave tube, discharge resistance and the switch of releasing, wherein:
After electrion finished, described energy-storage travelling wave tube of the described switch connection of releasing and described discharge resistance formed the loop, and the remaining capacity in the described energy-storage travelling wave tube is released by described discharge resistance.
9. delay initiator as claimed in claim 1 is characterized in that, described self-checking circuit comprises cell voltage comparison circuit, charge and discharge switch on off operating mode testing circuit and the energy-storage travelling wave tube remaining capacity testing circuit of releasing; Wherein:
Before the operation start that detonates, described pair of CPU detects control circuit described self-checking circuit output level state detected, judges to do the processing operation of shutdown or continuation performing a programme.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020591323XU CN201844765U (en) | 2010-10-29 | 2010-10-29 | Time-delay exploder |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201020591323XU CN201844765U (en) | 2010-10-29 | 2010-10-29 | Time-delay exploder |
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| CN201844765U true CN201844765U (en) | 2011-05-25 |
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| CN201020591323XU Expired - Fee Related CN201844765U (en) | 2010-10-29 | 2010-10-29 | Time-delay exploder |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355042A (en) * | 2011-09-14 | 2012-02-15 | 南京天溯自动化控制系统有限公司 | Super-capacitor-based direct current power device of power station and power supply method thereof |
| CN106597525A (en) * | 2016-12-30 | 2017-04-26 | 山东大学 | Automatic protection trigger and method for tunnel TSP advanced geological prediction |
| CN108490299A (en) * | 2018-05-31 | 2018-09-04 | 中国工程物理研究院电子工程研究所 | A kind of high pressure detonation component parameter automatic test approach and equipment |
| CN110174030A (en) * | 2019-06-26 | 2019-08-27 | 新疆工程学院 | A kind of detection device of perforation Magnedat time break |
| CN110673683A (en) * | 2019-10-14 | 2020-01-10 | 中国兵器工业集团第二一四研究所苏州研发中心 | Low temperature floats time delay drive controller |
| CN112037460A (en) * | 2020-08-22 | 2020-12-04 | 深圳市海曼科技股份有限公司 | Smoke alarm with battery state one-way switching function |
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2010
- 2010-10-29 CN CN201020591323XU patent/CN201844765U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355042A (en) * | 2011-09-14 | 2012-02-15 | 南京天溯自动化控制系统有限公司 | Super-capacitor-based direct current power device of power station and power supply method thereof |
| CN106597525A (en) * | 2016-12-30 | 2017-04-26 | 山东大学 | Automatic protection trigger and method for tunnel TSP advanced geological prediction |
| CN108490299A (en) * | 2018-05-31 | 2018-09-04 | 中国工程物理研究院电子工程研究所 | A kind of high pressure detonation component parameter automatic test approach and equipment |
| CN108490299B (en) * | 2018-05-31 | 2023-07-11 | 中国工程物理研究院电子工程研究所 | Automatic testing method and equipment for parameters of high-pressure detonation component |
| CN110174030A (en) * | 2019-06-26 | 2019-08-27 | 新疆工程学院 | A kind of detection device of perforation Magnedat time break |
| CN110174030B (en) * | 2019-06-26 | 2023-11-21 | 新疆工程学院 | Detection device for detonation signal of magneto-electric detonator for perforation |
| CN110673683A (en) * | 2019-10-14 | 2020-01-10 | 中国兵器工业集团第二一四研究所苏州研发中心 | Low temperature floats time delay drive controller |
| CN112037460A (en) * | 2020-08-22 | 2020-12-04 | 深圳市海曼科技股份有限公司 | Smoke alarm with battery state one-way switching function |
| CN112037460B (en) * | 2020-08-22 | 2022-02-18 | 深圳市海曼科技股份有限公司 | Smoke alarm with battery state one-way switching function |
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