CN201812817U - Adapter substrate of integrated circuit package - Google Patents
Adapter substrate of integrated circuit package Download PDFInfo
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- CN201812817U CN201812817U CN 201020550229 CN201020550229U CN201812817U CN 201812817 U CN201812817 U CN 201812817U CN 201020550229 CN201020550229 CN 201020550229 CN 201020550229 U CN201020550229 U CN 201020550229U CN 201812817 U CN201812817 U CN 201812817U
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- layer pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model relates to an adapter substrate of an integrated circuit package. The adapter substrate comprises a substrate body, wherein the substrate body is provided with a chip mounting region, first inner bonding pads and an outer bonding pad; and the outer bonding pad is electrically connected with the first inner bonding pads. In the adapter substrate, the substrate body is provided with the chip mounting region, a plurality of first inner bonding pads are arranged on the substrate body and electrically connected with the outer bonding pad which is positioned at the edge of the end part of the substrate body; when the substrate body is mounted in a shell, an input/output (I/O) port of a chip is electrically connected with the first inner bonding pads through second bonding wires and then the first inner bonding pads are electrically connected with bonding finger connecting ends on a bonding region through the second bonding wires, so that the I/O port of the chip is connected with a corresponding bonding finger connecting end on the bonding region to electrically connect the chip with the shell, the adapter substrate can adapt to the connection of different chips and the shell, is convenient to mount and use, shortens the research, development and package period of the circuit, reduces the package cost, improves the reliability of the connection between the chip and the shell and is safe and reliable.
Description
Technical field
The utility model relates to a kind of interposer substrate, and the interposer substrate of especially a kind of integrated circuit encapsulation specifically a kind ofly realizes being electrically connected between chip and shell by interposer substrate, belongs to the technical field of integrated circuit encapsulation.
Background technology
In the integrated circuit encapsulation, traditional IC lead-in wire bonding is fine wire on bonding between each I/O end of chip and its corresponding packaging pin, realizes that chip is connected with the electricity of shell.Along with the rapid raising of integrated circuit (IC) design and technology level, chip area is done littler and littler, and integrated level is more and more higher, and the I/O port number of chip is more and more, and chip I/O(I/O) the outer pins corresponding relation of port and shell is also complicated more.Integrated circuit for ceramic packaging, the pad on the ceramic package and the correspondence position of chip bonding pad, spacing etc. all have very strict requirement, thereby high-density packages is more intense with the specificity of ceramic package, and versatility is poor, and a kind of shell can only adapt to several chips seldom.
At present, the matching relationship of ceramic package and chip chamber mainly contains following problem: a class is that ceramic package profile and number of pins meet the demands, but the shell cavity is excessive, chip is too small, causes bonding wire long (easily causing collapse-deformation), influences reliability of products; Another kind of is PAD(pad on the chip) position refers to exist lead-in wire to intersect with the bonding of shell, can not realize bonding; It is inconsistent and problem such as can not use that the 3rd class is that the correspondence of chip requires with the corresponding relation of shell.
Solve the basic scheme of above-mentioned condition: the one, chip design is constant, according to features such as the overall dimension requirement of product and chip size, PAD position, designed enclosures, die sinking tool and customized shell; The 2nd, utilize existing shell, change the placement-and-routing's part in the chip design, comprise the size and the I/O port distribution of chip.But all there is following point in these two kinds of schemes: lead time and production and processing cycle are long, and chip change design, plate-making, flow etc. need three months at least.Designed enclosures, die sinking tool and customized shell need four months; Input cost expense height, no matter be the redesign processing chip or the expense of shell at least tens0000 to hundreds of thousands unit; The problem of some reliability aspect can't directly expose (needing to confirm through follow-up screening, examination) toward contact in the encapsulation process, thereby can't avoid, and has influenced the safety that Chip Packaging is used.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, and a kind of interposer substrate of integrated circuit encapsulation is provided, and it is simple and compact for structure, and is easy to install, shortens the encapsulation production cycle, improves the reliability of encapsulation, reduces packaging cost, safe and reliable.
According to the technical scheme that the utility model provides, the interposer substrate of described integrated circuit encapsulation comprises substrate body; The center of described substrate body is provided with chip installation area; Substrate body is provided with the first internal layer pad corresponding to the outer ring that chip installation area is set, and the outer ring of the described first internal layer pad is provided with outer layer pad, is complementary between described first internal layer pad and outer layer pad; Outer layer pad is positioned at the end edge of substrate body, the contiguous described chip installation area of the first internal layer pad; Be electrically connected between outer layer pad and the first internal layer pad.
Described substrate body is provided with the second internal layer pad corresponding to the outer ring that chip installation area is set, the contiguous described chip installation area of the described second internal layer pad, and the described second internal layer pad is electrically connected with outer layer pad.
Be electrically connected by first connecting line and/or second connecting line between the described first internal layer pad and outer layer pad.Be electrically connected by first connecting line and/or second connecting line between the described second internal layer pad and outer layer pad.On the described substrate body corresponding to being provided with the internal layer power ring between the chip installation area and the first internal layer pad.Be provided with between described adjacent outer layer pad and draw/pull down resistor.Be provided with diode between described adjacent outer layer pad.
Described substrate body is provided with shell outward, and the core of described shell is provided with installing zone, and the bonding that shell is used corresponding to the bonding that is provided with corresponding connection around the installing zone refers to; Substrate body is fixed on the installing zone of shell corresponding to the another side that chip installation area is set; Chip is installed on the chip installation area, the shape of described chip and chip installation area matches, corresponding I/O port is electrically connected with the first internal layer pad on the substrate body by second bonding wire on the described chip, refer to be electrically connected by first bonding wire and the bonding of the corresponding bonding region that is connected with the corresponding outer layer pad of the described first internal layer pad on the substrate body, make on the shell corresponding bonding refer on link and the chip that the I/O port is electrically connected accordingly.
Described substrate body is fixed on the surface of shell installing zone by first adhesive glue; Chip is fixed on the chip installation area of substrate body by second adhesive glue.Described substrate body is provided with the chip locating piece.
Advantage of the present utility model: substrate body is provided with chip installation area, is used to install and fix chip; Outer ring corresponding to chip installation area on the substrate body is provided with a plurality of first internal layer pads, and the first internal layer pad is electrically connected with the outer layer pad that is positioned at the substrate body end edge; When substrate body is installed in the enclosure, be electrically connected with the first internal layer pad by the I/O port of second bonding wire chip, by second bonding wire first internal layer pad is referred to that with bonding on the bonding region link is electrically connected again, thereby corresponding bonding refers to that link links to each other on the I/O port that makes chip and the bonding region, can adapt to being connected between different chips and shell, easy to install, the research and development and the encapsulation cycle of circuit have been shortened, reduced packaging cost, improved the reliability that chip is connected with shell, safe and reliable.
Description of drawings
Fig. 1 is a structural representation of the present utility model.
Fig. 2 is user mode figure of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with concrete drawings and Examples.
As Fig. 1 ~ shown in Figure 2: the utility model comprises outer layer pad 1, first connecting line 2, second connecting line 3, on draw/pull down resistor 4, diode 5, the first internal layer pad 6, the second internal layer pad 7, internal layer power ring 8, chip installation area 9 on the substrate, chip locating piece 10, shell 11, first bonding wire 12, second bonding wire 13, chip 14, interposer substrate 15, second adhesive glue 16, shell bonding region 17, first adhesive glue 18, chip on the shell/substrate installing zone 19 and substrate body 20.
As shown in Figure 1: described interposer substrate 15 comprises substrate body 20, and the center of described substrate body 20 is provided with chip installation area 9, and the shape of described chip installation area 9 matches with the size of the chip 14 that will install; Chip 14 can be fixed on the chip installation area 9 by second adhesive glue 16.Substrate body 20 is provided with the first internal layer pad 6 corresponding to the outer ring of chip installation area 9, and the described first internal layer pad 6 can be looped around the outer ring of chip installation area 9; The shape of the first internal layer pad 6 and quantity can be carried out relative set according to the I/O port distribution and the quantity of chip 14, can guarantee chip 14 the I/O port can with the corresponding connection of the link on the shell 11.Outer ring corresponding to the first internal layer pad 6 on the substrate body 20 is provided with outer layer pad 1, and the described outer layer pad 1 and the first internal layer pad 6 are complementary, and outer layer pad 1 links to each other with the first internal layer pad 6 is corresponding one by one mutually.The first internal layer pad, 6 adjacent chips installing zones 9, outer layer pad 1 is positioned at the end edge of substrate body 20, and outer layer pad 1 is electrically connected with 6 of the first internal layer pads.Substrate body 20 is provided with chip locating piece 10, and described chip locating piece 20 is positioned at the outside of chip installation area 9, can effectively locate the position that chip 14 is installed in chip installation area 9.
The second internal layer pad 7 can also be set on the substrate body 20, and the described second internal layer pad 7 is used for the connection of internal layer multikey chalaza; The first internal layer pad 6 and the second internal layer pad 7 can be set on the substrate body 20 as required simultaneously.The second internal layer pad 7 is adjacent chips installing zone 9 also.When outer layer pad 1 and the first internal layer pad 6, the second internal layer pad 7 just in time at once, when only laying one deck wiring board on the substrate body 20, outer layer pad 1 is electrically connected by first connecting line 2 with the first internal layer pad 6.When the outer layer pad 1 and the first internal layer pad 6 not at once, when laying two-layer wiring board on the substrate body 20, outer layer pad 1 is with the first internal layer pad 6, also need to be electrically connected by second connecting line 3; Two-layer wiring board is isolated by separator, and second connecting line 3 can be avoided the intersection that goes between.When the second internal layer pad 7 was set on the substrate body 20, the annexation and the first internal layer pad 6 that the second internal layer pad 7 and first connecting line 2, second connecting line are 3 were similar.Be provided with 1 of adjacent outer layer pad and draw/pull down resistor 4 or diode 5, on draw/pull down resistor 4 or diode 5 be provided with according to the needs that chip 14 connects, and can be used to change the function of circuit.In order to connect more easily, be provided with internal layer power ring 8 at chip installation area 9 and the first internal layer pad 6 or 7 of the second internal layer pads, described internal layer power ring 8 is looped around the outer ring of chip installation area 9, and corresponding I/O port can be electrically connected with corresponding link on the shell 11 by internal layer Voltage loop 8 on the chip 14.
As shown in Figure 2: after adopting interposer substrate 15, the encapsulating structure schematic diagram that chip 14 and shell are 11.Shell 11 adopts ceramic material to make, the center of shell 11 is provided with chip/substrate installing zone 19, shell 11 connects with bonding region 17 corresponding to being provided with around the installing zone 19, described connection bonding region 17 is provided with the link that corresponding bonding refers to mutually, described link can be electrically connected with corresponding I/O port on the chip 14, thus being electrically connected chip 14 and shell 11.Interposer substrate 15 is fixed on the surface of the chip/substrate installing zone 19 of shell by first adhesive glue 18 corresponding to the other end that chip installation area 9 is set; After interposer substrate 15 installed and fixed, chip 14 was fixed on chip installation area 9 by second adhesive glue 16; Because chip 14 matches with the size of chip installation area 9, so chip 14 can be safe and reliable is installed on the chip installation area 9.When corresponding I/O port on the chip 14 need be connected to bonding on the bonding region 17 and refers to link, corresponding I/O port is electrically connected with the first internal layer pad 6 or the second internal layer pad 7 on the substrate body 20 by second bonding wire 13 on the chip 14, also can be electrically connected with internal layer power ring 8.After corresponding I/O port connects on the chip 14, refer to that with bonding on being connected bonding region 17 link is electrically connected by first bonding wire 12 with the first internal layer pad 6 or the second internal layer pad, 7 corresponding outer layer pad 1, be corresponding I/O port refers to the link electrical connection by second bonding wire 13 and second bonding wire 12 with bonding on being connected bonding region 17 on the chip 14, reached being electrically connected of chip 14 and 11 on shell.When second bonding wire 13 linked to each other with internal layer power ring 8, first bonding wire 12 linked to each other with internal layer power ring 8, and corresponding bonding refers to that link is electrically connected on the other end and the bonding region 17.First bonding wire 12 and second bonding wire 13 all adopt naked spun gold to make; When the length of first bonding wire 12 or second bonding wire 13 was longer, first bonding wire 12 or second bonding wire, 13 easy collapse-deformations caused the short circuit of encapsulating structure.The two ends of first bonding wire 12 are when bonding on outer layer pad 1 and the bonding region 17 refers to that link links to each other, and first bonding wire, 12 curved shapes have a radian that makes progress; When second bonding wire 13 linked to each other with the first internal layer pad 6, the second internal layer pad 7 or internal layer power ring 8, second bonding wire 13 also needed to have a radian that makes progress, and had guaranteed the reliability that connects.During being electrically connected of chip 14 and shell 11, after the transition of the first internal layer pad 6 by substrate body 20 or the second internal layer pad 7 and outer layer pad 1, can reduce the length of chip 14 and 11 correspondent button plying of shell, avoid the collapse-deformation of chip 14 and 11 correspondent button plying of shell, guaranteed 11 reliabilities that are electrically connected of chip 14 and shell; Equally, when chip 14 passes through 8 transition of internal layer power ring with being electrically connected of 11 on shell, also can reduce the length of first bonding wire 12 and second bonding wire 13.
The structure of interposer substrate 15 is to utilize existing ripe semiconductor wafer manufacturing technique (5 μ m are to submicrometer processing, deep submicron process is preferably used less, because of its processing cost higher relatively), on the designing technique of integrated circuit, with the silicon wafer technological method for processing, on substrate body 20, obtain the corresponding first internal layer pad 6, the second internal layer pad 7, outer layer pad 1, first connecting line 2 and second connecting line 3; Draw simultaneously/pull down resistor 4 can make formation simultaneously with diode 5; The outer layer pad 1 on the substrate body 20 and the first internal layer pad 6(or the second internal layer pad 7) corresponding with the I/O port of chip 14 of corresponding link and required installation on the shell 11 respectively, guarantee 11 couplings that are connected of chip 14 and shell.
According to the order of the I/O port on the need packaged chip 14 and with the outer lead corresponding relation and the requirement of shell 11, at first design the domain of interposer substrate 15.The first internal layer pad 6 and the second internal layer pad 7 on the substrate body 20 are corresponding with the I/O port of chip 14, and the outer layer pad 1 on the substrate body 20 is corresponding with shell 11 outer leads that encapsulation requires.Secondly, by chip 14 processing technologys, realize the processing of interposer substrate 15; By mask plate-making, the disk of interposer substrate 15 is made in the technology flow, uses for encapsulation.By the processing of packaging technology, realize the application of interposer substrate 15 at last.
In encapsulation process, by attenuate, scribing, the disk of interposer substrate 15 is divided into slices, become the individual sheets that can be placed in the shell 11.Solidify through load again, interposer substrate 15 is cured in the mounting groove 19 of shell 11, then the chip 14 of required encapsulation is solidificated on the chip installation area 9 of interposer substrate 15, by corresponding cooperation the on first bonding wire 12 and second bonding wire 13 and the interposer substrate 15, realize being electrically connected of chip 14 and shell 11.
The process of making interposer substrate 15 comprises the steps:
(a), selected meet the shell 11 that overall dimension requires, shell 11 can be encapsulated chip 14 accordingly;
(b), the inner chamber body size according to selected shell 11, the area of chip 14, determine the size of substrate body 20 and the installation region of chip 14;
(c), the arrangement mode and the position that refer to according to the shell bonding, the position and the size of outer layer pad 1 on the design interposer substrate 15; According to arrangement mode, position and the size of the I/O port of chip 14, the position and the size of the first internal layer pad 6 and the second internal layer pad 7 on the design interposer substrate 15; Effective conducting of the first internal layer pad 6, the second internal layer pad 7 and outer layer pad 1 is realized just in time at once in the position of the outer layer pad 1 and the first internal layer pad 6, the second internal layer pad 7 by individual layer aluminium wiring (first connecting line 2) on interposer substrate 15; Change by the design multilayer wiring not at once the position of the outer layer pad 1 and the first internal layer pad 6, the second internal layer pad 7 on interposer substrate 15, realizes that outer layer pad 1 refers to the corresponding of (link) with the shell bonding; The I/O port of the first internal layer pad 6, the second internal layer pad 7 and chip 14 corresponding; When multilayer wiring is set, need the first internal layer pad 6, the second internal layer pad 7 to be electrically connected with outer layer pad 1 by second connecting line 3;
(d), interposer substrate 15 that design is finished carries out design verification, comprise parasitic capacitance, on draw/pull down resistor 4, inductive effect the characteristic of diode 5, the first internal layer pad 6, the second internal layer pad 7, internal layer power ring 8;
(e), chip installation area 9 upper left sides are provided with the installing and locating piece, formation installing and locating sign;
(f), the interposer substrate 15 by the wafer flow is carried out electric performance test;
(g), encapsulation that the disk of interposer substrate 15 is pressed laminated chips allows requirement for height, carries out the attenuate of disk thickness;
(h), after interposer substrate 15 test finishes, interposer substrate 15 is installed in the shell 11, then chip 14 is installed in chip installation area 9.
After above-mentioned steps, chip 14 is electrically connected with shell 11 with second bonding wire 13 by first bonding wire 12 again.
The utlity model has following advantage:
1), reduced cost; Design customization shell 11 needs the hundreds of thousands expense, and change integrated circuit (IC) design, flow expense also need hundreds of thousands unit, and design interposer substrate 15 and processing flow expense only need several ten thousand yuan, and cost reduces more than 80%.
2), the I/O port number that solved 11 pairs of chips 14 of general shell is many, the encapsulation problem that the area of chip 14 is little; Solved the I/O encapsulation problem not corresponding of chip 14 with the link of shell 11.
3), improved package reliability; By the effect of first bonding wire 12 and second bonding wire 13, shortened the length of single bonding wire, thereby improved the reliability and the encapsulation rate of finished products of bonding.
4), shortened the research and development and the encapsulation cycle of circuit, realize encapsulation fast; The design of interposer substrate 15 and production only need about 25 days, and four months of redesign, customized shell 11 relatively, the encapsulation cycle shortened about 80%, thereby realizes the purpose of encapsulation fast.
5), realize the versatility of shell 11; By interposer substrate 15, realize several chip 14 shared interposer substrate 15, realize the versatility of shell 11 and interposer substrate 15.
6), realize circuit exit function conversion, for the design optimization of circuit provides a kind of reference scheme.
The utility model interposer substrate 15 is to be added between integrated circuit when encapsulation chip 14 and the shell 11, and realization chip 14 is connected with the electricity of shell 11.By the bonding of chip 14, realize that chip 14 is connected with the electricity of shell 11 with bonding, interposer substrate 15 and the shell 11 of interposer substrate 15.By draw in the interposer substrate 15/pull down resistor 4, diode 5 realize the conversion of circuit functions, can adapt to being connected of different chips 14 and 11 on shell, easy to install, the research and development and the encapsulation cycle of circuit have been shortened, reduced packaging cost, improved the reliability that chip 14 is connected with shell 11, safe and reliable.
Claims (10)
1. the interposer substrate of an integrated circuit encapsulation comprises substrate body (20); It is characterized in that: the center of described substrate body (20) is provided with chip installation area (9); Substrate body (20) is provided with the first internal layer pad (6) corresponding to the outer ring that chip installation area (9) is set, and the outer ring of the described first internal layer pad (6) is provided with outer layer pad (1), is complementary between described first internal layer pad (6) and outer layer pad (1); Outer layer pad (1) is positioned at the end edge of substrate body (20), the contiguous described chip installation area (9) of the first internal layer pad (6); Be electrically connected between outer layer pad (1) and the first internal layer pad (6).
2. the interposer substrate of integrated circuit encapsulation according to claim 1, it is characterized in that: described substrate body (20) is provided with the second internal layer pad (7) corresponding to the outer ring that chip installation area (9) is set, the contiguous described chip installation area (9) of the described second internal layer pad (7), the described second internal layer pad (7) is electrically connected with outer layer pad (1).
3. the interposer substrate of integrated circuit according to claim 1 encapsulation is characterized in that: be electrically connected by first connecting line (2) and/or second connecting line (3) between the described first internal layer pad (6) and outer layer pad (1).
4. the interposer substrate of integrated circuit according to claim 2 encapsulation is characterized in that: be electrically connected by first connecting line (2) and/or second connecting line (3) between the described second internal layer pad (7) and outer layer pad (1).
5. the interposer substrate of integrated circuit encapsulation according to claim 1 is characterized in that: described substrate body (20) goes up corresponding to being provided with internal layer power ring (8) between the chip installation area (9) and the first internal layer pad (6).
6. the interposer substrate of integrated circuit encapsulation according to claim 1 is characterized in that: be provided with between described adjacent outer layer pad (1) and draw/pull down resistor (4).
7. the interposer substrate of integrated circuit encapsulation according to claim 1 is characterized in that: be provided with diode (5) between described adjacent outer layer pad (1).
8. the interposer substrate of integrated circuit encapsulation according to claim 1, it is characterized in that: described substrate body (20) is provided with shell (11), the center of described shell (11) is provided with the installing zone (19) of chip/substrate, shell (11) is corresponding to being provided with bonding region (17) around the installing zone (19), and described bonding region (17) is provided with corresponding bonding and refers to link; Substrate body (20) is fixed on the surface of installing zone (19) corresponding to the another side that chip installation area (9) is set; Chip (14) is installed on the chip installation area (9), described chip (14) matches with the shape of chip installation area (9), described chip (14) is gone up corresponding I/O port and is electrically connected with the first internal layer pad (6) on the substrate body (20) by second bonding wire (13), substrate body (20) goes up and to go up corresponding bonding with the described first corresponding outer layer pad of internal layer pad (6) (1) by first bonding wire (12) and bonding region (17) and refer to that link is electrically connected, and makes that corresponding bonding refers to that corresponding I/O port is electrically connected on link and the chip (14) on the bonding region (17).
9. the interposer substrate of integrated circuit encapsulation according to claim 8, it is characterized in that: described substrate body (20) is fixed on the bottom land of mounting groove (19) by first adhesive glue (18); Chip (14) is fixed on the chip installation area (9) of substrate body (20) by second adhesive glue (16).
10. the interposer substrate of integrated circuit encapsulation according to claim 1, it is characterized in that: described substrate body (20) is provided with chip locating piece (10).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020550229 CN201812817U (en) | 2010-09-30 | 2010-09-30 | Adapter substrate of integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020550229 CN201812817U (en) | 2010-09-30 | 2010-09-30 | Adapter substrate of integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201812817U true CN201812817U (en) | 2011-04-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201020550229 Expired - Lifetime CN201812817U (en) | 2010-09-30 | 2010-09-30 | Adapter substrate of integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201812817U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103823147A (en) * | 2013-11-04 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Bonding wire touch short circuit detection method based on pulse capture |
| WO2023083021A1 (en) * | 2021-11-12 | 2023-05-19 | 合肥本源量子计算科技有限责任公司 | Quantum device and preparation method therefor, and quantum computer |
-
2010
- 2010-09-30 CN CN 201020550229 patent/CN201812817U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103823147A (en) * | 2013-11-04 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Bonding wire touch short circuit detection method based on pulse capture |
| CN103823147B (en) * | 2013-11-04 | 2016-06-01 | 中国人民解放军国防科学技术大学 | Based on the bonding wire touching method for detecting short circuit of pulse capture |
| WO2023083021A1 (en) * | 2021-11-12 | 2023-05-19 | 合肥本源量子计算科技有限责任公司 | Quantum device and preparation method therefor, and quantum computer |
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