CN201774613U - RGB analog video signal acquisition system - Google Patents

Abstract

The utility model relates to the image display and video processing technology, in particular to an RGB analog video signal acquisition system, which is characterized by comprising a signal adjusting module, a timing sequence separating module and an A/D converting module. The signal adjusting module consists of a clamping circuit and a buffering amplifying circuit which are connected mutually, the timing sequence separating module consists of a synchronous separating chip, an FPGA chip and a clock separating circuit, the FPGA chip is respectively connected with the clock separating circuit, the synchronous separating chip, the clamping circuit and the A/D converting module, and the clock separating circuit is a lock-phase ring. The RGB analog video signal acquisition system can adjust stability, synchronism and differentiation such as data position shift and the like of input video signals, is fine in tolerance property of difference of input signals, and can meet actual application requirement better.

Description

RGB analog video signal acquisition system

Technical field

The utility model relates to image and shows and video processing technique, particularly about a kind of RGB analog video signal acquisition system.

Background technology

Development along with the electric video technology is referred from traditional television technology, and the video system of standard systems such as PAL, NTSC extensively applies to fields such as aviation, automobile, monitoring.Existing video acquisition realizes being divided into two kinds of discrete component and integrated chips.Two kinds of acquisition modes have satisfied the demand that normal video is gathered to a certain extent, but that dual mode all exists otherness equally is poor, the problem that the tolerance ability is weak.As under some specific conditions: it is different with standard system that video format does not satisfy standard, the video active position of standard slightly.When there being such difference, original acquisition technique just can not satisfy the demands, thereby causes the video acquisition afunction, the phenomenon of image data distortion.

Summary of the invention

The utility model purpose is: exist tolerance not good enough in order to solve the prior art video acquisition system, the problem of data distortion takes place easily, the utility model provides a kind of video acquisition system with better tolerance that utilizes discrete component and FPGA to make up.

The technical solution of the utility model is: a kind of RGB analog video signal acquisition system, its spy comprises signal adjusting module, sequential separation module, A/D modular converter, wherein, described signal adjusting module is made up of interconnective clamp circuit and buffer amplifier circuit, described sequential separation module is made up of Sync Separator Chip, fpga chip and hour hands split circuit, described fpga chip links to each other with hour hands split circuit, Sync Separator Chip, clamp circuit and A/D modular converter respectively, wherein, described hour hands split circuit is a phase-locked loop.

Described phase-locked loop comprises phase discriminator, loop filter and the voltage controlled oscillator that links to each other successively, and wherein, described voltage controlled oscillator links to each other with phase discriminator behind fpga chip.

Described A/D converter module is the TLC5540 chip.

Described Sync Separator Chip is the EL4583 chip, and described hour hands split circuit phase-locked loop is the 74HC4046 chip.

The beneficial effects of the utility model: the utility model RGB analog video signal acquisition system is utilized common discrete component framework, but the video acquisition system with high tolerance of employing scene editorial logic device (FPGA) art designs, solved amplitude when incoming video signal, level, synchronously, the video acquisition problem when active position etc. there are differences with video standard signal, it is good to have tolerance, easy to adjust, the little characteristics of data distortion in the video acquisition process.

Description of drawings

Fig. 1 is the theory diagram of the utility model RGB analog video signal acquisition system;

Fig. 2 is the utility model RGB analog video signal acquisition system signal adjusting module block diagram;

Fig. 3 is the utility model RGB analog video signal acquisition system sequential separation module block diagram;

Fig. 4 is the utility model RGB analog video signal acquisition system hour hands split circuit block diagram;

Wherein, 1-signal adjusting module, 2-sequential separation module, 3-A/D modular converter, 10-clamp circuit, 11-buffer amplifier circuit, 20-Sync Separator Chip, 21-hour hands split circuit, 22-FPGA chip.

Embodiment

Below by specific embodiment the utility model is described in further detail:

Please consult Fig. 1, Fig. 2 and Fig. 3 simultaneously, wherein, Fig. 1 is the theory diagram of the utility model RGB analog video signal acquisition system, and Fig. 2 is the signal adjusting module block diagram of RGB analog video signal acquisition system, and Fig. 3 is a RGB analog video signal acquisition system sequential separation module block diagram.In the present embodiment, described RGB analog video signal acquisition system comprises signal adjusting module 1, sequential separation module 2, A/D modular converter 3.Wherein, described signal adjusting module 1 is made up of with buffer amplifier circuit 11 interconnective clamp circuit 10.Described sequential separation module 2 is made up of Sync Separator Chip 20, fpga chip 22 and hour hands split circuit 21.Described fpga chip 22 links to each other with hour hands split circuit 21, Sync Separator Chip 20, clamp circuit 10 and A/D modular converter 3 respectively.

In the present embodiment, clamp circuit 10 in the described signal adjusting module 1 adopts field effect transistor ZXM61N03FTA, utilize the cyclophysis of the switching characteristic and the analog signal of field effect transistor, externally import the position of analog signal back porch, the vision signal of input is carried out direct current recover, the vision signal of input is unified clamper on zero level.And buffer amplifier circuit 11 adopts video algorithms amplifier AD813, and the analog signal of clamp circuit 10 outputs is carried out amplitude and level adjustment.

Therefore signal adjusting module 1 is adjusted to standard value by the adjustment of inner clamp circuit 10 with 11 pairs of signals of buffer amplifier circuit with outside incoming video signal amplitude leyel.

Described sequential separation module 2 comprises Sync Separator Chip 20, hour hands split circuit 21, s operation control fpga chip 22, and main effect is to generate the vision signal clock signal.Vision signal at first enters Sync Separator Chip 20, obtains row, field sync signal, the odd even identification signal of vision signal.S operation control fpga chip 22 receives row, field sync signal, odd even identification signal, after cooperation hour hands split circuit 21 feeds back computing, obtains pixel clock.And with pixel clock, line synchronizing signal, field sync signal, the output of odd even identification signal.

What wherein, the Sync Separator Chip 20 in the described sequential separation module 2 adopted is that the EL4583 chip is realized.The EL4583CS chip with the signal end filtering, obtains composite synchronizing signal by the amplitude control with signal, separates trip, field sync signal, odd even identification signal from the synchronous vision signal of input tape (green).

Described hour hands split circuit 21 employing phase-locked loop chip 74HC4046 utilize phase-locked loop to operate the line synchronizing signal that characteristic cooperates the cycle stability of s operation control FPGA22 acquisition, according to the comparison signal generation phase-locked clock of line synchronizing signal and the generation of FPGA counter.

Please consult Fig. 4 simultaneously, it is a hour hands split circuit block diagram among Fig. 1.Described hour hands split circuit is a kind of feedback control circuit, and its phase-locked loop is called phase comparator, loop filter (LF) and voltage controlled oscillator (VCO) three parts again by phase discriminator (PD) usually and forms.This phase-locked loop utilizes the frequency and the phase place of the reference signal control loop internal oscillation signal of outside input, realize output signal frequency to frequency input signal from motion tracking.Phase-locked loop work process in, when output signal frequency equates with the frequency of input signal, the phase difference value that output signal and input signal are maintained fixed, promptly output signal and phase of input signals are lockable.

In the present embodiment, because the reference signal SIG of phase-locked loop is identical in the cycle with comparison signal COMP, phase difference is certain.If the cycle of reference signal SIG is t _SIGSo, can obtain the pixel clock f of different frequency according to the divide ratio N that adjusts frequency counter _Vcoout

$f_{\mathrm{vcoout}}=\frac{N}{t_{\mathrm{SIG}}}$

As the isolated line frequency of pal mode standard signal is 15625Hz, and the cycle is 64us, and the cycle of reference signal SIG so herein is 64us.During as divide ratio 640:

$f_{\mathrm{vcoout}}=\frac{N}{t_{\mathrm{SIG}}}=\frac{640}{64\mathrm{us}}=10\×{10}^6\mathrm{Hz}$

Can obtain pixel clock is 10MHz.

In addition, described A/D converter module 3 adopts the TLC5540 chip, mainly mode video signal is converted to digital of digital video data according to pixel clock.

The utility model RGB analog video signal acquisition system adopts the core of fpga chip 22 as whole s operation control, the signal adjusting module that constitutes by clamp circuit 10 and buffer amplifier circuit 11, sequential separation module by Sync Separator Chip 20,22 realizations of hour hands split circuit 21 associative operations control fpga chip, realize vision signal benchmark uniformly by clamp circuit 10, realize the adjusted in concert sampling of external video by Sync Separator Chip 20, and realize the generation of optional frequency reference clock by hour hands split circuit 21.

And collection of video signal comprises video data and video sequential.Video data is meant the image content that input video is gathered.The video sequential is meant the pairing characterisitic parameter of video data, comprises pixel clock, line synchronizing signal, field sync signal, odd even identification signal.

During the work of the utility model RGB analog video signal acquisition system, through signal adjusting module 1, be converted to video data behind the A/D sampling module 3 after the outer video signal input.Enter sequential separation module 2 with synchronous vision signal and produce pixel clock, i.e. line synchronizing signal, field sync signal, odd even identification signal.When there is uncertain problem in the amplitude and the level of outside incoming video signal, nonstandard as amplitude, when level is unstable, can guarantee data stability by signal adjusting module 1.When outside incoming video signal exists synchronously and standard signal when there are differences, the configuration that can regulate Sync Separator Chip 20 realizes synchronous generation.When skew takes place in external video valid data position,, can obtain suitable frequency and data, thereby avoid the distortion in the video data acquiring process by adjusting the control of s operation control fpga chip 22.Therefore, the utility model can be to the stability of incoming video signal, and othernesses such as synchronism and Data Position skew are adjusted, and its tolerance to the input signal otherness is good, can satisfy actual application demand preferably.

Claims (4)

1. RGB analog video signal acquisition system, it is characterized in that: comprise signal adjusting module, sequential separation module, A/D modular converter, wherein, described signal adjusting module is made up of interconnective clamp circuit and buffer amplifier circuit, described sequential separation module is made up of Sync Separator Chip, fpga chip and hour hands split circuit, described fpga chip links to each other with hour hands split circuit, Sync Separator Chip, clamp circuit and A/D modular converter respectively, wherein, described hour hands split circuit is a phase-locked loop.

2. RGB analog video signal acquisition system according to claim 1 is characterized in that: described phase-locked loop comprises phase discriminator, loop filter and the voltage controlled oscillator that links to each other successively, and wherein, described voltage controlled oscillator links to each other with phase discriminator behind fpga chip.

3. RGB analog video signal acquisition system according to claim 2 is characterized in that: described A/D converter module is the TLC5540 chip.

4. RGB analog video signal acquisition system according to claim 3 is characterized in that: described Sync Separator Chip is the EL4583 chip, and described hour hands split circuit phase-locked loop is the 74HC4046 chip.

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