CN201674464U - Under-sampling frequency mixing circuit - Google Patents
Under-sampling frequency mixing circuit Download PDFInfo
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- CN201674464U CN201674464U CN2010202069244U CN201020206924U CN201674464U CN 201674464 U CN201674464 U CN 201674464U CN 2010202069244 U CN2010202069244 U CN 2010202069244U CN 201020206924 U CN201020206924 U CN 201020206924U CN 201674464 U CN201674464 U CN 201674464U
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Abstract
The utility model relates to an under-sampling frequency mixing circuit, which comprises a sampling control signal generator, a first-stage under-sampling circuit, a second-stage under-sampling circuit and a band-pass filter. A first output end of the sampling control signal generator is connected with a control signal input end of the first-stage under-sampling circuit, a second output end of the sampling control signal generator is connected with a control signal input end of the second-stage under-sampling circuit, a signal input end of the first-stage under-sampling circuit is connected with a signal input end of the second-stage under-sampling circuit, and a signal output end of the second-stage under-sampling circuit is connected with the band-pass filter. The under-sampling frequency mixing circuit has the advantages that the circuit is low in cost, can convert high-frequency signals into low-frequency signals, and is particularly applicable to element detecting devices.
Description
Technical field
The utility model relates to the signal mixing technical field, and the principle that particularly a kind of usefulness owes to sample is mixed to high-frequency signal the mixting circuit of low frequency signal.
Background technology
In the high-frequency test circuit, the test signal that the high-frequency signal that produces from signal generator produces after being loaded on the element under test still is a high-frequency signal, when these high-frequency signals are carried out digitized processing, often can't meet the demands because the sampling A sample frequency is low, and cause and can't element under test be detected accurately, if select the high sampling A of sample frequency, cost can be very high, and need the corresponding high performance process chip of configuration, finally cause cost high or can't realize detection to element under test at all.
Summary of the invention
The purpose of this utility model is at the sample frequency of existing sampling A in the existing high-frequency test circuit described in the background technology lower, can't satisfy the problem of the needs of high-frequency test circuit, and a kind of undersampling mixer circuit is provided.
The realization the technical solution of the utility model is as follows:
A kind of undersampling mixer circuit, it is characterized in that: it comprises the sampling control signal generator, the first order is owed sample circuit, sample circuit and band pass filter are owed in the second level, first output of sampling control signal generator connects the signal input end that the first order is owed sample circuit, second output of sampling control signal generator connects the signal input end that sample circuit is owed in the second level, the signal output part that the first order is owed sample circuit is connected with the signal input part that sample circuit is owed in the second level, and the signal output part connecting band bandpass filter of sample circuit is owed in the second level.
Described sampling control signal generator comprises sample frequency input, d type flip flop or door and not gate, the CLK end of described sample frequency input and d type flip flop, first or door be connected with second or the input of door, the output Q end connection first of d type flip flop or the input of door
The D end of the input of end connection second or door and d type flip flop, the CLR end of d type flip flop is connected power supply with the PR end, first or the door output connect first not gate, second or the door output connect second not gate, first or the door output be the positive control signal input part of second level sample circuit, the output of first not gate is the input of the negative control signal of second level sample circuit, second or the door output be the positive control signal input part of first order sample circuit, the output of second not gate is the input of the negative control signal of first order sample circuit.
The positive control signal input part of described first order sample circuit and first field effect transistor, the grid of the 3rd field effect transistor and the 4th field effect transistor connects, the source electrode of first field effect transistor connects treats sampled signal, the drain electrode of first field effect transistor connects the positive input terminal and first resistance of first amplifier, the first resistance other end ground connection, the output of first amplifier connects the negative input end of first amplifier by second resistance, the first amplifier output connects the drain electrode of second field effect transistor by the 3rd resistance, the grid of second field effect transistor connects the negative control signal input part of first order sample circuit, the source ground of second field effect transistor, the 3rd resistance is connected with the source electrode of the 3rd field effect transistor, the drain electrode of the 3rd field effect transistor connects the negative input end of second amplifier, the grounded drain of the 4th field effect transistor, the source electrode of the 4th field effect transistor connects the positive input terminal of second amplifier, the output of second amplifier is the signal output part that the first order is owed sample circuit, be connected with first electric capacity between the source electrode of the 4th field effect transistor and the drain electrode, be connected with second electric capacity between the negative input end of second amplifier and the output, the output of second amplifier is connected with the drain electrode of second field effect transistor by the 4th resistance.
The signal output part that the described first order is owed sample circuit is the signal input part that sample circuit is owed in the second level, the signal input part of second utmost point sample circuit connects the source electrode of the 5th field effect transistor, the positive control signal input part of second utmost point sample circuit connects the 5th field effect transistor, the grid of the 7th field effect transistor and the 8th field effect transistor, the drain electrode of the 5th field effect transistor connects the drain electrode of the 6th field effect transistor by the 5th resistance, the grid of the 6th field effect transistor connects the negative control signal input part of second utmost point sample circuit, the source ground of the 6th field effect transistor, the drain electrode of the 6th field effect transistor connects the source electrode of the 7th field effect transistor, the source electrode of the 7th field effect transistor is connected with the negative input end of the 3rd amplifier, the source electrode of the 8th field effect transistor connects the positive input terminal of the 3rd amplifier, the grounded drain of the 8th field effect transistor, be connected with the 3rd electric capacity between the source electrode of the 8th field effect transistor and the drain electrode, the output of the 3rd amplifier connects the negative input end of the 3rd amplifier by the 3rd electric capacity, the output of the 3rd amplifier connects the drain electrode of the 6th field effect transistor by the 6th resistance, and the output of the 3rd amplifier is the signal output part that sample circuit is owed in the second level.
The beneficial effect that the utility model has compared with prior art is that sampling control signal generator, the first order are owed sample circuit, second utmost point is owed sample circuit and band pass filter because be provided with in the undersampling mixer circuit of the present utility model, according to Nyquist's theorem: when time-continuous signal converts discrete signal to, sampling number in one-period will be more than twice, if sampling number is not enough, the signal that can't recover to lose.Waveform frequency after owing to sample can change, but, if to electric current and the sampling of voltage two signal Synchronization, the relative amplitude and the phase invariant of two waveforms that generate, therefore, still can guarantee that by the waveform that obtains of owing to sample the required parameter of element test is constant, and then guarantee the accuracy of element testing.The sampling control signal fs1 that the first order is owed sample circuit is a high level, when nfs1 is low level, first field effect transistor, the 3rd field effect transistor, the 4th field effect transistor conducting, second field effect transistor is ended, first amplifier is finished and is followed function, second amplifier is finished negative function, the whole first order is owed the variation that sample circuit can be oppositely followed input signal, when sampling control signal fs1 is a low level, when nfs1 is high level, first field effect transistor, the 3rd field effect transistor, the 4th field effect transistor is ended, the second field effect transistor conducting, second amplifier is finished the maintenance function, and the whole first order is owed sample circuit and entered hold mode.Because the aperture time of the sampling of first order sample circuit is very long, the waveform the inside sample phase that causes sampling has a lot of original signal waveforms, therefore need remove this part waveform by second level sample circuit, the sampling control signal fs2 that sample circuit is owed in the second level is a high level, when nfs2 is low level, the 5th field effect transistor, the 7th field effect transistor and the 8th field effect transistor conducting, the 6th field effect transistor is ended, the 3rd amplifier is finished reverse one to one effect of amplifying, when sampling control signal fs2 is a low level, when nfs2 is high level, the 5th field effect transistor, the 7th field effect transistor and the 8th field effect transistor are ended, the 6th field effect transistor conducting, the 3rd amplifier is finished the maintenance function.It is different that the sampling control signal that sample circuit and the first order owe sample circuit is owed in the second level, therefore owing sample circuit in the first local second level of owing the sample circuit maintenance samples, because when the first order is owed sample circuit and is kept during waveform relatively stably, waveform when therefore second utmost point is owed the sample circuit sampling also is stably, and final second output waveform of owing sample circuit also is relatively stably.Second output waveform of owing sample circuit makes output waveform become level and smooth sine wave through band pass filter, this sine wave frequency is compared with input signal change has been taken place, realized the transformation of high-frequency signal to low frequency signal, the frequency of output waveform can satisfy the requirement of the sample frequency of general sampling A, save the manufacturing cost of detection system greatly, and guaranteed the accuracy of detection system.
Description of drawings
Fig. 1 is a square frame principle schematic diagram of the present utility model;
Fig. 2 is the circuit theory diagrams of sampling control signal generator of the present utility model;
Fig. 3 is circuit theory diagrams of owing sample circuit of the present utility model;
Fig. 4 is the waveform schematic diagram of sampling control signal of the present utility model;
Fig. 5 is the signal schematic representation after the process first order is owed sample circuit;
Fig. 6 is through the signal schematic representation behind the sample circuit of the second level;
Fig. 7 is the band pass filter circuit schematic diagram;
Fig. 8 is through the signal schematic representation behind the band pass filter;
Fig. 9 is the signal after the mixing and the contrast schematic diagram of input signal;
Figure 10 is for using the circuit theory diagrams that the utility model carries out the detection system of element testing;
Embodiment
With reference to accompanying drawing 1 to a kind of undersampling mixer circuit shown in the accompanying drawing 9, it comprises that sampling control signal generator, the first order are owed sample circuit, second utmost point is owed sample circuit and band pass filter, the sampling control signal generator comprises sample frequency input, d type flip flop or door and not gate, the CLK end of described sample frequency input and d type flip flop, first or door U1A be connected with second or the input of door U1B, the output Q end connection first of d type flip flop or the input of door U1A
The D end of the input of end connection second or door U1B and d type flip flop, the CLR end of d type flip flop is connected power supply with the PR end, first or the door U1A output connect the first not gate U2A, second or the door U1B output connect second not gate, first or the door U1A output be the positive control signal input part fs2 of second level sample circuit, the output of the first not gate U2A is the input nfs2 of the negative control signal of second level sample circuit, second or the door U1B output be the positive control signal input part fs1 of first order sample circuit, the output of the second not gate U2B is the input nfs1 of the negative control signal of first order sample circuit.The positive control signal input part fs1 of described first order sample circuit and the first field effect transistor Q3, the grid of the 3rd field effect transistor Q1 and the 4th field effect transistor Q7 connects, the source electrode of the first field effect transistor Q3 connects treats sampled signal, the drain electrode of the first field effect transistor Q3 connects the positive input terminal and first resistance R 6 of the first amplifier U4A, first resistance R, 6 other end ground connection, the output of the first amplifier U4A connects the negative input end of the first amplifier U4A by second resistance R 2, the first amplifier U4A output connects the drain electrode of the second field effect transistor Q5 by the 3rd resistance R 4, the grid of the second field effect transistor Q5 connects the negative control signal input part that the first order is owed sample circuit, the source ground of the second field effect transistor Q5, the 3rd resistance R 4 is connected with the source electrode of the 3rd field effect transistor Q1, the drain electrode of the 3rd field effect transistor Q1 connects the negative input end of the second amplifier U4B, the grounded drain of the 4th field effect transistor Q7, the source electrode of the 4th field effect transistor Q7 connects the positive input terminal of the second amplifier U4B, the output of the second amplifier U4B is the signal output part vsmp that the first order is owed sample circuit, be connected with first capacitor C 3 between the source electrode of the 4th field effect transistor Q7 and the drain electrode, the output that is connected with second capacitor C, 1, the second amplifier U4B between the negative input end of the second amplifier U4B and the output is connected with the drain electrode of the second field effect transistor Q5 by the 4th resistance R 1.The signal output part Vsmp that the described first order is owed sample circuit is the signal input part that sample circuit is owed in the second level, the signal input part of second utmost point sample circuit connects the source electrode of the 5th field effect transistor Q4, the positive control signal input part of second utmost point sample circuit connects the 5th field effect transistor Q4, the grid of the 7th field effect transistor Q2 and the 8th field effect transistor Q8, the drain electrode of the 5th field effect transistor Q4 connects the drain electrode of the 6th field effect transistor Q6 by the 5th resistance, the grid of the 6th field effect transistor Q6 connects the negative control signal input part of second utmost point sample circuit, the source ground of the 6th field effect transistor Q6, the drain electrode of the 6th field effect transistor Q6 connects the source electrode of the 7th field effect transistor Q2, the source electrode of the 7th field effect transistor Q2 is connected with the negative input end of the 3rd amplifier U5A, the source electrode of the 8th field effect transistor Q8 connects the positive input terminal of the 3rd amplifier U5A, the grounded drain of the 8th field effect transistor Q8, be connected with the 3rd capacitor C 4 between the source electrode of the 8th field effect transistor Q8 and the drain electrode, the output of the 3rd amplifier U5A connects the negative input end of the 3rd amplifier U5A by the 3rd capacitor C 4, the output of the 3rd amplifier U5A is by the drain electrode of the 6th resistance R 3 connections the 6th field effect transistor Q6, and the output of the 3rd amplifier U5A is the signal output part vsmp2 that sample circuit is owed in the second level.The input of the signal output part vsmp2 connecting band bandpass filter of sample circuit is owed in the second level.Described amplifier is AD826 two-way, high speed voltage feedback operational amplifier, is particularly suitable for requiring the application of unity gain stable and high output driving force, as buffering and cable drive etc.The sample frequency input of owing the sampling control signal generator is loaded into the CLK end and first or door U1A and second or the input of door U1B of d type flip flop with square wave, the D end of d type flip flop and d type flip flop
End connects, and the Q end is connected with first or the input of a U1A,
End is connected with second or the input of U1B, first or the positive control signal fs2 of the output output second level sample circuit of door U1A, second or the positive control signal fs1 of the output output first order sample circuit of door U1B, fs1 is output as the negative control signal nfs1 of first order sample circuit after through the second not gate U2B, fs2 is output as the negative control signal nfs2 of second level sample circuit after through the first not gate U2A, according to the characteristic of d type flip flop, when CLK is low level, output Q and
Constant, when CLK was high level, output Q was identical with D end level,
Hold level opposite with D, as shown in Figure 4 Shu Chu the oscillogram of owing sampling control signal fs1, nfs1, fs2 and nfs2.The sampling control signal fs1 that the first order is owed sample circuit is a high level, when nfs1 is low level, the first field effect transistor Q3, the 3rd field effect transistor Q1, the 4th field effect transistor Q7 conducting, the second field effect transistor Q5 ends, the first amplifier U4A finishes and follows function, the second amplifier U4B finishes negative function, the whole first order is owed the variation that sample circuit can be oppositely followed input signal, when sampling control signal fs1 is a low level, when nfs1 is high level, the first field effect transistor Q3, the 3rd field effect transistor Q1, the 4th field effect transistor Q7 ends, the second field effect transistor Q5 conducting, the second amplifier U4B finishes the maintenance function, and the whole first order is owed sample circuit and entered hold mode.Because the aperture time of the sampling of first order sample circuit is very long, the waveform the inside sample phase that causes sampling has a lot of original signal waveforms, therefore need remove this part waveform by second level sample circuit, the sampling control signal fs2 that sample circuit is owed in the second level is a high level, when nfs2 is low level, the 5th field effect transistor Q4, the 7th field effect transistor Q2 and the 8th field effect transistor Q8 conducting, the 6th field effect transistor Q6 ends, the 3rd amplifier U5A finishes reverse one to one effect of amplifying, when sampling control signal fs2 is a low level, when nfs2 is high level, the 5th field effect transistor Q4, the 7th field effect transistor Q2 and the 8th field effect transistor Q8 end, the 6th field effect transistor Q6 conducting, the 3rd amplifier U5A finishes the maintenance function.It is different that the sampling control signal that sample circuit and the first order owe sample circuit is owed in the second level, therefore owing sample circuit in the first local second level of owing the sample circuit maintenance samples, because when the first order is owed sample circuit and is kept during waveform relatively stably, waveform when therefore second utmost point is owed the sample circuit sampling also is stably, and final second output waveform of owing sample circuit also is relatively stably.Second output waveform of owing sample circuit makes output waveform become level and smooth sine wave through band pass filter, this sine wave frequency is compared with input signal change has been taken place, realized the transformation of high-frequency signal to low frequency signal, the frequency of output waveform can satisfy the requirement of the sample frequency of general sampling A, save the manufacturing cost of detection system greatly, and guaranteed the accuracy of detection system.
Be a kind of application of the present utility model as shown in figure 10, signal source produces the sine wave of 20Hz～5MHz, by being added to behind the current-limiting resistance on the measured piece Zx, follow-up voltage detection module and current detection module can detect the pressure drop V on the measured piece Zx and flow through the electric current I of Zx, this V and I are transferred to follow-up mixting circuit, deliver to follow-up ADC again and carry out digital-to-analogue conversion, give CPU the good digital quantity of conversion at last and calculate: Zx=U/I.Here U and I are plural numbers.Will be the phasor of the sinusoidal waveform of time domain conversion frequency domain, a sine wave period will have 16 sampled points at least, and needs the resolution of 16bit, so the signal of 1kHz needs the sample rate of 16kHz at least.Consider from cost and cost performance, what select is the dual-channel audio sampling A of 48kHz, as can be seen, by can only the sample test signal of 48k/16=3kHz of this AD sampling A of reason, then can't sample from the signal of 3KHz～5MHz, a kind of scheme is exactly to improve the sample rate of ADC, satisfy 5MHz and sampling at 16, need the sample rate of 80MHz at least, the 80MHz sample rate can reach on the double channel A C chip market of 16bit precision almost not to be had, even it also is quite high that price is arranged, and, even used this ADC chip, also to require the data throughput of CPU to want high, at least bus speed is greater than 160MHz, and cost is high.The utility model has adopted undersampling mixer circuit, high frequency voltage and high-frequency current are carried out Frequency mixing processing, make its frequency be reduced to 1KHZ, and the amplitude and the phase information that guarantee primary signal are not lost, the ADC chip can be sampled to it, after the sampling, transfer of data to CPU, is obtained to be measured relevant parameter.
Claims (4)
1. undersampling mixer circuit, it is characterized in that: it comprises the sampling control signal generator, the first order is owed sample circuit, sample circuit and band pass filter are owed in the second level, first output of sampling control signal generator connects the signal input end that the first order is owed sample circuit, second output of sampling control signal generator connects the signal input end that sample circuit is owed in the second level, the signal output part that the first order is owed sample circuit is connected with the signal input part that sample circuit is owed in the second level, and the signal output part connecting band bandpass filter of sample circuit is owed in the second level.
2. undersampling mixer circuit according to claim 1, it is characterized in that: described sampling control signal generator comprises sample frequency input, d type flip flop or door and not gate, the CLK end of described sample frequency input and d type flip flop, first or door be connected with second or the input of door, the output Q end connection first of d type flip flop or the input of door
The D end of the input of end connection second or door and d type flip flop, the CLR end of d type flip flop is connected power supply with the PR end, first or the door output connect first not gate, second or the door output connect second not gate, first or the door output be the positive control signal input part of second level sample circuit, the output of first not gate is the input of the negative control signal of second level sample circuit, second or the door output be the positive control signal input part of first order sample circuit, the output of second not gate is the input of the negative control signal of first order sample circuit.
3. undersampling mixer circuit according to claim 1, it is characterized in that: the positive control signal input part of described first order sample circuit and first field effect transistor, the grid of the 3rd field effect transistor and the 4th field effect transistor connects, the source electrode of first field effect transistor connects treats sampled signal, the drain electrode of first field effect transistor connects the positive input terminal and first resistance of first amplifier, the first resistance other end ground connection, the output of first amplifier connects the negative input end of first amplifier by second resistance, the first amplifier output connects the drain electrode of second field effect transistor by the 3rd resistance, the grid of second field effect transistor connects the negative control signal input part of first order sample circuit, the source ground of second field effect transistor, the 3rd resistance is connected with the source electrode of the 3rd field effect transistor, the drain electrode of the 3rd field effect transistor connects the negative input end of second amplifier, the grounded drain of the 4th field effect transistor, the source electrode of the 4th field effect transistor connects the positive input terminal of second amplifier, the output of second amplifier is the signal output part that the first order is owed sample circuit, be connected with first electric capacity between the source electrode of the 4th field effect transistor and the drain electrode, be connected with second electric capacity between the negative input end of second amplifier and the output, the output of second amplifier is connected with the drain electrode of second field effect transistor by the 4th resistance.
4. undersampling mixer circuit according to claim 1, it is characterized in that: the signal output part that the described first order is owed sample circuit is the signal input part that sample circuit is owed in the second level, the signal input part of second utmost point sample circuit connects the source electrode of the 5th field effect transistor, the positive control signal input part of second utmost point sample circuit connects the 5th field effect transistor, the grid of the 7th field effect transistor and the 8th field effect transistor, the drain electrode of the 5th field effect transistor connects the drain electrode of the 6th field effect transistor by the 5th resistance, the grid of the 6th field effect transistor connects the negative control signal input part of second utmost point sample circuit, the source ground of the 6th field effect transistor, the drain electrode of the 6th field effect transistor connects the source electrode of the 7th field effect transistor, the source electrode of the 7th field effect transistor is connected with the negative input end of the 3rd amplifier, the source electrode of the 8th field effect transistor connects the positive input terminal of the 3rd amplifier, the grounded drain of the 8th field effect transistor, be connected with the 3rd electric capacity between the source electrode of the 8th field effect transistor and the drain electrode, the output of the 3rd amplifier connects the negative input end of the 3rd amplifier by the 3rd electric capacity, the output of the 3rd amplifier connects the drain electrode of the 6th field effect transistor by the 6th resistance, and the output of the 3rd amplifier is the signal output part that sample circuit is owed in the second level.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202069244U CN201674464U (en) | 2010-05-28 | 2010-05-28 | Under-sampling frequency mixing circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010202069244U CN201674464U (en) | 2010-05-28 | 2010-05-28 | Under-sampling frequency mixing circuit |
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| CN201674464U true CN201674464U (en) | 2010-12-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841301A (en) * | 2010-05-28 | 2010-09-22 | 常州市同惠电子有限公司 | Undersampling mixer circuit |
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2010
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841301A (en) * | 2010-05-28 | 2010-09-22 | 常州市同惠电子有限公司 | Undersampling mixer circuit |
| CN101841301B (en) * | 2010-05-28 | 2012-07-04 | 常州市同惠电子有限公司 | Undersampling mixer circuit |
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Granted publication date: 20101215 Termination date: 20140528 |