CN201663587U - Transmission interface circuit of single transmission line - Google Patents
Transmission interface circuit of single transmission line Download PDFInfo
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- CN201663587U CN201663587U CN2009202192142U CN200920219214U CN201663587U CN 201663587 U CN201663587 U CN 201663587U CN 2009202192142 U CN2009202192142 U CN 2009202192142U CN 200920219214 U CN200920219214 U CN 200920219214U CN 201663587 U CN201663587 U CN 201663587U
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Abstract
The utility model discloses a transmission interface circuit of a single transmission line, comprising a signal detection circuit, a counter and a single short pulse wave generator, wherein the signal detection circuit detects level conversion of a transmission signal from the single transmission line and generates an enabling signal and a decoding signal corresponding to the transmission signal, the level conversion comprises a first conversion converting from a first level to a second level and a second conversion converting from the second level to the first level, the signal detection circuit can start generating the enabling signal according to the first conversion of the transmission signal, and stop generating the enabling signal within a definite time when the first conversion is not generated any more after the second conversion of the transmission signal, and the signal detection circuit determines a rising edge (or a falling edge) of the decoding signal according to the first conversion of the transmission signal; the counter conducts counting aiming at the rising edge (or the falling edge) of the decoding signal or the first conversion of the transmission signal under the enabling of the enabling signal, and generates the counting output; and the single short pulse wave generator starts generating a short pulse wave according to the enabling signal, and momentarily returns the decoding signal to zero.
Description
Technical field
The utility model relates to a kind of single transmission line transmission interface circuit.
Background technology
Present communication interface such as I2C, SPI among the SMBUS, all needs at least two transmission lines, a data transmission, a transmission clock pulse.If can reach the transmission of data and clock pulse with single transmission line, can reduce the pin number.Therefore, in No. 7127631 case of prior art United States Patent (USP), propose single line sequence transmission mode, it can be used for operator scheme or other parameter state of setting chip inside.The disclosed method of this case as shown in Figure 1, when receiving terminal detects EN/SET signal rising edge, be enabled and begin reception data (shown in waveform Enable), and according to the EN/SET signal and the corresponding decoding signal (shown in the 3rd waveform) that produces, the counter of receiving terminal begins to count (1～n) at the rising edge of EN/SET signal simultaneously.When receiving terminal detects EN/SET signal falling edge, begin to activate timing,, then stop to enable signal Enable, and counting is made zero, and the decoding signal is also got back to low level thereupon if when in the time limit, not detecting a time rising edge.
In the above-mentioned prior art, after arriving the time limit, not only counting makes zero, and the decoding signal is also got back to low level thereupon; But for some application scenario, such arrangement is also unnecessary, even can say unsatisfactory.After arriving the time limit, it is accurate that the decoding signal should rest on any position, can carry out different application by convenient late-class circuit.
Summary of the invention
Because the above, the purpose of this utility model is to overcome the deficiencies in the prior art and defective, proposes a kind of single transmission line transmission interface circuit, and wherein after arriving the time limit, it is accurate that the decoding signal can rest on any position.
According to above-mentioned purpose, with regard to one of them viewpoint speech, the utility model provides a kind of single transmission line transmission interface circuit, comprise: a signal detecting circuit, the accurate conversion in position of the transmission signal that its detecting comes from a single transmission line, generation enables signal and the decoding signal corresponding with this transmission signal, institute's accurate conversion of rheme comprises first conversion that is converted into second standard from first standard and second conversion that is converted into first standard from second standard, wherein this signal detecting circuit according to first conversion of this transmission signal and initial generation this enable signal, stop to produce this when one section given time first conversion does not take place after this transmission signal second conversion again and enable signal, and this signal detecting circuit determines the rising edge of this decoding signal according to first conversion of this transmission signal; One counter enables signal at this and enables down, counts at the rising edge of decoding signal or first conversion of transmission signal, and produces counting output; And single short pulse wave generator, at first produce a short pulse wave according to enabling rising of signal, will decipher that signal is of short duration to make zero.
With regard to another viewpoint speech, the utility model proposes a kind of single transmission line transmission interface circuit, comprise: a signal detecting circuit, the accurate conversion in position of the transmission signal that its detecting comes from a single transmission line, generation enables signal and the decoding signal corresponding with this transmission signal, institute's accurate conversion of rheme comprises first conversion that is converted into second standard from first standard and second conversion that is converted into first standard from second standard, wherein this signal detecting circuit according to first conversion of this transmission signal and initial generation this enable signal, stop to produce this when one section given time first conversion does not take place after this transmission signal second conversion again and enable signal, and this signal detecting circuit determines the falling edge of this decoding signal according to first conversion of this transmission signal; One counter enables signal at this and enables down, counts at the falling edge of decoding signal or first conversion of transmission signal, and produces counting output; And single short pulse wave generator, at first produce a short pulse wave according to enabling rising of signal, will decipher that signal is of short duration to make zero.
In the above-mentioned single transmission line transmission interface circuit, in enabling signal when stopping, the decoding signal can be maintained at high levels or low level.Implement in the kenel for one therein, in enabling signal when stopping, it is accurate and do not change state that the decoding signal can be maintained at its position at that time.
Below by specific embodiment is illustrated in detail, when the effect that is easier to understand the purpose of this utility model, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 shows the waveform of prior art;
Fig. 2 shows waveform of the present utility model;
Fig. 3 is a schematic circuit diagram, shows a hardware embodiment of the present utility model.
Symbol description among the figure
31 signal detecting circuit
35 counters
36 single short pulse wave generators
101 high levels wave bands
102 low level wave bands
The SW switch
Embodiment
See also Fig. 2, operation format of the present utility model at first is described.The single transmission line transmission interface circuit produces according to the rising edge of EN/SET signal and enables signal Enable, and according to the EN/SET signal and the corresponding decoding signal that produces.Comprise counter (holding the back explanation) in the single transmission line transmission interface circuit, its rising edge at the EN/SET signal counts (1～n).When the single transmission line transmission interface circuit detects EN/SET signal falling edge, promptly begin to activate timing, if when in the time limit, not detecting a time rising edge, then stop to enable signal Enable, and counting is made zero.The utility model unlike the prior art be that when enabling signal Enable when stopping, it is accurate and do not need to be returned to low level that the decoding signal can be any position; As shown in the figure, the needs of visual late-class circuit, and order decoding signal rests on high levels 101 or low level 102.
When enabling signal Enable when getting back to high levels once more, single transmission line transmission interface circuit of the present utility model produces the of short duration signal that makes zero, and the decoding signal is returned to low level, no matter and the decoding signal is to rest on high levels 101 or low level 102.So, can guarantee the decoding signal that follow-up generation is correct, and do not deciphered the signal influence of stop place standard originally.
On the hardware, single transmission line transmission interface circuit of the present utility model has various execution modes, all can produce waveform shown in Figure 2.For an embodiment as shown in Figure 3, comprise signal detecting circuit 31, counter 35, single short pulse wave generator 36, and switch SW in the single transmission line transmission interface circuit of the present utility model.The rising edge and the falling edge of signal detecting circuit 31 detecting EN/SET signals cooperate time limit calculator system, produce and enable signal Enable and the decoding signal corresponding with the EN/SET signal.Counter 35 is counted (rising edge that equals to calculate the EN/SET signal in the present embodiment) at the rising edge of decoding signal, and produces counting output.Single short pulse wave generator 36 produces a short pulse wave according to the rising edge that enables signal Enable, and this short pulse wave makes the of short duration conducting of switch SW, will decipher that signal is of short duration to make zero, and switch SW recovery is afterwards opened circuit.So, can produce each waveform among Fig. 2.
Among the above embodiment, the meaning of two standards of height can be exchanged, for example, can change falling edge according to the EN/SET signal produces and enables signal Enable, or, the decoding signal can be the accurate waveform of exchanging (that is its falling edge is corresponding to rising edge of EN/SET signal among Fig. 2) in height position, or comprehensive above both, or the like.
Below at preferred embodiment the utility model is described, just the above for making those skilled in the art be easy to understand content of the present utility model, is not to be used for limiting interest field of the present utility model only.For those skilled in the art, when can within the utility model notion, thinking immediately and various equivalence variation.So all according to a notion of the present utility model and spirit impartial for it a variation or modification, all should be included in the scope of the utility model claims.
Claims (8)
1. a single transmission line transmission interface circuit is characterized in that, comprises:
One signal detecting circuit, the accurate conversion in position of the transmission signal that its detecting comes from a single transmission line, generation enables signal and the decoding signal corresponding with this transmission signal, institute's accurate conversion of rheme comprises first conversion that is converted into second standard from first standard and second conversion that is converted into first standard from second standard, wherein this signal detecting circuit according to first conversion of this transmission signal and initial generation this enable signal, stop to produce this when one section given time first conversion does not take place after this transmission signal second conversion again and enable signal, and this signal detecting circuit determines the rising edge of this decoding signal according to first conversion of this transmission signal;
One counter enables signal at this and enables down, counts at the rising edge of decoding signal or first conversion of transmission signal, and produces counting output; And
Single short pulse wave generator at first produces a short pulse wave according to enabling rising of signal, will decipher that signal is of short duration to make zero.
2. single transmission line transmission interface circuit as claimed in claim 1 is characterized in that, also includes the switch that makes zero, and this switch that makes zero is controlled in the output of wherein aforementioned single short pulse wave generator, will decipher signal and make zero when making zero switch conduction.
3. single transmission line transmission interface circuit as claimed in claim 1 is characterized in that, in the described signal that enables when stopping, this signal detecting circuit will be deciphered signal, and to be maintained at its position at that time accurate and do not change state.
4. single transmission line transmission interface circuit as claimed in claim 1 is characterized in that, when stopping, this signal detecting circuit will be deciphered signal and be maintained high levels in the described signal that enables.
5. a single transmission line transmission interface circuit is characterized in that, comprises:
One signal detecting circuit, the accurate conversion in position of the transmission signal that its detecting comes from a single transmission line, generation enables signal and the decoding signal corresponding with this transmission signal, institute's accurate conversion of rheme comprises first conversion that is converted into second standard from first standard and second conversion that is converted into first standard from second standard, wherein this signal detecting circuit according to first conversion of this transmission signal and initial generation this enable signal, stop to produce this when one section given time first conversion does not take place after this transmission signal second conversion again and enable signal, and this signal detecting circuit determines the falling edge of this decoding signal according to first conversion of this transmission signal;
One counter enables signal at this and enables down, counts at the falling edge of decoding signal or first conversion of transmission signal, and produces counting output; And
Single short pulse wave generator at first produces a short pulse wave according to enabling rising of signal, will decipher that signal is of short duration to make zero.
6. single transmission line transmission interface circuit as claimed in claim 5 is characterized in that, also includes the switch that makes zero, and this switch that makes zero is controlled in the output of wherein aforementioned single short pulse wave generator, will decipher signal and make zero when making zero switch conduction.
7. single transmission line transmission interface circuit as claimed in claim 5 is characterized in that, in the described signal that enables when stopping, this signal detecting circuit will be deciphered signal, and to be maintained at its position at that time accurate and do not change state.
8. single transmission line transmission interface circuit as claimed in claim 5 is characterized in that, when stopping, this signal detecting circuit will be deciphered signal and be maintained high levels in the described signal that enables.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202192142U CN201663587U (en) | 2009-10-10 | 2009-10-10 | Transmission interface circuit of single transmission line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202192142U CN201663587U (en) | 2009-10-10 | 2009-10-10 | Transmission interface circuit of single transmission line |
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| Publication Number | Publication Date |
|---|---|
| CN201663587U true CN201663587U (en) | 2010-12-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009202192142U Expired - Fee Related CN201663587U (en) | 2009-10-10 | 2009-10-10 | Transmission interface circuit of single transmission line |
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| CN (1) | CN201663587U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108075765A (en) * | 2016-11-15 | 2018-05-25 | 财团法人工业技术研究院 | Sensor interface circuit and sensor output adjusting method |
-
2009
- 2009-10-10 CN CN2009202192142U patent/CN201663587U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108075765A (en) * | 2016-11-15 | 2018-05-25 | 财团法人工业技术研究院 | Sensor interface circuit and sensor output adjusting method |
| CN108075765B (en) * | 2016-11-15 | 2021-07-23 | 财团法人工业技术研究院 | Sensor interface circuit and sensor output adjustment method |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101201 Termination date: 20141010 |
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| EXPY | Termination of patent right or utility model |