CN104198814A - Digital phase position checking device by using identical clock source for calibrating sampling time - Google Patents
Digital phase position checking device by using identical clock source for calibrating sampling time Download PDFInfo
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- CN104198814A CN104198814A CN201410459611.2A CN201410459611A CN104198814A CN 104198814 A CN104198814 A CN 104198814A CN 201410459611 A CN201410459611 A CN 201410459611A CN 104198814 A CN104198814 A CN 104198814A
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Abstract
The invention discloses a digital phase position checking device by using an identical clock source for calibrating sampling time. The digital phase position checking device by using the identical clock source for calibrating the sampling time comprises an FPGA (field-programmable gate array) hardware unit used for front-end signal acquisition, a PowerPC microprocessor used for back-end data processing, an SDRAM (synchronous dynamic random access memory) and a FLASH, wherein the FPGA hardware unit is connected with the PowerPC microprocessor through a bus, and the SDRAM and the FLASH are connected with the bus. A synchronous pulse signal receiving interface, an A/D (analog/digital) sampling interface, two parallel FT3 data receiving interfaces and two parallel optical Ethernet data receiving interfaces are arranged at an input end of the FPGA hardware unit. The digital phase position checking device by using the identical clock source for calibrating the sampling time has the advantages of simple structure, convenience in manufacture and high practicality, phase position checking error caused by crystal oscillator error from different clock sources in the prior art can be eliminated, response consistency is guaranteed, and urgent demands of intelligent substations and digital substations on high precision of electrical quantity phase position checking can be satisfied.
Description
Technical field
The present invention relates to the phase place corrector that a kind of intelligent substation and digital transformer substation use, particularly relate to a kind of digitizing phase place corrector of being demarcated sampling instant by same clock source, belong to the checkout equipment field of intelligent substation of electric power system and digital transformer substation.
Background technology
Intelligent substation is indispensable important component part during intelligent grid is built.At present, the development of domestic intelligent substation and digital transformer substation has entered the engineering application stage on a large scale.Along with the large-scale application of electronic mutual inductor, digital collection unit, merge cells, the sampled signal between electrical equipment is changed for optical fiber and digital transmission mode by traditional cable analog quantity transmission mode.Correspondingly, the electric parameters Verification Technology of traditional transformer station has also been proposed to new requirement.
PH phasemeter is the professional instrument that electric system electric energy metrical and relay protection specialty are carried out secondary circuit Site Detection, can be used for detecting relay protection and respectively organizes phase relation between CT, judges that whether electrical wiring mode is correct etc.Traditional PH phasemeter directly accesses analog quantity electric signal and realizes corresponding function, for intelligent substation and digital transformer substation, digitized sampled signal inputs to digitizing PH phasemeter by optical fiber, carries out computing according to corresponding configuration parameter, completes electric parameters check work.
The domestic phase place check equipment that is applicable to intelligent substation and digital transformer substation mainly contains two classes at present.The hardware platform architecture of one class based on single flush bonding processor, can only complete the phase bit check of Ethernet form SMV message, does not possess the phase bit check to FT3 and analog references source; One class is based on FPGA and PowerPC dual processor framework, but FPGA and PowerPC have clock crystal oscillator source separately, and the real-time difference in both precision and response can produce phase place verify error.
Summary of the invention
Fundamental purpose of the present invention is, overcome deficiency of the prior art, a kind of digitizing phase place corrector of being demarcated sampling instant by same clock source is provided, is specially adapted to meet the demand of electric system user for intelligent substation and the detection of digital transformer substation electric parameters.
Technical matters to be solved by this invention is to provide simple in structure, easy to make, the practical digitizing phase place corrector by same clock source demarcation sampling instant, can eliminate the phase place verify error causing because of Crystal Oscillator Errors from different clocks source in prior art, ensure the consistance of response, the high precision an urgent demand of checking for electric parameters phase place to meet intelligent substation and digital transformer substation, and there is the value in industry.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind of digitizing phase place corrector of being demarcated sampling instant by same clock source, comprise the FPGA hardware cell that gathers for front end signal and for the PowerPC of Back end data processing, described FPGA hardware cell is connected by bus with PowerPC; Also comprise the SDRAM and the FLASH that are connected with bus respectively; The input end of described FPGA hardware cell is provided with synchronization pulse receiving interface, A/D Sampling Interface, parallel FT3 data receiver interface and parallel optical fibre Ethernet data receiving interface.
The present invention is further set to: described synchronization pulse receiving interface is 1 tunnel; Described A/D Sampling Interface is 1 tunnel; Described FT3 data receiver interface is 2 tunnels; Described fiber optic Ethernet data receiver interface is 2 tunnels.
The present invention is further set to: described PowerPC is also connected with keyboard with display.
Adopt technique scheme, by the dual processor framework of FPGA hardware cell and PowerPC, FPGA hardware cell is for front end signal collection, is responsible for realizing A/D sampling to reference source, FT3 data receiver, fiber optic Ethernet data receiver etc.; PowerPC is for Back end data processing, be responsible for file system management, packet parsing, software phase-lock loop message disappear tremble, interpolation is synchronous, data operation and man-machine interaction processing etc.Described FPGA hardware cell not only completes simulating signal A/D sampling and FT3 form sampled value phase bit check, complete the data receiver of fiber optic Ethernet simultaneously, ensured that various forms of sampled values complete sampled value collection or reception by the sampling instant of same clock source mark and by same hardware cell.
Compared with prior art, the beneficial effect that digitizing phase place corrector of the present invention has is:
1, completed collection or the reception in reference source, nuclear phase source by same hardware cell.The sampled value signals collecting of form of ownership or reception complete by the FPGA hardware cell with parallel processing capability, have ensured the consistance of multi-form, different channel sample values responses.
2, by the sampling instant in same clock source mark reference source, nuclear phase source, eliminated sampling instant and caused the time error of mark from different clocks source because of Crystal Oscillator Errors.
3, sampled data accurately, in real time.The sampled value signals collecting of form of ownership or reception complete by real-time FPGA hardware cell, have ensured to greatest extent the real-time synchronization performance of sampled data.
So, the digitizing phase place corrector that should demarcate sampling instant by same clock source can facilitate the electric parameters of current intelligent substation and digital transformer substation to detect and check work, the Start-up and Adjustment speed before greatly improving intelligent substation and digital transformer substation and putting into operation.
Foregoing is only the general introduction of technical solution of the present invention, and for clearer understanding technological means of the present invention, below in conjunction with accompanying drawing, the invention will be further described.
Brief description of the drawings
Fig. 1 is the present invention is demarcated the digitizing phase place corrector of sampling instant structural representation by same clock source.
Embodiment
Below in conjunction with Figure of description, the present invention is further illustrated.
As shown in Fig. 1, a kind of digitizing phase place corrector of being demarcated sampling instant by same clock source, comprise the FPGA hardware cell that gathers for front end signal and for the PowerPC of Back end data processing, described FPGA hardware cell is connected by bus with PowerPC; Also comprise liquid crystal display LCD and keyboard that the SDRAM that is connected with bus is respectively connected with FLASH, with PowerPC.
Wherein, the input end of described FPGA hardware cell is provided with 1 road synchronization pulse receiving interface, 1 road A/D Sampling Interface, the parallel FT3 data receiver interface in 2 tunnels and 2 road parallel optical fibre Ethernet data receiving interfaces.
This digitizing phase place corrector adopts the dual processor framework of FPGA hardware cell and PowerPC, and FPGA hardware cell is for front end signal collection, and PowerPC is for Back end data processing, in change prior art, FPGA and PowerPC have the version in clock crystal oscillator source separately, not only complete simulating signal A/D sampling and FT3 form sampled value phase bit check by FPGA hardware cell, complete the data receiver of fiber optic Ethernet simultaneously, ensure that various forms of sampled values complete sampled value collection or reception by the sampling instant of same clock source mark and by same hardware cell, thereby the phase place verify error causing because of Crystal Oscillator Errors from different clocks source in elimination prior art, ensure the consistance of response, the high precision an urgent demand of checking for electric parameters phase place to meet intelligent substation and digital transformer substation.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (6)
1. demarcated the digitizing phase place corrector of sampling instant by same clock source for one kind, comprise the FPGA hardware cell that gathers for front end signal and for the PowerPC of Back end data processing, it is characterized in that: described FPGA hardware cell is connected by bus with PowerPC; Also comprise the SDRAM and the FLASH that are connected with bus respectively; The input end of described FPGA hardware cell is provided with synchronization pulse receiving interface, A/D Sampling Interface, parallel FT3 data receiver interface and parallel optical fibre Ethernet data receiving interface.
2. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described synchronization pulse receiving interface is 1 tunnel.
3. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described A/D Sampling Interface is 1 tunnel.
4. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described FT3 data receiver interface is 2 tunnels.
5. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described fiber optic Ethernet data receiver interface is 2 tunnels.
6. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described PowerPC is also connected with keyboard with display.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410459611.2A CN104198814A (en) | 2014-09-11 | 2014-09-11 | Digital phase position checking device by using identical clock source for calibrating sampling time |
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| CN201410459611.2A CN104198814A (en) | 2014-09-11 | 2014-09-11 | Digital phase position checking device by using identical clock source for calibrating sampling time |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099828A (en) * | 2015-08-25 | 2015-11-25 | 南京理工大学 | High performance network tester and the testing method thereof |
| CN106950526A (en) * | 2017-02-09 | 2017-07-14 | 武汉科技大学 | Protocol converter for DC converter station current transformer digit check |
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| JPH0921835A (en) * | 1995-07-05 | 1997-01-21 | Mitsubishi Heavy Ind Ltd | Voltage phase detection device |
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| CN102128975A (en) * | 2010-12-22 | 2011-07-20 | 四川省电力公司 | Voltage stabilization online monitoring phasor data measurement device and phasor measurement method |
| CN202362383U (en) * | 2011-11-23 | 2012-08-01 | 贵州电力试验研究院 | Phase calibration device of digital substation based on composite sampling |
| CN103543335A (en) * | 2013-10-30 | 2014-01-29 | 国家电网公司 | Method for measuring synchronous phasor |
| CN204086395U (en) * | 2014-09-11 | 2015-01-07 | 国家电网公司 | The digitized phase corrector of sampling instant is demarcated by same clock source |
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2014
- 2014-09-11 CN CN201410459611.2A patent/CN104198814A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| DE3907781A1 (en) * | 1989-03-10 | 1990-09-20 | Battelle Institut E V | Method and device for the digital measurement of phase |
| JPH0921835A (en) * | 1995-07-05 | 1997-01-21 | Mitsubishi Heavy Ind Ltd | Voltage phase detection device |
| CN201740815U (en) * | 2010-06-11 | 2011-02-09 | 中国电力工程顾问集团东北电力设计院 | Synchronous phasor measurement device |
| CN102128975A (en) * | 2010-12-22 | 2011-07-20 | 四川省电力公司 | Voltage stabilization online monitoring phasor data measurement device and phasor measurement method |
| CN202362383U (en) * | 2011-11-23 | 2012-08-01 | 贵州电力试验研究院 | Phase calibration device of digital substation based on composite sampling |
| CN103543335A (en) * | 2013-10-30 | 2014-01-29 | 国家电网公司 | Method for measuring synchronous phasor |
| CN204086395U (en) * | 2014-09-11 | 2015-01-07 | 国家电网公司 | The digitized phase corrector of sampling instant is demarcated by same clock source |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099828A (en) * | 2015-08-25 | 2015-11-25 | 南京理工大学 | High performance network tester and the testing method thereof |
| CN105099828B (en) * | 2015-08-25 | 2018-09-25 | 南京理工大学 | A kind of implementation method of high performance network tester |
| CN106950526A (en) * | 2017-02-09 | 2017-07-14 | 武汉科技大学 | Protocol converter for DC converter station current transformer digit check |
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