CN104198814A - Digital phase position checking device by using identical clock source for calibrating sampling time - Google Patents

Abstract

The invention discloses a digital phase verification device for marking the sampling time by the same clock source, comprising an FPGA hardware unit for front-end signal acquisition and a PowerPC microprocessor for back-end data processing, the FPGA hardware unit and the PowerPC microprocessor The processor is connected through a bus; it also includes SDRAM and FLASH connected to the bus respectively; the input end of the FPGA hardware unit is provided with a synchronous pulse signal receiving interface of one route, an A/D sampling interface of one route, and a parallel FT3 data receiving interface of two routes And 2-way parallel optical fiber Ethernet data receiving interface. It has the advantages of simple structure, convenient manufacture, and strong practicability. It can eliminate the phase calibration error caused by crystal oscillator errors from different clock sources in the prior art, and ensure the consistency of the response to meet the needs of smart substations and digital substations for electrical quantities. The high precision of phase calibration is urgently required.

Description

A digital phase verification device that uses the same clock source to calibrate the sampling time

technical field

The invention relates to a phase verification device used in an intelligent substation and a digital substation, in particular to a digital phase verification device that uses the same clock source to calibrate the sampling time, and belongs to the field of detection equipment for smart substations and digital substations in power systems.

Background technique

Smart substation is an indispensable part of smart grid construction. At present, the development of domestic smart substations and digital substations has entered the stage of large-scale engineering applications. With the large-scale application of electronic transformers, digital acquisition units, and merging units, the sampling signal between electrical equipment has changed from the traditional cable analog transmission method to the optical fiber digital transmission method. Correspondingly, new requirements are also put forward for the traditional substation electrical quantity calibration technology.

The phase meter is a professional instrument for on-site detection of secondary circuits in electric power system electric energy measurement and relay protection. The traditional phase meter is directly connected to the analog electrical signal and realizes the corresponding functions. For the smart substation and the digital substation, the digital sampling signal is input to the digital phase meter through the optical fiber, and the operation is performed according to the corresponding configuration parameters to complete the electrical quantity calibration.

At present, there are mainly two types of phase calibration equipment suitable for smart substations and digital substations in China. A type of hardware platform architecture based on a single embedded processor can only complete the phase verification of SMV messages in the form of Ethernet, and does not have the phase verification of FT3 and analog reference sources; a type based on FPGA and PowerPC dual processor architecture , but FPGA and PowerPC have their own clock crystal oscillator sources, and the real-time difference in precision and response between the two will cause phase calibration errors.

Contents of the invention

The main purpose of the present invention is to overcome the deficiencies in the prior art and provide a digital phase verification device that uses the same clock source to calibrate the sampling time, especially suitable for meeting the needs of power system users for the detection of electrical quantities in smart substations and digital substations.

The technical problem to be solved by the present invention is to provide a digital phase verification device that uses the same clock source to calibrate the sampling time, which has a simple structure, is convenient to manufacture, and has strong practicability. To ensure the consistency of the response, to meet the high-precision requirements of smart substations and digital substations for electrical quantity phase verification, and has industrial application value.

In order to achieve the above object, the technical scheme adopted in the present invention is:

A kind of digitized phase verification device that calibrates the sampling moment by the same clock source, including FPGA hardware unit for front-end signal acquisition and PowerPC microprocessor for back-end data processing, said FPGA hardware unit and PowerPC microprocessor pass bus Connected; also include SDRAM and FLASH connected to the bus respectively; the input end of the FPGA hardware unit is provided with a synchronous pulse signal receiving interface, an A/D sampling interface, a parallel FT3 data receiving interface and a parallel optical fiber Ethernet data receiving interface.

The present invention is further set as: the synchronous pulse signal receiving interface is 1 channel; the A/D sampling interface is 1 channel; the FT3 data receiving interface is 2 channels; the optical fiber Ethernet data receiving interface is 2 channels.

The present invention is further set as: the PowerPC microprocessor is also connected with a display and a keyboard.

Using the above technical solution, through the FPGA hardware unit and the dual-processor architecture of the PowerPC microprocessor, the FPGA hardware unit is used for front-end signal acquisition, responsible for A/D sampling of reference sources, FT3 data reception, optical fiber Ethernet data reception, etc. ; PowerPC microprocessor is used for back-end data processing, responsible for file system management, message analysis, software phase-locked loop message debounce, interpolation synchronization, data calculation and human-computer interaction processing, etc. The FPGA hardware unit not only completes analog signal A/D sampling and FT3 form sampling value phase verification, but also completes the data reception of optical fiber Ethernet, which ensures that various forms of sampling values are marked by the same clock source and sampled by the same clock source. The hardware unit completes the acquisition or reception of sampled values.

Compared with the prior art, the beneficial effects of the digital phase verification device of the present invention are:

1. Acquisition or reception of reference source and nuclear phase source is completed by the same hardware unit. All forms of sampling value signal acquisition or reception are completed by the FPGA hardware unit with parallel processing capabilities, which ensures the consistency of sampling value responses in different forms and channels.

2. The sampling time of the reference source and the nuclear phase source is marked by the same clock source, which eliminates the time error of the sampling time from different clock sources caused by the error of the crystal oscillator.

3. The sampling data is accurate and real-time. All forms of sampling value signal acquisition or reception are completed by the real-time FPGA hardware unit, which ensures the real-time synchronization performance of the sampling data to the greatest extent.

Therefore, the digital phase verification device that uses the same clock source to calibrate the sampling time can facilitate the electrical quantity detection and verification work of the current smart substation and the digital substation, and greatly improve the start-up and debugging speed of the smart substation and the digital substation before they are put into operation.

The above content is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly, the present invention will be further described below in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is a schematic structural diagram of a digitized phase verification device that uses the same clock source to calibrate the sampling time according to the present invention.

Detailed ways

Below in conjunction with accompanying drawing of description, the present invention will be further described.

As shown in Fig. 1, a kind of digitized phase checking device that calibrates the sampling moment by the same clock source includes FPGA hardware unit for front-end signal acquisition and PowerPC microprocessor for back-end data processing, described FPGA hardware unit and The PowerPC microprocessor is connected through the bus; it also includes SDRAM and FLASH connected to the bus, liquid crystal display LCD and keyboard connected to the PowerPC microprocessor.

Wherein, the input end of the FPGA hardware unit is provided with 1-way synchronous pulse signal receiving interface, 1-way A/D sampling interface, 2-way parallel FT3 data receiving interface and 2-way parallel optical fiber Ethernet data receiving interface.

The digital phase verification device adopts a dual-processor architecture of an FPGA hardware unit and a PowerPC microprocessor, the FPGA hardware unit is used for front-end signal acquisition, and the PowerPC microprocessor is used for back-end data processing; FPGA and PowerPC have their own clocks in the prior art The structural form of the crystal oscillator not only completes the analog signal A/D sampling and FT3 form sampling value phase verification through the FPGA hardware unit, but also completes the data reception of optical fiber Ethernet to ensure that all forms of sampling values are sampled by the same clock source. Time and the same hardware unit completes the sampling value acquisition or reception, thereby eliminating the phase calibration error caused by crystal oscillator errors from different clock sources in the prior art, ensuring the consistency of the response, and meeting the needs of smart substations and digital substations for electrical quantities The high precision of phase calibration is urgently required.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the technical content disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes. Technical Essence of the Invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solutions of the present invention.

Claims (6)

1. demarcated the digitizing phase place corrector of sampling instant by same clock source for one kind, comprise the FPGA hardware cell that gathers for front end signal and for the PowerPC of Back end data processing, it is characterized in that: described FPGA hardware cell is connected by bus with PowerPC; Also comprise the SDRAM and the FLASH that are connected with bus respectively; The input end of described FPGA hardware cell is provided with synchronization pulse receiving interface, A/D Sampling Interface, parallel FT3 data receiver interface and parallel optical fibre Ethernet data receiving interface.

2. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described synchronization pulse receiving interface is 1 tunnel.

3. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described A/D Sampling Interface is 1 tunnel.

4. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described FT3 data receiver interface is 2 tunnels.

5. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described fiber optic Ethernet data receiver interface is 2 tunnels.

6. the digitizing phase place corrector of being demarcated sampling instant by same clock source according to claim 1, is characterized in that: described PowerPC is also connected with keyboard with display.