CN201403046Y

CN201403046Y - Parallel connection IGBT difference interface drive unit based on FPGA

Info

Publication number: CN201403046Y
Application number: CN2009201465871U
Authority: CN
Inventors: 于英男; 马惠春; 车向中; 戴碧君
Original assignee: CNR Dalian Electric Traction R& D Center Co Ltd
Current assignee: CRRC Dalian R&D Co Ltd
Priority date: 2008-11-10
Filing date: 2009-04-22
Publication date: 2010-02-10
Anticipated expiration: 2019-04-22

Abstract

The utility model discloses a parallel connection IGBT difference interface drive unit based on FPGA. The drive unit comprises a main control unit, a twisted pair and a gate drive detecting unit, wherein the main control unit is connected to the gate drive detecting unit through the twisted pair; the main control unit consists of a CPU and an FPGA difference generating and receiving unit; the gatedrive detecting unit consists of an FPGA difference generating and receiving unit, a gate drive unit consists of an FPGA difference generating and receiving unit, a gate drive unit and a fault feedback unit; the CPU consists of a minimum control system of DSP240 series; and the FPGA difference generating and receiving unit consists of a minimum control system of XC3S200FPGA. A circuit adopts LVDStechnology and realizes the reliability and real-time property of drive signal transmission. After the difference generating and receiving unit at a drive side receives a difference signal, the difference signal can be converted to a plurality of single-end drive signals to be output. The drive unit can drive a plurality of IGBTs in the form of parallel connection and realize the drive of a high-power IGBT.

Description

Parallel IGBT differential interface driving unit based on FPGA

Technical field

The utility model relates to a kind of high-power IGBT differential interface driving unit, but relates in particular to the parallel IGBT differential interface driving unit based on FPGA of a kind of long-distance transmissions drive signal that is used for traction convertor or AuCT and fault feedback signal etc.

Background technology

In the high-power frequency conversion speed regulating device, because device size is bigger, consider the condition of structure and heat radiation, the pwm signal that digital signal processor DSP produces on the master control borad need just can be delivered in the IGBT inversion unit through long distance.The high-frequency interferencing signal that is produced by the switch motion of IGBT is easy to produce wave distortion in the transmission course of drive signal, thereby influences the operating efficiency of IGBT.And for the parallel IGBT driver element, require the drive signal sent by digital signal processor DSP in real time and synchronous transmission to driving side, the parallel real-time of assurance drive signal.And existing parallel IGBT differential interface driving unit based on digital signal processor DSP and FPGA, what adopt is RS422 data-signal differential transfer mode, belong to a kind of low level balance transmission, its interference free performance is good, can steady operation in the environment of the high voltage of big-power transducer, strong electromagnetic, but the PMW signal is converted into RS422 differential signal standard transmission, the transmission delay effect is apparent in view, transmit on 100 meters long twisted-pair feeders, the transmission time is generally about 100 nanoseconds.For the PWM driving pulse is the transport process of drive plate part from low-voltage control circuit to the high-voltage power circuit, if distance is greater than 1 meter, generally all adopt Optical Fiber Transmission, just use particular device such as optical generator, optical fiber, optical receiver, finish the conversion of " electrical-optical-", Zhuan Huan transmission delay effect is apparent in view like this, and the transmission time is usually to more than 200 nanoseconds.

In sum, there is following problem in prior art:

1,, influenced the reliability and the synchronism of IGBT drive signal transmission because the RS422 signal transmission system has tangible late effect.

2, in the high-power frequency conversion device, need 2 even more IGBT parallel connection usually, and the drive signal of prior art is through after carrying out logical process in the drive plate, draw with rigid line inside, and drive signal is passed through between drive plate and drive plate, cause the unreliable of drive signal, and draw the more hard signal of multiple parallel for high-power needs.

3, because the RS422 signal transmission system is made up of a pair of generation acknowledge(ment) signal chip and transmission medium, then need manyly for multiple signals, both increased the complexity of hardware, also increased cost chip.

Summary of the invention

For overcoming the problems referred to above of prior art, the purpose of this utility model is a kind of high-power, high reliability of design, can be used for the parallel IGBT differential interface driving unit based on FPGA of Locomotive Converter or AuCT cheaply.

Technical solution of the present utility model is achieved in that a kind of parallel IGBT differential interface driving unit based on FPGA, comprise main control unit, twisted-pair feeder and gate driving detecting unit, described main control unit is connected to the gate driving detecting unit by twisted-pair feeder, described main control unit is taken place by CPU and FPGA difference and accepts the unit and form, described gate driving detecting unit is by the generation of FPGA difference and accept the unit, drive element of the grid, the fault feedback unit is formed, described CPU is made up of digital signal processor DSP 240 serial minimum control system, and described FPGA difference takes place and accepts the unit and be made up of the minimum control system of XC3S200FPGA field programmable gate array.

The pin PWM1-PWM6 of CPU described in the utility model with interrupt protection pin PDPINT and link to each other with 7 single-ended I/O of the FPGA of master control side respectively.

The power driving circuit that drive element of the grid described in the utility model is is core with two 2SD315 drive plates, 4 single-ended I/O of unit take place and accept in the FPGA difference that the INA of two 2SD315 drive plates and INB end is connected respectively to driving side through two logical circuits, and the pin SO of two 2SD315 drive plates is connected in series through the FPGA difference generation of level matching circuit and driving side and 1 single-ended I/O accepting the unit.

Twisted-pair feeder described in the utility model is the twisted-pair feeder of the configurable at least LVDS standard signal more than 10 pairs.

Compared with prior art, the beneficial effects of the utility model are as follows:

1, because circuit of the present utility model has adopted the LVDS technology, and the maximum transmission rate of LVDS technology can reach 1.923Gbps, has realized the reliability and the real-time of drive signal transmission.

2, because driving side difference of the present utility model takes place and accepts the unit and accept can be converted into the output of multichannel single-ended drive signal behind one road differential signal, can in parallelly drive a plurality of IGBT, realize the driving of high-power IGBT.

3, since the utility model take place by master control side FPGA difference and accept the multi-channel drive signal that the unit sends, avoid finishing the rigid line expansion of drive signal from drive plate inside, make drive signal all from the Interface Terminal input of drive plate, increased the reliability of high-power driving.

4, because the utility model utilizes the FPGA difference to take place and accepts the configurable multichannel differential signal in unit, realize the differential transfer of drive signal, reduced cost.

Description of drawings

The utility model has 4 accompanying drawings, wherein:

Fig. 1 is based on the parallel IGBT differential interface driving unit schematic flow sheet of FPGA.

Fig. 2 is based on the circuit diagram of the parallel IGBT differential interface driving unit of FPGA.

Be based on Fig. 3 CPU of parallel IGBT differential interface driving unit of FPGA and master control side FPGA difference take place and accept unit connection relation figure.

The annexation figure of unit and 2SD315 drive plate takes place and accepts in the driving side FPGA difference that Fig. 4 is based on the parallel IGBT differential interface driving unit of FPGA.

Among the figure, 1, main control unit, 2, twisted-pair feeder, 3, the gate driving detecting unit.

Embodiment

Below in conjunction with accompanying drawing the utility model is further specified.Shown in Fig. 1-4, a kind of parallel IGBT differential interface driving unit based on FPGA, comprise main control unit 1, twisted-pair feeder 2 and gate driving detecting unit 3, described main control unit 1 is connected to gate driving detecting unit 3 by twisted-pair feeder 2, it is characterized in that: described main control unit 1 is taken place by CPU and FPGA difference and accepts the unit and form, described gate driving detecting unit 3 is by the generation of FPGA difference and accept the unit, drive element of the grid, the fault feedback unit is formed, described CPU is made up of digital signal processor DSP 240 serial minimum control system, and described FPGA difference takes place and accepts the unit and be made up of the minimum control system of XC3S200FPGA field programmable gate array.The pin PWM1-PWM6 of described CPU with interrupt protection pin PDPINT and link to each other with 7 single-ended I/O of the FPGA of master control side respectively.The power driving circuit that described drive element of the grid is is core with two 2SD315 drive plates, 4 single-ended I/O of unit take place and accept in the FPGA difference that the INA of two 2SD315 drive plates and INB end is connected respectively to driving side through two logical circuits, and the pin SO of two 2SD315 drive plates is connected in series through the FPGA difference generation of level matching circuit and driving side and 1 single-ended I/O accepting the unit.Described twisted-pair feeder 2 is twisted-pair feeders 2 of the configurable at least LVDS standard signal more than 10 pairs.

Driving method of the present utility model may further comprise the steps:

A, according to the requirement of IGBT Devices Characteristics and control system, send period register and the comparand register of CPU in needed pulse frequency and the duty ratio configuration main control unit 1, CPU produces 6 tunnel single-ended pwm signals by pin PWM1-PWM6, delivers to master control side FPGA difference and takes place and accept in the unit;

B, master control side FPGA difference take place and accept the unit and accept 6 the I/O end input of 6 road pwm signals through matched level 3.3V, by differential pin output, the FPGA difference of signal being delivered to driving side by twisted-pair feeder 2 and terminal build-out resistor takes place and the differential signal of accepting the unit is accepted pin;

The FPGA difference of C, driving side takes place and accepts the unit and accept differential signal, realize the input of single channel differential signal, produce multichannel IGBT single-ended drive signal simultaneously, and the interlock circuit of process upper and lower bridge arm, deliver to the InA and the InB end of two 2SD315 drive plates more respectively, finish the triggering high-power IGBT;

D, the fault-signal of the SO of two 2SD315 drive plates end output is linked into the single-ended I/O pin of BANK4 through the resistor network of 5V-3.3V; by DCI-P, the output of DCI-N pin difference; the BANK3 difference input pin of unit takes place and accepts in the FPGA difference of delivering to the master control side; output to the inverter of two 5V power supplies by single-ended I/O with BANK; output to the interruption protection pin PDPINT of CPU again; when CPU detects the level variation of PDPINT pin; block pwm pulse, the protection main circuit.

In the utility model when work,, all VCOO of CPU all insert the 3.3V level in the main control unit 1, and the FPGA difference of driving side takes place and the VCCO that accepts the unit all inserts the 3.3V level.And, select the FPGA difference that the quantity of the single-ended I/O mouth of unit takes place and accepts, by single-ended I/O output pwm pulse signal according to the quantity of parallel IGBT.

Claims

1, a kind of parallel IGBT differential interface driving unit based on FPGA, comprise main control unit (1), twisted-pair feeder (2) and gate driving detecting unit (3), described main control unit (1) is connected to gate driving detecting unit (3) by twisted-pair feeder (2), it is characterized in that: described main control unit (1) is taken place by CPU and FPGA difference and accepts the unit and form, described gate driving detecting unit (3) is by the generation of FPGA difference and accept the unit, drive element of the grid, the fault feedback unit is formed, described CPU is made up of digital signal processor DSP 240 serial minimum control system, and described FPGA difference takes place and accepts the unit and be made up of the minimum control system of XC3S200FPGA field programmable gate array.

2, the parallel IGBT differential interface driving unit based on FPGA according to claim 1 is characterized in that: the pin PWM1-PWM6 of described CPU with interrupt protection pin PDPINT and link to each other with 7 single-ended I/O of the FPGA of master control side respectively.

3, the parallel IGBT differential interface driving unit based on FPGA according to claim 1, it is characterized in that: the power driving circuit that described drive element of the grid is is core with two 2SD315 drive plates, 4 single-ended I/O of unit take place and accept in the FPGA difference that the INA of two 2SD315 drive plates and INB end is connected respectively to driving side through two logical circuits, and the pin SO of two 2SD315 drive plates is connected in series through the FPGA difference generation of level matching circuit and driving side and 1 single-ended I/O accepting the unit.

4, the parallel IGBT differential interface driving unit based on FPGA according to claim 1 is characterized in that: described twisted-pair feeder (2) is the twisted-pair feeder (2) of the configurable at least LVDS standard signal more than 10 pairs.