CN105807675A - Dual-core processor-based rail transit converter control unit - Google Patents
Dual-core processor-based rail transit converter control unit Download PDFInfo
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- CN105807675A CN105807675A CN201410845385.1A CN201410845385A CN105807675A CN 105807675 A CN105807675 A CN 105807675A CN 201410845385 A CN201410845385 A CN 201410845385A CN 105807675 A CN105807675 A CN 105807675A
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Abstract
The invention discloses a dual-core processor-based rail transit converter control unit, which comprises more than one dual-core processor, a field programmable gate array (FPGA) and a complex programmable logic device (CPLD). The dual-core processor comprises a DSP core and an ARM core. The DSP core is used for implementing the real-time algorithm control. The ARM core is used for realizing the logic control and the communication with the outside. The FPGA is used for calculating the speed and generating a PWM latch pulse, and serves as an intermediate station for the data transmission between the CPLD and the dual-core processor. The CPLD is used for controlling the AD conversion and managing input and digital input and output control signals. The CPLD and the FPGA are directly connected via an I/O port, so that the data transmission between the CPLD and the FPGA is realized. The high-speed data transmission between the FPGA and the dual-core processor is realized via a universal parallel interface, namely a uPP interface. The dual-core processor-based rail transit converter control unit has the advantages of small volume, higher operation speed, optimized overall performance, and the like.
Description
Technical field
Present invention relates generally to current transformer control field, refer in particular to a kind of track traffic current transformer control unit based on dual core processor.
Background technology
At present, existing track traffic converter control system is generally adopted DSP+FPGA pattern, belongs to single core processor system, and wherein FPGA is field programmable gate array, and DSP is digital signal processor.Although the mathematical operation that DSP is powerful and processing capability in real time and the efficient mass data operating capability of FPGA bring out the best in each other, but still unavoidably have some shortcoming.Needing to carry out the industrial Variable flow control field of algorithm controls and logic control, algorithm controls and logic control are all realized by DSP, and namely within a calculating cycle, DSP should carry out algorithm computing, carries out logic control again simultaneously.This is to algorithm computing for core, having the industrial Variable flow control system of significantly high requirement of real-time, and logic control occupies certain clock sources, extends the calculating cycle, have impact on the efficiency of system and performance.
Conventional a kind of settling mode is to use two different device dsp chips and ARM chip, carries out algorithm controls and logic control respectively by dsp chip and ARM chip, the problem that thus can solve above-mentioned calculating cycle stretch-out, but adds chip number.And in the single core processor framework of DSP+ARM+FPGA, the data transmission between DSP and FPGA is generally adopted external memory interface EMIF mode or dual port RAM mode.If adopting dual port RAM data transfer mode, it is necessary to special dual port RAM chip.Along with the increase of number of chips, force control unit printed board area to increase on the one hand, add the complexity of external circuit on the other hand.
Summary of the invention
The technical problem to be solved in the present invention is that for the technical problem that prior art exists, and the present invention provides that a kind of volume is little, can improve arithmetic speed, optimizes the track traffic current transformer control unit based on dual core processor of overall performance.
For solving above-mentioned technical problem, the present invention by the following technical solutions:
A kind of track traffic current transformer control unit based on dual core processor, including more than one dual core processor, FPGA and CPLD, described dual core processor includes DSP core and ARM core, and described DSP core is used for realizing real time algorithm control, and described ARM core is used for realizing logic control and externally communication；Described FPGA is used for carrying out speed calculation and pwm pulse latch generation, and as the intermediate station of described CPLD with the transmission of described dual core processor data；Described CPLD is controlled for AD is converted, and digital IO control signal is managed；It is joined directly together by I/O mouth between described CPLD and described FPGA and carries out data transmission, between described FPGA and described dual core processor, carry out high speed data transfer by universal parallel interface uPP interface.
In said structure, ARM core and DSP core share memory ram, ARM core and DSP core carry out efficient data interaction by sharing RAM, thus avoiding the time setting up interruption in monokaryon system for processing logic control signal in dsp, substantially increase the execution efficiency of real time algorithm, take full advantage of clock sources, arithmetic speed can be improved, promote real-time.Because algorithm controls and logic control are completed by two separate units of same device respectively, no matter ARM core and DSP core are to share a clock signal, or adopt the asynchronous system using different clock signals, because the independence on hardware, two class control tasks can executed in parallel, running can discharge clock sources, shorten the calculating cycle of system, it is ensured that processor is efficiently completed control task.
As a further improvement on the present invention, also include A/D sampling unit, be used for gathering voltage, electric current, temperature analog signal, and these signals are carried out A/D conversion, voltage after conversion, current signal will participate in unsteady flow real time algorithm and control, and temperature signal will participate in logic control.
As a further improvement on the present invention, also include rate signal to receive and delivery unit, being used for sending rate signal to described FPGA to be calculated, the velocity amplitude after calculating is sent to the DSP core of described dual core processor and participates in the control of unsteady flow real time algorithm by described FPGA.
As a further improvement on the present invention, also include described digital controlled signal input-output unit, it is used for through the described CPLD described ARM core being sent to described dual core processor, the digital controlled signal of externally input is participated in logic control, described ARM core produces digital control output signal, externally export through described CPLD, control the break-make of switching device of outside convertor equipment to realize logic control.
As a further improvement on the present invention, the described DSP core of described dual core processor generates pwm pulse by unsteady flow real time control algorithms, and the pwm pulse of generation is sent to after described FPGA latches and exports by described DSP core.
In aforesaid way, carry out speed calculation by FPGA and pwm pulse latches and generates, FPGA has the advantage that capability of sequential control is strong and register number is many, intrinsic advantage can be given full play to, the high speed signals such as processing speed pulse signal and pwm pulse signal, accurately calculate speed pulse signal, undertaken latching then exporting by the multi-channel PWM pulse signal that DSP generates, improve the accuracy controlled in real time and the reliability of PWM control.Cross CPLD and carry out A/D management conversion, can not be limited by the dominant frequency of processor chip, the A/D clock signal of conversion can being provided by CPLD self, carrying out A/D conversion and control independently, thus improve the speed of sampling.
As a further improvement on the present invention, universal parallel interface uPP is adopted to carry out high speed data transfer between described FPGA and described dual core processor.Described uPP interface includes two dma module passages: the first DMA channel and the second DMA channel；Described first DMA channel is used for sending data to processor cache unit, and described second DMA channel is used for receiving data to realize the bidirectional high speed parallel transmission of data from processor cache unit.
Compared with prior art, it is an advantage of the current invention that:
1, the track traffic current transformer control unit based on dual core processor of the present invention, two cores of dual core processor realize difference in functionality respectively, the task division of labor is clear, respectively take the chief, carry out data transmission on backstage between dinuclear, it is to avoid monokaryon system is set up for processing logic control signal the time of interruption in dsp, substantially increase the execution efficiency of real time algorithm, take full advantage of clock sources, arithmetic speed can be improved, promote real-time.
2, the track traffic current transformer control unit based on dual core processor of the present invention, algorithm controls and logic control are completed by two separate units of same device respectively, no matter ARM core and DSP core are to share a clock signal, or adopt the asynchronous system using different clock signals, because the independence on hardware, two class control tasks can executed in parallel, running can discharge clock sources, the calculating cycle of shortening system, it is ensured that processor is efficiently completed control task.
3, the track traffic current transformer control unit based on dual core processor of the present invention, owing to decreasing the quantity of chip, it is possible to make control unit printed board area reduce, control device more light small and exquisite, and the reduction of external circuit complexity, the overall performance of control unit can be made to be improved.
4, the track traffic current transformer control unit based on dual core processor of the present invention, universal parallel interface uPP can be adopted between double-core device and FPGA to carry out data transmission, the speed of data transmission can be greatly improved, increase the reliability of data transmission so that control system and can process more real time data.
5, the track traffic current transformer control unit based on dual core processor of the present invention, utilize the advantage that FPGA capability of sequential control is strong and register number is many, can accurately calculate speed pulse signal, the latch of pwm pulse can be carried out, improve the accuracy of real time algorithm control and the reliability of PWM control.
6, the track traffic current transformer control unit based on dual core processor of the present invention, carry out A/D management conversion by CPLD, can not be limited by the dominant frequency of processor chip, the A/D clock signal of conversion can be provided by CPLD self, carry out A/D conversion and control independently, thus improve the speed of sampling.
Accompanying drawing explanation
Fig. 1 is the topological structure schematic diagram of track traffic current transformer control unit of the present invention.
Fig. 2 is the uPP interface data transmission schematic diagram of track traffic current transformer control unit of the present invention.
Fig. 3 is present invention topological structure schematic diagram in another concrete application example.
Marginal data:
1, ARM core；2, DSP core；3, dual core processor；4, the first dual core processor；5, the second dual core processor；6, rate signal receives and delivery unit；7、FPGA；8、CPLD；9, A/D sampling unit；10, digital controlled signal input-output unit；11, pwm pulse level conversion and output unit；12, uPP interface；13, the first DMA channel；14, the second DMA channel；15, processor cache unit.
Detailed description of the invention
Below with reference to Figure of description and specific embodiment, the present invention is described in further details.
As it is shown in figure 1, the track traffic current transformer control unit based on dual core processor of the present invention, including dual core processor 3, FPGA7 and CPLD8.Dual core processor 3 has DSP core 2 and ARM core 1, ARM core 1 primary responsibility realizes logic control and external communication, DSP core 2 be then absorbed in realize unsteady flow real time algorithm control.FPGA7 is used for carrying out speed calculation and pwm pulse latch generation, and as the intermediate station of CPLD8 with the transmission of dual core processor 3 data；CPLD8 is controlled for AD is converted, and digital IO control signal is managed；It is joined directly together by I/O mouth between CPLD8 and FPGA7 and carries out data transmission, between FPGA7 and dual core processor 3, carry out high speed data transfer by universal parallel interface uPP interface 12.
In said structure, ARM core 1 and DSP core 2 share memory ram, ARM core 1 and DSP core 2 carry out efficient data interaction by sharing RAM, thus avoiding the time setting up interruption in monokaryon system for processing logic control signal in dsp, substantially increase the execution efficiency of real time algorithm, take full advantage of clock sources, arithmetic speed can be improved, promote real-time.Because algorithm controls and logic control are completed by two separate units of same device respectively, no matter ARM core 1 and DSP core 2 are to share a clock signal, or adopt the asynchronous system using different clock signals, because the independence on hardware, two class control tasks can executed in parallel, running can discharge clock sources, shorten the calculating cycle of system, it is ensured that processor is efficiently completed control task.
In the present embodiment, present invention additionally comprises A/D sampling unit 9, it is used for gathering the analogue signals such as the voltage of external sensor input, electric current, temperature, and under the control of CPLD8, carry out A/D conversion, then being sent to dual core processor 3 through FPGA7, the voltage after wherein converting, current signal are sent to DSP core 2 and directly participate in real time algorithm control, and temperature signal is then mainly sent to ARM core 1 and participates in logic control.
In the present embodiment, present invention additionally comprises rate signal to receive and delivery unit 6, be used for receiving the rate signal of external speed sensor input, and rate signal is transmitted directly to FPGA7 is calculated, obtain velocity amplitude, be then passed to DSP core 2 and participate in real time algorithm control.DSP core 2 will be sent in FPGA7 by the pwm pulse that real time algorithm generates and latch, be then retransmitted to pwm pulse level conversion and output unit 11 carry out level conversion after externally export, drive the IGBT constant power device of outside current transformer, and then realize the purpose of unsteady flow.
In the present embodiment, present invention additionally comprises digital controlled signal input-output unit 10, be used for the numerical control instruction signal of externally input is sent to CPLD8, be sent to ARM core 1 through FPGA7 after carrying out logical process in CPLD8, participate in logic control.ARM core 1 makes logical judgment and process according to the external digital control instruction received and current current transformer state, produce numeral output control signal, externally exporting after FPGA7 and CPLD8, controlling the switching device break-makes such as the outside chopper of convertor equipment, catalyst, thus realizing logic control.
In the present embodiment, the ARM core 1 in the present invention carries out communication from outside network device with different interface modes also by the multiple interfaces that processor self is integrated, it is achieved more higher leveled data interaction.
As in figure 2 it is shown, in the present embodiment, the universal parallel interface uPP data transmission adopted between FPGA7 and dual core processor 3.The data transmission of uPP interface 12 is directly processor cache unit 15 to be conducted interviews by the dma module within uPP interface 12.Two dma module passages are included: the first DMA channel 13 and the second DMA channel 14 in uPP interface 12.First DMA channel 13 is used for sending data to processor cache unit 15, and the second DMA channel 14 is used for receiving data from processor cache unit 15.The two-way simultaneous data transmission sending data with receiving data can be realized.Simultaneously as dma module is direct access process device buffer unit 15, so data transmission bauds is quickly, it is possible to achieve the purpose of mass data high-speed transfer, substantially increase the real-time of Variable flow control unit.
As it is shown on figure 3, the needs according to practical application, plural dual core processor can also be adopted in other embodiments, namely include the first dual core processor 4 and the second dual core processor 5, to realize more powerful control ability.
Protection scope of the present invention is not limited merely to above-described embodiment, and all technical schemes belonged under thinking of the present invention belong to protection scope of the present invention.It should be pointed out that, for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be regarded as protection scope of the present invention.
Claims (7)
1. the track traffic current transformer control unit based on dual core processor, it is characterized in that, including more than one dual core processor (3), FPGA(7) and CPLD(8), described dual core processor (3) includes DSP core (2) and ARM core (1), described DSP core (2) is used for realizing real time algorithm control, and described ARM core (1) is used for realizing logic control and externally communication；Described FPGA(7) be used for carrying out speed calculation and pwm pulse and latch and generate, and as described CPLD(8) with the intermediate station of described dual core processor (3) data transmission；Described CPLD(8) it is controlled for AD is converted, digital IO control signal is managed；Described CPLD(8) and described FPGA(7) between be joined directly together by I/O mouth and to carry out data transmission, described FPGA(7) and described dual core processor (3) between carry out high speed data transfer by universal parallel interface uPP interface (12).
2. the track traffic current transformer control unit based on dual core processor according to claim 1, it is characterized in that, also include A/D sampling unit (9), for gathering voltage, electric current, temperature analog signal, and these signals are carried out A/D conversion, voltage after conversion, current signal will participate in unsteady flow real time algorithm and control, and temperature signal will participate in logic control.
3. the track traffic current transformer control unit processed based on double-core according to claim 1, it is characterized in that, also include rate signal to receive and delivery unit (6), it is used for sending rate signal to described FPGA(7) be calculated, described FPGA(7) velocity amplitude after calculating is sent to the DSP core (2) of described dual core processor (3) participate in unsteady flow real time algorithm and control.
4. the track traffic current transformer control unit based on dual core processor according to claim 1, it is characterized in that, also include described digital controlled signal input-output unit (10), it being used for the digital controlled signal of externally input through described CPLD(8) the described ARM core (1) that be sent to described dual core processor (3) participate in logic control, described ARM core (1) produces digital control output signal, through described CPLD(8) externally export, control the break-make of switching device of outside convertor equipment to realize logic control.
5. the track traffic current transformer control unit based on dual core processor according to any one in Claims 1 to 4, it is characterized in that, the described DSP core (2) of described dual core processor (3) by unsteady flow real time control algorithms generate pwm pulse, the pwm pulse of generation is sent to described FPGA(7 by described DSP core (2)) latch after output.
6. the track traffic current transformer control unit based on dual core processor according to any one in Claims 1 to 4, it is characterised in that described uPP interface (12) includes two dma module passages: the first DMA channel (13) and the second DMA channel (14)；Described first DMA channel (13) is used for sending data to processor cache unit (15), and described second DMA channel is used for receiving data to realize the bidirectional high speed parallel transmission of data from processor cache unit (15).
7. the track traffic current transformer control unit based on dual core processor according to any one in Claims 1 to 4, it is characterized in that, described ARM core (1) and DSP core (2) are shared memory ram, described ARM core (1) and DSP core (2) and are carried out efficient data interaction by sharing RAM.
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| CN201410845385.1A CN105807675A (en) | 2014-12-31 | 2014-12-31 | Dual-core processor-based rail transit converter control unit |
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| CN201410845385.1A CN105807675A (en) | 2014-12-31 | 2014-12-31 | Dual-core processor-based rail transit converter control unit |
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| CN111767020A (en) * | 2020-05-18 | 2020-10-13 | 深圳市东微智能科技股份有限公司 | Method, device and terminal for optimizing audio processing and readable storage medium |
| CN116360397A (en) * | 2023-03-28 | 2023-06-30 | 中国电力科学研究院有限公司 | Whole vehicle control system and method for new energy rail locomotive |
| CN116974233A (en) * | 2023-09-19 | 2023-10-31 | 西安热工研究院有限公司 | Dual-channel Profibus-DP master station system and design method |
| CN111767020B (en) * | 2020-05-18 | 2024-05-17 | 深圳市东微智能科技股份有限公司 | Optimized audio processing method, device, terminal and readable storage medium |
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