CN201392832Y - Improved SOT encapsulation structure - Google Patents
Improved SOT encapsulation structure Download PDFInfo
- Publication number
- CN201392832Y CN201392832Y CN200920036274U CN200920036274U CN201392832Y CN 201392832 Y CN201392832 Y CN 201392832Y CN 200920036274 U CN200920036274 U CN 200920036274U CN 200920036274 U CN200920036274 U CN 200920036274U CN 201392832 Y CN201392832 Y CN 201392832Y
- Authority
- CN
- China
- Prior art keywords
- chip
- inner lead
- encapsulation structure
- dao
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to an improved SOT encapsulation structure which has strong performance stability and low manufacturing cost and can meet the development requirements on miniaturization and micromation in the electronic industry. The structure comprises a base island, an inner lead and a chip, wherein one chip is arranged on the base island. The structure is characterized in that the inner lead is placed with one chip, and an inner lead wire is connected with the chip and the island on the inner lead.
Description
(1) technical field
The utility model relates to integrated circuit encapsulation technology field, is specially a kind of SOT encapsulating structure of multicore sheet.
(2) background technology
Existing SOT (small outline transistor) encapsulating structure, see Fig. 1, it places a chip 2 on basic island 1, when it needs two kinds of chip portfolios, prior art is that two chip blocks are encapsulated in respectively on two the device, and so latter two device connects by aerial lug, and its stability is not strong, the manufacturing cost height, and can not satisfy electron trade miniaturization, microminiaturized growth requirement.
(3) utility model content
At the problems referred to above, the utility model provides a kind of follow-on SOT encapsulating structure, and its stability is strong, low cost of manufacture, and it can satisfy the growth requirement of electron trade miniaturization, microminiaturization.
A kind of follow-on SOT encapsulating structure, its technical scheme is such: its bag Ji Dao, interior pin, chip, be placed with a chip on the described Ji Dao, it is characterized in that: pin is placed with a chip in described, and lead connects chip and the described Ji Dao on the described interior pin.
In the said structure of the present utility model, because pin is placed with a chip in described, lead connects chip and the described Ji Dao on the described interior pin, because it is installed in two chips that are associated on the plastic-sealed body, the stability of its performance is enhanced, it is reduced to a plastic-sealed body by two original plastic-sealed bodies, so its manufacturing cost is reduced, and it satisfies electron trade miniaturization, microminiaturized growth requirement.
(4) description of drawings
Fig. 1 is the schematic diagram of prior art SOT encapsulating structure front view;
Fig. 2 is the left view of the utility model front view.
(5) embodiment
See Fig. 2, it wraps basic island 1, interior pin 2, chip 3, is placed with a chip 3 on the basic island 1, and interior pin 2 is placed with a chip 4, chip 4 and basic island 1 in lead 5 connects on the pin.
Claims (1)
1, a kind of follow-on SOT encapsulating structure, its bag Ji Dao, interior pin, chip are placed with a chip on the described Ji Dao, and it is characterized in that: pin is placed with a chip in described, and lead connects chip and the described Ji Dao on the described interior pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200920036274U CN201392832Y (en) | 2009-03-09 | 2009-03-09 | Improved SOT encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200920036274U CN201392832Y (en) | 2009-03-09 | 2009-03-09 | Improved SOT encapsulation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201392832Y true CN201392832Y (en) | 2010-01-27 |
Family
ID=41599653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200920036274U Expired - Lifetime CN201392832Y (en) | 2009-03-09 | 2009-03-09 | Improved SOT encapsulation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201392832Y (en) |
-
2009
- 2009-03-09 CN CN200920036274U patent/CN201392832Y/en not_active Expired - Lifetime
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201838584U (en) | Encapsulated triode | |
| CN102437134B (en) | Ultra-small packing body and production method thereof | |
| CN201392832Y (en) | Improved SOT encapsulation structure | |
| CN201392823Y (en) | Multi-chip double-base island SOT encapsulation structure | |
| CN202712172U (en) | Multi-chip dual-base island SOP package structure | |
| CN204289421U (en) | Air-tightness two-chamber encapsulating structure | |
| CN101504942A (en) | Improved SOT encapsulation structure | |
| CN202461257U (en) | Stamping die Male die punch of four-side pins of high-precision integrated circuit | |
| CN204216030U (en) | A kind of encapsulation triode | |
| CN203503695U (en) | Novel structure of direct inserting LED | |
| CN101504941A (en) | Improved SOT encapsulation structure for multi-chip dual basement | |
| CN207719196U (en) | A kind of HZIP25 encapsulating leads | |
| CN103617965B (en) | A kind of external form has the flat integrated circuit package structure of lead | |
| CN202067792U (en) | Semiconductor chip and memory device | |
| CN202352651U (en) | Packaging structure of solid state disk (SSD) | |
| CN102231371A (en) | Semiconductor chip and storage device | |
| CN202487575U (en) | Composite diode structure | |
| CN202127013U (en) | Semiconductor lead frame of whole substrate surface | |
| CN204167636U (en) | The black colloid of a kind of mobile phone USB flash disk | |
| CN203596032U (en) | Stepped Active SIM full-featured card | |
| CN203617274U (en) | Lead frame for low-power devices | |
| CN201838583U (en) | Surface mount type lead pair | |
| CN204885127U (en) | Novel TSOP packaging structure | |
| CN204966492U (en) | Packaging structure of miniature SD card | |
| CN202461299U (en) | Female mold punching head of punching mold for both-side J-shaped pins of high-precision integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100127 |