CN201364724Y - Programmable voltage source of time division multiplex output - Google Patents
Programmable voltage source of time division multiplex output Download PDFInfo
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- CN201364724Y CN201364724Y CNU2009200958316U CN200920095831U CN201364724Y CN 201364724 Y CN201364724 Y CN 201364724Y CN U2009200958316 U CNU2009200958316 U CN U2009200958316U CN 200920095831 U CN200920095831 U CN 200920095831U CN 201364724 Y CN201364724 Y CN 201364724Y
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Abstract
The utility model relates to a programmable voltage source of time division multiplex output, which can be used for gamma correction of LCD, LCoS and the like. A gamma correction circuit of the present LCD adopts the design of a discrete device or a monolithic integrated circuit; although multi-path reference voltage can be generated, the design of the circuit is complicated, the system occupying area is large, the power consumption is high, and debugging and energy saving are unfavorable. The programmable voltage source comprises the following five parts: a programmable interface controller, a 2<M> channel data register, a 2<M-1> channel multi-path selector, a 2<M-1> channel digital-to-analogy converter, a 2<M-1> channel buffer and the like which are integrated together and output 2<M-1> path reference voltage. The time division multiplex function output by the programmable voltage source can be realized according to the changing of external output VCOM signals. The programmable voltage source can optimize the gamma correction circuit of an LCD system, reduce the cost, power consumption as well as area of the LCD system, and realize a programmable voltage source chip of the time division multiplex output.
Description
[technical field]:
The utility model belongs to technical field of liquid crystal display, relates to a kind of 26S Proteasome Structure and Function of programmable voltage source, particularly has the function of time division multiplex output, can be used for the gamma correction of LCD such as LCD, LCoS.
[background technology]:
LCD has become the display of modern main, and it has occupied the status of governance property in flat-panel monitor.In liquid crystal display device, show and the gamma rectification of vision signal, all need peripheral circuit to provide a plurality of reference voltages to liquid crystal display device for the multi-stage grey scale of realizing image.Say the two kinds of methods that mainly contain from the mode that produces reference voltage: separation circuit method and monolithic integrated power supply method.The separation circuit method is to adopt the separation circuit design to produce reference voltage, and this need design the precision resistance network and a plurality of operational amplifier is formed the buffering output circuit, circuit design more complicated like this, and voltage accuracy is not high, and the volume and the power consumption of system are big; Monolithic integrated power supply method is to adopt the design of single-chip integrated power supply to produce reference voltage, produce 2
MIndividual reference voltage needs the single-chip integrated power supply to have 2
MIndividual output port.By analysis, in liquid crystal display, positive and negative of LCD then needs different reference voltages, and does not need to provide simultaneously positive and negative reference voltage.Though now the single-chip integrated power supply on the market can produce the multichannel reference voltage, all can not realize the time division multiplex exported, chip area and power consumption are also relatively large.Therefore inventing a kind of output can time-multiplexed programmable power supply, can reduce the chip area of programmable power supply, reduces power consumption, reduces cost.But still there is not this output device that the programmable voltage source of time-division multiplexing function is arranged both at home and abroad at present.
[utility model content]:
The utility model purpose is to overcome the prior art above shortcomings, and a kind of programmable voltage source of time division multiplex output is provided, and makes this voltage source provide reference voltage for the LCD of various display modes.
The programmable voltage source of the time division multiplex output that the utility model provides comprises:
DLL (dynamic link library) controller: link to each other with the outer CPU interface by bus, by M bit address line and N bit data bus and 2
MChannel data register links to each other, wherein, and 1≤M≤6,1≤N≤16; Be used to receive the programming protocol signal of outer CPU, the externally effect of clock Clk down and under the control of home address controller, order will be user configured write 2 by the outer CPU data of importing of programming
MEach data register in the channel data register;
2
MChannel data register: link to each other with the DLL (dynamic link library) controller with the N bit data bus by M bit address line; Be used to deposit by the DLL (dynamic link library) controller and write 2 respectively
MData in each data register in the channel data register by user configured outer CPU programming input;
2
M-1The passage MUX: the MUX of each passage links to each other with the output of the data register of two different passages by the 2N position datawire, by 2
M-1The selection control end SEL of passage MUX connects the V of outside input
COMSignal is according to V
COMOutput 2 is selected in the saltus step of signal
MChannel data register DR1～DR2
MIn different 2
M-1Data in the individual passage;
2
M-1The port number weighted-voltage D/A converter: the digital to analog converter of each passage links to each other with the output of a MUX of respective channel by the N position datawire, realizes by 2
M-1The digital-to-analog conversion of the data of passage MUX output;
2
M-1Channel buffer: the input end of each channel buffer links to each other with the output of the digital to analog converter of respective channel, is used to stablize 2
M-1The output of port number weighted-voltage D/A converter, the driving force of raising digital to analog converter.
Wherein, described DLL (dynamic link library) controller inside is made up of time schedule controller, address generator circuit.
Described 2
MChannel data register is 2
MThe N bit data register of passage is respectively the 1st channel data register to the 2
MChannel data register; M bit address and 2
MThe relation of each data register in the channel data register is: 0 ... 000 is configuration the 1st channel data register DR1,0 ... 001 is configuration the 2nd channel data register DR2, by that analogy, and 1 ... 110 are configuration the 2nd
M-1 channel data register DR2
M-1,1 ... 111 are configuration the 2nd
MChannel data register DR2
M
Described 2
M-1The passage MUX is by 2
M-1Individual 2N selects n-selector and 2
M-1Individual N position latch is formed; According to V
COMThe saltus step of signal is by 2
M-1The passage MUX is selected output 2
MChannel data register DR1～DR2
MIn 2
M-1Data in the individual channel data register, and latch in 2
M-1In the N position latch of passage.
Described 2
M-1The port number weighted-voltage D/A converter is by 2
M-1The N figure place weighted-voltage D/A converter of passage is formed; Be used to realize 2
M-1The digital-to-analog conversion of the N position latch output data of passage.
Described 2
M-1Channel buffer is by 2
M-1The rail-to-rail operational amplifier of passage is formed; Be used to stablize 2
M-1The output of port number weighted-voltage D/A converter, the driving force of raising digital to analog converter.
The utility model adopts fully integrated method for designing, DLL (dynamic link library) controller, multichannel data register, hyperchannel MUX, hyperchannel digital to analog converter, multiple channel buffer are integrated, be designed to the programmable voltage source chip of time division multiplex output.Be characterized in that the chip layout area is little, low in energy consumption, and realize the time-division multiplexing function of programmable voltage source output.
Advantage of the present utility model and good effect:
The programmable voltage source of the time division multiplex output that the utility model provides can be according to the needs of LCD, and time division multiplex output is applicable to 2 of positive and negative gamma correction of LCD
MIndividual reference voltage.The area of programmable power supply be can reduce, power consumption and production cost reduced; Can make the circuit compactedness of liquid crystal display systems higher, power consumption is lower, it is convenient to dispose and debug.
[description of drawings]:
Fig. 1 is the programmable voltage source structured flowchart;
Fig. 2 is 2
MThe channel data register structured flowchart;
Fig. 3 is 2
M-1Passage MUX structured flowchart;
Fig. 4 is 2
M-1Port number weighted-voltage D/A converter structured flowchart;
Fig. 5 is 2
M-1The channel buffer structured flowchart.
[embodiment]:
Embodiment 1:
As shown in Figure 1, the programmable voltage source of this time division multiplex output, it comprises DLL (dynamic link library) controller 1,2
M Channel data register 2,2
M-1 Passage MUX 3,2
M-1Port number weighted-voltage D/A converter 4,2
M-1Channel buffer 5, wherein 1≤M≤6 are characterized in that the chip layout area is little, low in energy consumption, and realize programmable voltage source output time-division multiplexing function.
DLL (dynamic link library) controller 1: DLL (dynamic link library) controller inside is made up of time schedule controller, address generator circuit; The DLL (dynamic link library) controller links to each other with the outer CPU interface by bus, by M bit address line and N (1≤N≤16) bit data bus and 2
M Channel data register 2 links to each other; The DLL (dynamic link library) controller receives the programming protocol signal of outer CPU, the externally effect of clock Clk down and under the control of home address controller, in proper order write 2
MThe 1st channel data register to the 2 in the channel data register 2
MChannel data register, address and 2
MThe relation of each data register in the channel data register 2 is: 0 ... 000 (M position altogether) is configuration N bit data register 6 (the 1st channel data register DR1); 0 ... 001 is configuration N bit data register 7 (the 2nd channel data register DR2); By that analogy, 1 ... 110 are configuration N bit data register 8 the (the 2nd
M-1 channel data register DR2
M-1); 1 ... 111 are configuration N bit data register 9 the (the 2nd
MChannel data register DR2
M).
2
MChannel data register 2 (see figure 2)s: by N bit data register 6 (the 1st channel data register DR1), N bit data register 7 (the 2nd channel data register DR2), N bit data register 8 the (the 2nd
M-1 channel data register DR2
M-1), the N bit data register 9 the (the 2nd
MChannel data register DR2
M) wait 2
MThe N bit data register and the M-2 of passage
MCode translator 10 is formed; 2
MThe N bit data input bus of passage links to each other with DLL (dynamic link library) controller N position output data bus; Pass through M-2
MThe decoding of the M bit address line of 10 pairs of DLL (dynamic link library) controllers of code translator is respectively charged into N bit data by user configured outer CPU programming input in N bit data register 6, N bit data register 7, N bit data register 8, N bit data register 9 etc. 2 by the DLL (dynamic link library) controller
MThe N bit data register of individual passage;
2
M-1Passage MUX 3 (see figure 3)s select n-selector 11,2N to select n-selector 12, N position latch 13, N position latch 14 etc. 2 by 2N
M-1Individual 2N selects n-selector and 2
M-1Individual N position latch is formed; According to V
COMThe saltus step of signal selects n-selector 11,2N to select n-selector 12 etc. 2 by 2N
M-1Individual 2N selects n-selector to select output N bit data register 6, N bit data register 7, N bit data register 8, N bit data register 9 etc. 2
MD1～the D2 of the N bit data register output of individual passage
MIn different 2
M-1The group data are in N position latch 13, N position latch 14 etc. 2
M-1Individual N position latch; Through N position latch 13, N position latch 14 etc. 2
M-1Data L1～L2 after the latches of individual N position
M-1Export to N figure place weighted-voltage D/A converter 15, N figure place weighted-voltage D/A converter 16 etc. 2
M-1The N figure place weighted-voltage D/A converter of individual passage; Work as V
COMSelect N bit data register 6, N bit data register 8 etc. 2 during for high level
M-1D1, the D3 of the N bit data register output of individual passage ..., D2
M-3, D2
M(being numbered odd number) 2 such as-1
M-1The group data are exported to N position latch 13, N position latch 14 etc. 2
M-1Individual N position latch; Work as V
COMSelect N bit data register 7, N bit data register 9 etc. 2 during for low level
MD2, the D4 of the N bit data register output of-1 passage ..., D2
M-2, D2
MDeng (being numbered even number) 2
M-1The group data are exported to N position latch 13, N position latch 14 etc. 2
M-1Individual N position latch;
2
M-1Port number weighted-voltage D/A converter 4 (see figure 4)s: by N figure place weighted-voltage D/A converter 15, N figure place weighted-voltage D/A converter 16 etc. 2
M-1The N figure place weighted-voltage D/A converter of passage is formed; Realization is by N position latch 13, N position latch 14 etc. 2
M-1The digital-to-analog conversion of the data of the N position latch output of passage;
2
M-1Channel buffer 5 (see figure 5)s: by rail-to-rail operational amplifier 17, rail-to-rail operational amplifier 18 etc. 2
M-1The rail-to-rail operational amplifier of passage is formed; Realization stablizes 2
M-1The voltage of port number weighted-voltage D/A converter 4 outputs, and the driving force of raising digital to analog converter.
Top technical scheme digital circuit is partly with the verilogHDL hardware description language with based on the design of the semi-custom method in elementary cell storehouse, and artificial circuit part is with the method design of full customization; The entire circuit system designs with the EDA design tool of Synopsys company and Cadence company, adopt 0.35um and following multiple layer metal CMOS integrated circuit technology condition to come the design circuit domain, finish Front-end Design and rear end emulation, submit the flow of foundries GDSII data at last to, the programmable voltage source chip of exporting with the integrated time division multiplex of the monolithic that is used for the liquid crystal display gamma correcting circuit forms this utility model product.
Embodiment 2:
The programmable voltage source of this routine time division multiplex output is got M=4, N=10.As shown in Figure 1, it comprises DLL (dynamic link library) controller 1,16 channel data register 2,8 passage MUX 3,8 port number weighted-voltage D/A converters 4,8 channel buffers 5, be characterized in that the chip layout area is little, low in energy consumption, and realize programmable voltage source output time-division multiplexing function.
DLL (dynamic link library) controller 1: DLL (dynamic link library) controller inside is made up of time schedule controller, address generator circuit; The DLL (dynamic link library) controller links to each other with the outer CPU interface by bus, links to each other with multichannel data register 2 with 10 bit data bus by 4 bit address lines; The DLL (dynamic link library) controller receives the programming protocol signal of outer CPU, externally under the effect of clock Clk and under the control of home address controller, order write the 1st channel data register to the 16 channel data register in 16 channel data register 2, the relation of each data register in address and 16 channel data register 2 is: 0000 for disposing 10 bit data register 6 (the 1st channel data register DR1); 0001 is configuration 10 bit data register 7 (the 2nd channel data register DR2); By that analogy, 1110 are configuration 10 bit data register 8 (the 15th channel data register DR15); 1111 are configuration 10 bit data register 9 (the 16th channel data register DR16).
16 channel data register, 2 (see figure 2)s: 10 bit data register and 4-16 code translator 10 by 10 bit data register 6 (the 1st channel data register DR1), 10 bit data register 7 (the 2nd channel data register DR2), 10 bit data register 8 (the 15th channel data register DR15), 10 bit data register 9 16 passages such as (the 16th channel data register DR16) are formed; 10 output data bus of 10 bit data input buss and DLL (dynamic link library) controller of 16 passages link to each other; The decoding of 4 bit address lines by 10 pairs of DLL (dynamic link library) controllers of 4-16 code translator is respectively charged into 10 bit data by user configured outer CPU programming input in 10 bit data register of 16 passages such as 10 bit data register, 6,10 bit data register, 7,10 bit data register, 8,10 bit data register 9 by the DLL (dynamic link library) controller;
8 passage MUX, 3 (see figure 3)s select 10 selector switchs 11,20 to select 8 20 of 13,10 latchs 14 of 12,10 latchs of 10 selector switchs etc. to select 10 selector switchs and 8 10 latchs to form by 20; According to V
COMThe saltus step of signal selects 10 selector switchs 11,20 to select 8 20 of 10 selector switchs 12 etc. to select 10 selector switchs to select 8 groups of different among the D1～D16 of 10 bit data register output of 16 passages such as output 10 bit data register 6,10 bit data register 7,10 bit data register 8,10 bit data register 9 data in 13,10 8 10 latchs such as latch 14 of 10 latchs by 20; Data L1～L8 after 8 10 latches such as 13,10 latchs 14 of 10 latchs exports to 10 figure place weighted-voltage D/A converters of 8 passages such as 10 figure place weighted-voltage D/A converters, 15,10 figure place weighted-voltage D/A converters 16; Work as V
COMSelect during for high level the 10 bit data register output of 8 passages such as 10 bit data register, 6,10 bit data register 8 D1, D3 ..., 8 groups of data of D13, D15 etc. (being numbered odd number) export to 13,10 8 10 latchs such as latch 14 of 10 latchs; Work as V
COMSelect during for low level the 10 bit data register output of 8 passages such as 10 bit data register, 7,10 bit data register 9 D2, D4 ..., 8 groups of data of D14, D16 etc. (being numbered even number) export to 13,10 8 10 latchs such as latch 14 of 10 latchs;
8 port number weighted-voltage D/A converters, 4 (see figure 4)s: 10 figure place weighted-voltage D/A converters by 8 passages such as 10 figure place weighted-voltage D/A converters, 15,10 figure place weighted-voltage D/A converters 16 are formed; Its input end links to each other with 10 latch output terminals of 13,10 8 passages such as latch 14 of 10 latchs respectively, and realization is by the digital-to-analog conversion of the data L1～L8 of 10 latchs outputs of 13,10 8 passages such as latch 14 of 10 latchs;
8 channel buffers, 5 (see figure 5)s: the rail-to-rail operational amplifier by 8 passages such as rail-to-rail operational amplifier 17, rail-to-rail operational amplifiers 18 is formed; Its input end links to each other with the output terminal of 10 figure place weighted-voltage D/A converters of 8 passages such as 10 figure place weighted-voltage D/A converters, 15,10 figure place weighted-voltage D/A converters 16, output DA1～the DA8 of 10 figure place weighted-voltage D/A converters of 8 passages such as 10 figure place weighted-voltage D/A converters, 15,10 figure place weighted-voltage D/A converters 16 is stablized in realization, and improves the driving force of digital to analog converter
Top technical scheme digital circuit is partly with the verilogHDL hardware description language with based on the design of the semi-custom method in elementary cell storehouse, and artificial circuit part is with the method design of full customization; The entire circuit system designs with the EDA design tool of Synopsys company and Cadence company, adopt 0.35um and following multiple layer metal CMOS integrated circuit technology condition to come the design circuit domain, finish Front-end Design and rear end emulation, submit the flow of foundries GDSII data at last to, form this invention product with the monolithic integrated programmable voltage source chip that is used for the liquid crystal display gamma correcting circuit.
Embodiment 3:
This example is got M=3, N=8.As shown in Figure 1, the programmable voltage source of this time division multiplex output, it comprises DLL (dynamic link library) controller 1,8 channel data register 2,4 passage MUX 3,4 port number weighted-voltage D/A converters 4,4 channel buffers 5, be characterized in that the chip layout area is little, low in energy consumption, and realize programmable voltage source output time-division multiplexing function.In the DLL (dynamic link library) controller 1, the relation of each data register in address and 8 channel data register 2 is: 000 is configuration 8 bit data register 6 (the 1st channel data register DR1); 001 is configuration 8 bit data register 7 (the 2nd channel data register DR2); By that analogy, 110 are configuration 8 bit data register 8 (the 7th channel data register DR7); 111 are configuration 8 bit data register 9 (the 8th channel data register DR8).
All the other concrete structures, annexation and principle of work are omitted with example 1 herein.
When M (1≤M≤16) and N (1≤N≤16) got interval other value, its principle of work and implementation method were basic identical, and reference example 1 can be expanded according to above-mentioned described thinking.
Claims (6)
1, a kind of programmable voltage source of time division multiplex output is characterized in that this voltage source comprises:
DLL (dynamic link library) controller: link to each other with the outer CPU interface by bus, by M bit address line and N bit data bus and 2
MChannel data register links to each other, wherein, and 1≤M≤6,1≤N≤16; Be used to receive the programming protocol signal of outer CPU, the externally effect of clock Clk down and under the control of home address controller, order will be user configured write 2 by the outer CPU data of importing of programming
MEach data register in the channel data register;
2
MChannel data register: link to each other with the DLL (dynamic link library) controller with the N bit data bus by M bit address line; Be used to deposit by the DLL (dynamic link library) controller and write 2 respectively
MData in each data register in the channel data register by user configured outer CPU programming input;
2
M-1The passage MUX: the MUX of each passage links to each other with the output of the data register of two different passages by the 2N position datawire, by 2
M-1The selection control end SEL of passage MUX connects the V of outside input
COMSignal is according to V
COMOutput 2 is selected in the saltus step of signal
MChannel data register DR1～DR2
MIn different 2
M-1Data in the individual passage;
2
M-1The port number weighted-voltage D/A converter: the digital to analog converter of each passage links to each other with the output of a MUX of respective channel by the N position datawire, realizes by 2
M-1The digital-to-analog conversion of the data of passage MUX output;
2
M-1Channel buffer: the input end of each channel buffer links to each other with the output of the digital to analog converter of respective channel, is used to stablize 2
M-1The output of port number weighted-voltage D/A converter, the driving force of raising digital to analog converter.
2, the programmable voltage source of time division multiplex according to claim 1 output is characterized in that described DLL (dynamic link library) controller inside is made up of time schedule controller, address generator circuit.
3, the programmable voltage source of time division multiplex output according to claim 1 is characterized in that described 2
MChannel data register is 2
MThe N bit data register of passage is respectively the 1st channel data register to the 2
MChannel data register; M bit address and 2
MThe relation of each data register in the channel data register is: 0 ... 000 is configuration the 1st channel data register DR1,0 ... 001 is configuration the 2nd channel data register DR2, by that analogy, and 1 ... 110 are configuration the 2nd
M-1 channel data register DR2
M-1,1 ... 111 are configuration the 2nd
MChannel data register DR2
M
4, the programmable voltage source of time division multiplex output according to claim 1 is characterized in that described 2
M-1The passage MUX is by 2
M-1Individual 2N selects n-selector and 2
M-1Individual N position latch is formed; According to V
COMThe saltus step of signal is by 2
M-1The passage MUX is selected output 2
MChannel data register DR1～DR2
MIn 2
M-1Data in the individual channel data register, and latch in 2
M-1In the N position latch of passage.
5, the programmable voltage source of time division multiplex output according to claim 1 is characterized in that described 2
M-1The port number weighted-voltage D/A converter is by 2
M-1The N figure place weighted-voltage D/A converter of passage is formed; Be used to realize 2
M-1The digital-to-analog conversion of the N position latch output data of passage.
6, the programmable voltage source of time division multiplex output according to claim 1 is characterized in that described 2
M-1Channel buffer is by 2
M-1The rail-to-rail operational amplifier of passage is formed; Be used to stablize 2
M-1The output of port number weighted-voltage D/A converter, the driving force of raising digital to analog converter.
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| CNU2009200958316U CN201364724Y (en) | 2009-03-11 | 2009-03-11 | Programmable voltage source of time division multiplex output |
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| CNU2009200958316U CN201364724Y (en) | 2009-03-11 | 2009-03-11 | Programmable voltage source of time division multiplex output |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510407B (en) * | 2009-03-11 | 2011-04-20 | 南开大学 | Programmable voltage source with TDM output and implementing method |
-
2009
- 2009-03-11 CN CNU2009200958316U patent/CN201364724Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510407B (en) * | 2009-03-11 | 2011-04-20 | 南开大学 | Programmable voltage source with TDM output and implementing method |
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Granted publication date: 20091216 Effective date of abandoning: 20090311 |