CN201196910Y - Packaging body used for sheet-type multilayer ceramic capacitor and sheet-type multi-layer piezoresistor - Google Patents
Packaging body used for sheet-type multilayer ceramic capacitor and sheet-type multi-layer piezoresistor Download PDFInfo
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- CN201196910Y CN201196910Y CNU2008200635688U CN200820063568U CN201196910Y CN 201196910 Y CN201196910 Y CN 201196910Y CN U2008200635688 U CNU2008200635688 U CN U2008200635688U CN 200820063568 U CN200820063568 U CN 200820063568U CN 201196910 Y CN201196910 Y CN 201196910Y
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- ceramic capacitor
- chip multilayer
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- encapsulated
- multilayer ceramic
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Abstract
The utility model discloses an encapsulating body for a plate type multi-layer ceramic capacitor and a plate type multi-layer pressure sensitive resistor. In the encapsulating body, other outer surfaces except for two termination electrodes in the plate type multi-layer ceramic capacitor or the plate type multi-layer pressure sensitive resistor are tightly encapsulated with an encapsulated layer which prefers a glass glaze integrated encapsulated layer. Due to adoption of the structure of the high-temperature sintered glass glaze encapsulated layer, the humidity resistance and the insulating property of the plate type multi-layer ceramic capacitor or the plate type multi-layer pressure sensitive resistor are obviously strengthened, so that the operation of products is more stable and more reliable.
Description
Technical field
The utility model relates to a kind of encapsulating structure that is suitable for surface-pasted electronic devices and components, relates in particular to a kind of encapsulated member that is used for chip multilayer ceramic capacitor and chip multilayer varistor, belongs to the field of sealing of chip multilayer electronic devices and components.
Background technology
Chip multilayer varistor (be called for short VSR) is mainly used in IC chip overvoltage protection, ESD electrostatic defending, and chip multilayer ceramic capacitor (being called for short MLCC) is widely used in that stopping direct current, coupling, bypass, filtering, resonant tank are tuning, the time constant in the power conversion, control circuit etc.The chip multilayer ceramic capacitor of extensive use at present and the outer surface of chip multilayer varistor have only bluff piece, all there is not outer encapsulated layer, have following problem: (1) is not owing to there is the external packets seal, moisture is easily invaded, and 1100 ℃～1200 ℃ intermediate sintering temperatures and to be lower than in the electrode of 1100 ℃ of low-temperature sintering chip multilayer ceramic capacitors (MLCC) and chip multilayer varistor (VSR) silver content higher, the back silver ion migration of making moist is strengthened, cause the decreasing insulating of product serious, cause reliability of products relatively poor.(2) three layers of plating are substrate with silver, the back silver ion migration of making moist, and it is more serious to cause insulation resistance to descend, and low-temperature sintering chip multilayer ceramic capacitor (MLCC) so its humidity resistance is poor, generally can not be applicable to three layers of plating because of there not being encapsulated layer; Especially for chip multilayer varistor (VSR),, be not suitable for three layers of plating because its surface conductance is electroplated easily short circuit of back yet; (3) owing to there is not outer encapsulated layer,, produced additional capacitor owing to plate the end bound edge, so influenced the capacity precision of electric capacity for chip multilayer ceramic capacitor (MLCC); For chip multilayer varistor (VSR), because plating end bound edge, make resistive short, so influenced the resistance accuracy of resistance.
Summary of the invention
The purpose of this utility model is to provide a kind of encapsulated member that is used for chip multilayer ceramic capacitor and chip multilayer varistor in order to address the above problem, and this structure can make the humidity resistance and the insulation property of chip multilayer ceramic capacitor or chip multilayer varistor obviously strengthen.
In order to achieve the above object, the utility model is by the following technical solutions:
Other outer surface in chip multilayer ceramic capacitor or chip multilayer varistor except that two termination electrodes is close to and is encapsulated with one deck encapsulated layer.Encapsulated layer mainly contains strengthens humidity resistance and insulation property effect, can effectively improve reliability of products and capacitance and resistance accuracy.
As best-of-breed technology scheme of the present utility model, described encapsulated layer is continuous integrated glass glaze encapsulated layer; Its thickness is the 5--100 micron.The glass glaze encapsulated layer is general to adopt the mode of 960 ℃～1100 ℃ high temperature sinterings (also can increase in 400 ℃～960 ℃, low-temperature sintering), and its humidity resistance and insulation property are very high, can reach best insulation effect.
The beneficial effects of the utility model are:
(1) owing to after having sealed glass glaze, improved the humidity resistance of product, reduced the silver ion migration,, thereby the reliability of chip multilayer ceramic capacitor or the work of chip multilayer varistor has obviously been improved so the insulation property of product have obtained guarantee; (2) be largely increased owing to insulation property, so be applicable to three layers of plating; (3), reduced the additional capacitor that plating end bound edge produces, thereby improved the capacity precision because glass glaze has been sealed on the surface, and for chip multilayer ceramic capacitor (MLCC), glass-glazed dielectric constant is low; And for chip multilayer varistor (VSR), seal glass glaze after, surface insulation has reduced because the short-circuit resistance that plating end bound edge effectiveness reduces, thereby has improved resistance accuracy.
Description of drawings
Fig. 1 is the main TV structure schematic diagram that the utility model is used in general termination electrode product;
Fig. 2 is the A-A cutaway view among Fig. 1;
Fig. 3 is that the utility model is electroplated the main TV structure schematic diagram of using in the termination electrode product at three layers;
Fig. 4 is the B-B cutaway view among Fig. 3;
Fig. 5 is that the utility model is electroplated the plan structure schematic diagram of using in the termination electrode product at three layers;
Fig. 6 is the C-C cutaway view among Fig. 5.
Embodiment
Below in conjunction with accompanying drawing the utility model is further described in detail:
The application that is the utility model in general termination electrode product illustrated in figures 1 and 2, other outer surface in chip multilayer ceramic capacitor 2 (2 also can be the chip multilayer varistor) except that two termination electrodes 1 are close to and are encapsulated with one deck glass glaze encapsulated layer 3.Glass glaze encapsulated layer 3 has the effect of strengthening humidity resistance and insulation property, can effectively improve reliability of products and resistance accuracy.In Fig. 2,6 is bluff piece, and 5 is electrode in palladium-silver or the fine silver, and 8 is deielectric-coating.Particularly, if 2 be chip multilayer ceramic capacitor, then 8 is ceramic dielectric films; If 2 is the chip multilayer varistor, then 8 is metal oxide film.
Fig. 3---Figure 6 shows that the utility model three layers of application of electroplating in the termination electrode products, other outer surface in chip multilayer ceramic capacitor 13 (13 also can be the chip multilayer varistor) except that two termination electrodes 9 is close to and is encapsulated with one deck glass glaze encapsulated layer 3.Glass glaze encapsulated layer 3 has the effect of strengthening humidity resistance and insulation property, can effectively improve reliability of products and resistance accuracy.In Fig. 4 and Fig. 6,6 is bluff piece, and 5 is electrode in palladium-silver or the fine silver, and 8 is deielectric-coating.Particularly, if 2 be chip multilayer ceramic capacitor, then 8 is ceramic dielectric films; If 2 is the chip multilayer varistor, then 8 is metal oxide film.As shown in Figure 6,10---12 are respectively three layers of electrodeposited coating, and wherein, 10 is outer tin or tin lead electrode, and 11 is middle level nickel or copper electrode, and 12 is internal layer silver or palladium-silver electrode.
In Fig. 2, Fig. 4 and Fig. 6, glass glaze encapsulated layer 3 is continuous integrated encapsulated layer, and its thickness is 5---100 microns, determine according to actual needs.Adopt the mode of 960 ℃～1100 ℃ high temperature sinterings (also can increase in 400 ℃～960 ℃, low-temperature sintering) because glass glaze encapsulated layer 3 is general,, can reach best insulation effect so its humidity resistance and insulation property are very high.
Claims (5)
1. encapsulated member that is used for chip multilayer ceramic capacitor and chip multilayer varistor is characterized in that: other outer surface in chip multilayer ceramic capacitor or chip multilayer varistor except that two termination electrodes is close to and is encapsulated with one deck encapsulated layer.
2. the encapsulated member that is used for chip multilayer ceramic capacitor and chip multilayer varistor according to claim 1 is characterized in that: described encapsulated layer is continuous integrated encapsulated layer.
3. the encapsulated member that is used for chip multilayer ceramic capacitor and chip multilayer varistor according to claim 1 and 2 is characterized in that: described encapsulated layer is the glass glaze encapsulated layer.
4. the encapsulated member that is used for chip multilayer ceramic capacitor and chip multilayer varistor according to claim 3 is characterized in that: the thickness of described encapsulated layer is 5---100 microns.
5. the encapsulated member that is used for chip multilayer ceramic capacitor and chip multilayer varistor according to claim 1 and 2 is characterized in that: the thickness of described encapsulated layer is 5---100 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200635688U CN201196910Y (en) | 2008-05-29 | 2008-05-29 | Packaging body used for sheet-type multilayer ceramic capacitor and sheet-type multi-layer piezoresistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200635688U CN201196910Y (en) | 2008-05-29 | 2008-05-29 | Packaging body used for sheet-type multilayer ceramic capacitor and sheet-type multi-layer piezoresistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201196910Y true CN201196910Y (en) | 2009-02-18 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008200635688U Expired - Lifetime CN201196910Y (en) | 2008-05-29 | 2008-05-29 | Packaging body used for sheet-type multilayer ceramic capacitor and sheet-type multi-layer piezoresistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201196910Y (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679529A (en) * | 2016-01-14 | 2016-06-15 | 深圳顺络电子股份有限公司 | Magnetic device and manufacturing method thereof |
| CN108288529A (en) * | 2018-01-19 | 2018-07-17 | 安徽建筑大学 | Preparation method of negative low-aging-rate negative temperature coefficient thermistor ceramic material |
| CN108695067A (en) * | 2017-04-04 | 2018-10-23 | 三星电机株式会社 | Multi-layer capacitor and the method for manufacturing multi-layer capacitor |
| CN108695065A (en) * | 2017-03-29 | 2018-10-23 | 三星电机株式会社 | Multi-layer capacitor and its manufacturing method |
| US10770234B2 (en) | 2017-04-04 | 2020-09-08 | Samsung Electro-Mechanics Co., Ltd. | Multilayer capacitor |
| CN112216512A (en) * | 2019-07-10 | 2021-01-12 | 三星电机株式会社 | Multilayer capacitor and mounting substrate therefor |
-
2008
- 2008-05-29 CN CNU2008200635688U patent/CN201196910Y/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679529A (en) * | 2016-01-14 | 2016-06-15 | 深圳顺络电子股份有限公司 | Magnetic device and manufacturing method thereof |
| CN108695065A (en) * | 2017-03-29 | 2018-10-23 | 三星电机株式会社 | Multi-layer capacitor and its manufacturing method |
| US10726997B2 (en) | 2017-03-29 | 2020-07-28 | Samsung Electro-Mechanics Co., Ltd. | Multilayer capacitor and method for manufacturing the same |
| CN108695067A (en) * | 2017-04-04 | 2018-10-23 | 三星电机株式会社 | Multi-layer capacitor and the method for manufacturing multi-layer capacitor |
| US10770234B2 (en) | 2017-04-04 | 2020-09-08 | Samsung Electro-Mechanics Co., Ltd. | Multilayer capacitor |
| CN108695067B (en) * | 2017-04-04 | 2022-01-07 | 三星电机株式会社 | Multilayer capacitor and method for manufacturing multilayer capacitor |
| CN108288529A (en) * | 2018-01-19 | 2018-07-17 | 安徽建筑大学 | Preparation method of negative low-aging-rate negative temperature coefficient thermistor ceramic material |
| CN108288529B (en) * | 2018-01-19 | 2019-07-26 | 安徽建筑大学 | Preparation method of negative low-aging-rate negative temperature coefficient thermistor ceramic material |
| CN112216512A (en) * | 2019-07-10 | 2021-01-12 | 三星电机株式会社 | Multilayer capacitor and mounting substrate therefor |
| CN112216512B (en) * | 2019-07-10 | 2022-06-07 | 三星电机株式会社 | Multilayer capacitor and mounting substrate therefor |
| US12014880B2 (en) | 2019-07-10 | 2024-06-18 | Samsung Electro-Mechanics Co., Ltd. | Multilayered capacitor and board having the same mounted thereon |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090218 |
|
| CX01 | Expiry of patent term | ||
| DD01 | Delivery of document by public notice |
Addressee: Hongming Electronic Co., Ltd, Chengdu Document name: Notification of Expiration of Patent Right Duration |
|
| DD01 | Delivery of document by public notice |