CN201146493Y - High speed output circuit with improved impedance matching performance - Google Patents
High speed output circuit with improved impedance matching performance Download PDFInfo
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- CN201146493Y CN201146493Y CNU200720071317XU CN200720071317U CN201146493Y CN 201146493 Y CN201146493 Y CN 201146493Y CN U200720071317X U CNU200720071317X U CN U200720071317XU CN 200720071317 U CN200720071317 U CN 200720071317U CN 201146493 Y CN201146493 Y CN 201146493Y
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- resistor
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- impedance
- drain electrode
- source electrode
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Abstract
The utility model discloses a high-speed output circuit which improves the impedance matching performance and consists of a first field-effect triode, a second field-effect triode, a first resistor and a second resistor. A third resistor is added between a cathode of an output node and a drain of the first field-effect triode; a fourth resistor is added between an anode of the output node and a drain of the second field-effect triode, thus equivalently respectively dividing the two resistors in the prior art into a first resistor and a third resistor, a second resistor and a fourth resistor. Sum of the impedance of the first resistor and the third resistor and sum of the impedance of the second resistor and the fourth resistor equal to the impedance of one resistor in the prior art. In high-speed application, the impedance matching of a signal output end is not basically affected by a parasitic resistor. According to the application requirements of the circuit, the impedance distribution of the first resistor and the third resistor and the impedance distribution of the second resistor and the fourth resistor can be chosen to satisfy the need of impedance matching of high-speed output.
Description
Technical field:
The utility model relates to electricity field, relates in particular to the high speed current mode logic circuits, particularly a kind of high speed output circuit that improves the impedance matching performance.
Background technology:
The output circuit of communication chip needs the output matched impedance of 50ohm.The impedance of the resistor that output impedance is connected in parallel by two 50ohm, two fet drain electrodes realizes.Two fets all are connected with capacitor parasitics.The impedance of the drain electrode of two fets is by the internal output impedance decision of two fets.Whole output impedance value is by the impedance generation in parallel with the 50ohm resistor of fet drain electrode.In the analogue circuit applications of low speed, internal output impedance is far longer than 50ohm, so whole output impedance approximates the impedance of a 50ohm resistor greatly.But in application very at a high speed, especially in deep submicron process, because capacitor parasitics, the resistance value of the drain electrode of two fets no longer is far longer than 50ohm.Therefore, the output impedance coupling of realization 50ohm is very difficult.
Summary of the invention:
The purpose of this utility model provides a kind of high speed output circuit that improves the impedance matching performance, and the high speed output circuit of described this improvement impedance matching performance will solve the unfavorable technical problem of output impedance matching technique that is used for the high speed communication chip in the prior art.
The high speed output circuit of this improvement impedance matching performance of the present utility model is by one first fet, second fet, one first resistor and one second resistor are formed, the source electrode of described first fet is connected with the source electrode of second fet, be connected with the drain electrode of one the 3rd fet between the source electrode of the source electrode of first fet and second fet, the source electrode of described the 3rd fet is connected with a power supply, described first resistor and second resistor in series are connected between the drain electrode and the drain electrode of second fet of first fet, be connected with described power supply between first resistor and second resistor, be connected with the negative pole of an output node between first resistor and first fet, be connected with the positive pole of described output node between second resistor and second fet, the grid of first fet is connected with the positive pole of an input node, the grid of second fet is connected with the negative pole of described input node, between the source electrode and grid of first fet, between grid and the drain electrode, be connected with capacitor parasitics separately between drain electrode and the source electrode, between the source electrode and grid of second fet, between grid and the drain electrode, be connected with capacitor parasitics separately between drain electrode and the source electrode, wherein, be connected with one the 3rd resistor between the drain electrode of the negative pole of described output node and first fet, be connected with one the 4th resistor between the drain electrode of the positive pole of output node and second fet.
Operation principle of the present utility model is: the utility model increases by one the 3rd resistor between the drain electrode of the negative pole of output node and first fet, between the drain electrode of the positive pole of output node and second fet, increase by one the 4th resistor, be equivalent to two resistors of the prior art are divided into first resistor and the 3rd resistor respectively, second resistor and the 4th resistor, the impedance sum of first resistor and the 3rd resistor, the impedance sum of second resistor and the 4th resistor is equivalent to the impedance of a resistor of the prior art, and the impedance matching of signal output part is not subjected to the influence of capacitor parasitics substantially in application very at a high speed.Can select the impedance of impedance distribution, second resistor and the 4th resistor of first resistor and the 3rd resistor to distribute, to satisfy the needs of output at a high speed according to the application requirements of circuit.
The utility model and prior art contrast, and its effect is actively with tangible.The utility model increases a resistor between the drain electrode of the negative pole of output node and first fet, between the drain electrode of the positive pole of output node and second fet, increase a resistor, can be according to the application requirements of circuit, select the impedance allocative decision between newly-increased resistor and the primary circuit intrinsic resistance device, signal output part can not be subjected to the influence of capacitor parasitics, to satisfy the needs of high speed output impedance coupling.
Description of drawings:
Fig. 1 is the structural representation of the high speed output circuit of improvement impedance matching performance of the present utility model.
Embodiment:
As shown in Figure 1, the high speed output circuit of improvement impedance matching performance of the present utility model is by one first fet, second fet, one first resistor R 1 and one second resistor R 2 are formed, the source electrode MINN of described first fet is connected with the source electrode MINP of second fet, be connected with the drain electrode of one the 3rd fet between the source electrode MINN of first fet and the source electrode MINP of second fet, the source electrode MB of described the 3rd fet is connected with the Vss of power supply end, the grid of the 3rd fet is connected with the Vbias of circuit end, described first resistor R 1 and second resistor R 2 are connected in series between the drain electrode and second fet of first fet, be connected with the Vdd end of described power supply between first resistor R 1 and second resistor R 2, be connected with the negative pole OUT-of an output node between first resistor R 1 and first fet, be connected with the anodal OUT+ of described output node between second resistor R 2 and second fet, the grid of first fet is connected with the anodal Vin+ of an input node, the grid of second fet is connected with the negative pole Vin-of described input node, between the source electrode and grid of first fet, between grid and the drain electrode, be connected with capacitor parasitics separately between drain electrode and the source electrode, between the source electrode and grid of second fet, between grid and the drain electrode, be connected with capacitor parasitics separately between drain electrode and the source electrode, wherein, be connected with one the 3rd resistor R 3 between the drain electrode of the negative pole of described output node and first fet, be connected with one the 4th resistor R 4 between the drain electrode of the positive pole of output node and second fet.
Operation principle of the present utility model is: the utility model increases by one the 3rd resistor R 3 between the drain electrode of the negative pole of output node and first fet, between the drain electrode of the positive pole of output node and second fet, increase by one the 4th resistor R 4, be equivalent to two resistors of the prior art are divided into first resistor R 1 and the 3rd resistor R 3 respectively, second resistor R 2 and the 4th resistor R 4, the impedance sum of first resistor R 1 and the 3rd resistor R 3, the impedance sum of second resistor R 2 and the 4th resistor R 4 is equivalent to the impedance of a resistor of the prior art, and the impedance matching of signal output part is not subjected to the influence of capacitor parasitics substantially in application very at a high speed.Can select the impedance allocative decision of impedance allocative decision, second resistor R 2 and the 4th resistor R 4 of first resistor R 1 and the 3rd resistor R 3 according to the application requirements of circuit, to satisfy the needs of high speed output impedance coupling.
Claims (1)
1. high speed output circuit that improves the impedance matching performance, by one first fet, second fet, one first resistor and one second resistor are formed, the source electrode of described first fet is connected with the source electrode of second fet, be connected with the drain electrode of one the 3rd fet between the source electrode of the source electrode of first fet and second fet, the source electrode of described the 3rd fet is connected with a power supply, described first resistor and second resistor are connected between the drain electrode and the drain electrode of second fet of first fet, be connected with described power supply between first resistor and second resistor, be connected with the negative pole of an output node between first resistor and first fet, be connected with the positive pole of described output node between second resistor and second fet, the grid of first fet is connected with the positive pole of an input node, the grid of second fet is connected with the negative pole of described input node, between the source electrode and grid of first fet, between grid and the drain electrode, be connected with capacitor parasitics separately between drain electrode and the source electrode, between the source electrode and grid of second fet, between grid and the drain electrode, be connected with capacitor parasitics separately between drain electrode and the source electrode, it is characterized in that: be connected with one the 3rd resistor between the drain electrode of the negative pole of described output node and first fet, be connected with one the 4th resistor between the drain electrode of the positive pole of output node and second fet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200720071317XU CN201146493Y (en) | 2007-06-20 | 2007-06-20 | High speed output circuit with improved impedance matching performance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200720071317XU CN201146493Y (en) | 2007-06-20 | 2007-06-20 | High speed output circuit with improved impedance matching performance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201146493Y true CN201146493Y (en) | 2008-11-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU200720071317XU Expired - Fee Related CN201146493Y (en) | 2007-06-20 | 2007-06-20 | High speed output circuit with improved impedance matching performance |
Country Status (1)
| Country | Link |
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| CN (1) | CN201146493Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106877936A (en) * | 2017-04-17 | 2017-06-20 | 武汉飞鹏光科技有限公司 | A kind of SFP28 optical modules |
-
2007
- 2007-06-20 CN CNU200720071317XU patent/CN201146493Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106877936A (en) * | 2017-04-17 | 2017-06-20 | 武汉飞鹏光科技有限公司 | A kind of SFP28 optical modules |
| CN106877936B (en) * | 2017-04-17 | 2024-02-23 | 武汉飞鹏光科技有限公司 | SFP28 optical module |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| C53 | Correction of patent for invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Sun Runhua Inventor before: Sun Runhua Inventor before: Peng Lihua Inventor before: Kong Weixin |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20090213 Address after: Room 1001, room 765, South Tibet Road, Shanghai, 200011 Patentee after: Sun Runhua Address before: Room 1001, room 765, South Tibet Road, Shanghai, 200011 Co-patentee before: Sun Runhua Patentee before: Qi Ling microelectronics technology (Shanghai) Co., Ltd. Co-patentee before: Peng Lihua Co-patentee before: Kong Weixin |
|
| ASS | Succession or assignment of patent right |
Owner name: SUN RUNHUA Free format text: FORMER OWNER: QILING MICRO-ELECTRON SCIENCE ( SHANGHAI ) CO., LTD. Effective date: 20090213 |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: SUN RUNHUA; PENG LIHUA; KONG WEIXIN TO: SUN RUNHUA |
|
| ASS | Succession or assignment of patent right |
Owner name: QILING MICROELECTRONICS TECHNOLOGY (SHANGHAI) CO., Free format text: FORMER OWNER: SUN RUNHUA Effective date: 20100416 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20100416 Address after: 200011 room 765, South Tibet Road, Shanghai, 1001 Patentee after: Visem Microelectronics Inc. Address before: 200011 room 765, South Tibet Road, Shanghai, 1001 Patentee before: Sun Runhua |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081105 Termination date: 20100620 |