CN201116928Y - Simple digital circuit logic analyzer - Google Patents
Simple digital circuit logic analyzer Download PDFInfo
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- CN201116928Y CN201116928Y CNU2007200430005U CN200720043000U CN201116928Y CN 201116928 Y CN201116928 Y CN 201116928Y CN U2007200430005 U CNU2007200430005 U CN U2007200430005U CN 200720043000 U CN200720043000 U CN 200720043000U CN 201116928 Y CN201116928 Y CN 201116928Y
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Abstract
The utility model relates to a simple digital circuit logic analyzer, which is characterized in that the simple digital circuit logic analyzer adopts a general purpose ondoscope, and is provided with a signal collecting processing circuit which utilizes a singlechip to be a central processing unit, wherein the signal collecting processing circuit comprises 8 or 16 channels multipath data collecting circuit, a level shifter transfer circuit in which digital collecting signals do multistage level shifter transformation of digital signals, multipath signals which are transferred through the level shifter are displayed on the ondoscope through an input end of the ondoscope in different zero coordinates, an output circuit which utilizes a general purpose ondoscope to be the display terminal, which outputs logical shift level signals in synchronous cycle in recirculation in time division. The structure of the simple digital circuit logic analyzer has simple structure and low production cost, which is suitable for normally allocating in the teaching of colleges and universities to improve teaching experiment quality.
Description
Technical field:
The utility model relates to the analytical instrument that is applied to digital circuit, more particularly especially a kind ofly is suitable for the simple type digital circuit logic analyser that education experiment is used.
Background technology:
The special logic analyser is the advanced analysis instrument of digital circuit, and its sample frequency height, capacity is big, passage is many, analytic function is strong, is the strong instrument of analyzing with design complex digital system.
In the Fundamental Digital Circuit education experiment of institution of higher learning, usually relate to design, experiment and the analysis of DLC (digital logic circuit).Yet above-mentioned existing logic analyser costs an arm and a leg, and being difficult in experiment has influenced teaching efficiency to a certain extent for each student is equipped with.
At present, in the education experiment of digital circuit, the common surveying instrument that disposes only is single channel or binary channels ordinary oscilloscope.But, when adopting oscilloscope measurement circuit signal sequential, can only measure and demonstrate constant single channel of cycle stability or two-way output waveform, then can't measure demonstration for transient state and multiple signals.
The utility model content:
The utility model is for avoiding above-mentioned existing in prior technology weak point, provide a kind of simple in structure, cost is low, be suitable for carrying out the simple type digital circuit logic analyser of common configuration in institution of higher learning's teaching, to improve the education experiment quality.
The technical scheme that the utility model technical solution problem is adopted is:
The utility model simple type digital circuit logic analyser is characterized in adopting general purpose oscialloscope, and to be provided with the single-chip microcomputer be the signal acquisition processing circuit of central processing unit, and described signal acquisition processing circuit comprises:
8 or 16 passage multichannel data sample circuits, the multichannel data sampled signal is imported single-chip microcomputer P1 mouth through buffer interface, and is stored among the outer extension memory RAM;
The level shift change-over circuit, the multichannel data sampled signal that is stored in outer extension memory RAM is removed, the single-chip microcomputer expansion I/O interface is delivered in timesharing, the digital sampled signal of timesharing output is carried out the multilevel electrical level displacement conversion of digital signal in the level shift change-over circuit, the multiple signals of changing through level shift show with different zero coordinates on oscillograph by an oscillographic input channel;
Output circuit is a display terminal with described general purpose oscialloscope, and the outer synchronous triggering signal input port EXT and the Y-axis input port of its output interface and display terminal link, the timesharing output logic shift levels that circulates synchronizing cycle signal.
Design feature of the present utility model also is:
Sample circuit is provided with many grades of sample frequency.
The level shift change-over circuit adopts a slice multi-path digital switch U6 and a slice multiway analog switch U5, the diode D1 that series connection is provided with, D2, D3, D4, D5, D6, D7 and D8 constitute bleeder circuit, between described bleeder circuit and earth terminal GND, series connection is provided with two diode D9 by switching tube Q1 control, D10, the base stage of switching tube Q1 connects multi-path digital switch U6's/the Z end, different voltage division signal inserts the signal input part at multiway analog switch U5 respectively, the eight tunnel level signal d0s corresponding with input logic signal, d1, d2, d3, d4, d5, d6 and d7 insert multi-path digital switch U6, control signal A from eight kinds of different states of characterized 0-7 of single-chip microcomputer, B, C inserts the control end of multi-path digital switch U6 and multiway analog switch U5 respectively, with the input port of the OUT termination general purpose oscialloscope of multiway analog switch U5.
Compared with the prior art, the utility model beneficial effect is embodied in:
The utility model is by the sampling storage to multiple signals, utilize the level shift change-over circuit timesharing output logic shift levels signal that circulates synchronizing cycle, finally be to be display terminal with the oscillograph, utilize people's retentivity time of eye characteristics, on oscillograph, demonstrate 8 one 16 road stable logical sequence figures.Compare with simple use oscillograph, the utlity model has the logic analysis function of multiple signals, realize showing for the measurement of transient state and multiple signals.Compare with existing special logic analyser, its price reduces greatly, is suitable for common configuration in education experiment, helps improving the quality of teaching.
Description of drawings:
Fig. 1 is the utility model system chart.
Fig. 2 is the utility model level shift change-over circuit schematic diagram.
Fig. 3 is 8 tunnel logic analysis signals that the utility model shows on oscillograph simultaneously.
Fig. 4 for the utility model through the 8 tunnel level signal oscillograms corresponding behind the level shift with input logic signal.
Fig. 5 is the utility model and d0, d1, d2, d3, d4, d5, d6, triggering synchronous signal waveforms that d78 road signal is corresponding.
Below, in conjunction with the accompanying drawings the utility model is further described by embodiment:
Embodiment:
Referring to Fig. 1, present embodiment adopts general purpose oscialloscope, and to be provided with the single-chip microcomputer be the signal acquisition processing circuit of central processing unit, and signal acquisition processing circuit comprises:
The multichannel data sample circuit of 8 or 16 passages, the multichannel data sampled signal is imported single-chip microcomputer P1 mouth through buffer interface, and is stored among the outer extension memory RAM;
The level shift change-over circuit, the multichannel data sampled signal that is stored in outer extension memory RAM is removed, the single-chip microcomputer expansion I/O interface is delivered in timesharing, the digital sampled signal of timesharing output is carried out the multilevel electrical level displacement conversion of digital signal by the level shift conversion interface circuit in the level shift change-over circuit, the multiple signals of changing through level shift show with different zero coordinates on oscillograph by an oscillographic input channel;
Output circuit is a display terminal with the general purpose oscialloscope, and the outer synchronous triggering signal input port EXT and the Y-axis input port of output interface and display terminal link, the timesharing output logic shift levels that circulates synchronizing cycle signal.
In concrete the enforcement, the corresponding structure setting also comprises:
Sample circuit is provided with many grades of sample frequency, to analyze the logical sequence of different frequency bands.
Multiple triggering mode is provided, comprises manual triggers and triggering automatically.Wherein manual triggers is divided into the rising edge triggering again, negative edge triggers dual mode, can catch random signal.
Waveform displacement button is provided, comprises two keys that move to left and move to right, can translation logical sequence waveform, with the live forever different waveforms constantly of storage of convenient observation.
The built-in switch power supply provides the multiple voltage power supply.
Outside eight road logical signals are delivered to single-chip microcomputer through buffer interface 74LS245, single-chip microcomputer is kept at the data-signal that collects and extends out among the RAM 62256 (32K), after sampling finishes, single-chip microcomputer takes out data from extending out RAM, and expansion I/O interface 8255A is delivered in timesharing, behind the level conversion shift circuit, the 8 circuit-switched data timesharing that collect are outputed to oscillograph show.Show though this eight road signal is the mode by timesharing and level shift,, show simultaneously thereby the observer feels eight road signals because processing speed is fast and people's persistence of vision.
The signal procedure for displaying comprises data acquisition, output waveform displacement and output three phases.
Data acquisition:
Outside eight road logical signals are delivered to the P1 mouth of single-chip microcomputer through buffer interface 74LS245, and single-chip microcomputer is kept at the data that collect and extends out among the RAM 62256 (32K), up to and adopt full 32K.The sampling before sample frequency can be set as requested, maximum sample frequency can reach 333K, all the other also have 100K, 200K etc. totally seven grades adjustable.And can select manual triggers or triggering automatically, and for manual triggers, after pressing start button, begin sampling immediately, for automatic triggering, system triggers sampling automatically according to selected rising edge or negative edge.
The output waveform displacement is a level conversion:
The effect of level conversion is that eight road input logic signals are carried out suitable level translation, and it is shown with different zero coordinates on oscillograph by an oscillographic input channel.This part is realized that by hardware its circuit structure as shown in Figure 2.
Referring to Fig. 2, adopting a slice multi-path digital switch 74LS151 is that chip U6, a slice multiway analog switch CD4051 are chip U5, eight general-purpose diode D1, D2, D3, D4, D5, D6, D7 and D8, and diode D9 and D10, ceramic disc capacitor C17, C18 and the C19 of a transistor Q1, three different appearance values, and the resistance R 10 of three different resistances, R11 and R12 form.Wherein, the positive pole of a termination 9V direct supply of resistance R 12, the anode of another terminating diode D1; Diode D1, D1, D2, D3, D4, D5, D6, D7, D8, D9 and D10, polyphone joins, that is, the negative electrode of D1 connects the anode of D2, and the negative electrode of D2 connects the anode of D3 ... by that analogy, connect the anode of D10 until the negative electrode of D9, diode D1 simultaneously, the anode of D1, D2, D3, D4, D5, D6, D7 respectively with the input of multiway analog switch U5 delivery outlet IO0, IO1, IO2, IO3, IO4, IO5, IO6, IO7 link to each other; The pin 9,10,11 of U5 is that the pin 9,10,11 of U6 meets external control signal C, B, A after corresponding linking to each other with multi-path digital switch 74LS1512 respectively; 6,7,8 pin of U5 and connect the back link to each other with ground, be connected to the end of C17 simultaneously, the positive pole of another termination 9V direct supply of C17 and 12 pin of U5; The OUT pin of U5 connects oscillographic input port; The anode of diode D9 links to each other with the collector of the negative electrode of D8 and transistor Q1; The plus earth of diode D10; Resistance R 10 and capacitor C 18 pin/Z of termination 74LS151 afterwards in parallel, the other end links to each other with the base stage of resistance R 11 and transistor Q1, the other end ground connection of R11; 7,8 pin of U6 also connect the back and link to each other with an end of ground and capacitor C 19, another termination VCC pin of C19, and outside digital signal d0, d1, d2, d3, d4, d5, d6 and the d7 that samples connects 10,11,12,13,14,15,16,17 pin of U6.
Among Fig. 2, d0, d1, d2, d3, d4, d5, d6, d7 are eight tunnel level signals of input logic signal correspondence, and A, B, C are " 0 ", " 1 " control signal that Single Chip Microcomputer (SCM) program is sent, and the various combination of A, B, C obtains eight kinds of different states of 0-7 altogether.
Circuit characteristic according to chip self, chip U5 is according to the combination difference of control signal A, B, C, on OUT end pin, obtain 4,2,5,1,12,15,14 and 13 varying level, control signal A, B, C also are used for the output of control chip U6 simultaneously, chip U6 exports d0, d1, d2, d3, d4, d5, d6 and d7 according to the combination of control signal A, B, C respectively on its pin 6.When d0, d1, d2, d3, d4, d5, d6 and d7 are high level, transistor Q1 conducting, two schottky diodes are by short circuit, and the level that obtains at the 4th, 2,5,1,12,15,14 and 13 each pin of chip U5 is respectively 0.7V, 1.4V, 2.1V, 2.8V, 3.5V, 4.2V, 4.9V, 5.6V; When d0, d1, d2, d3, d4, d5, d6 and d7 are low level, transistor Q1 ends, the level that obtains on the 4th, 2,5,1,12,15,14 and the 13rd each pin of chip U5 is respectively: 1V, 1.7V, 2.4V, 3.2V, 3.8V, 4.5V, 5.2V, 5.9V, various combination according to d0, d1, d2, d3, d4, d5, d6 and d7 digital signal obtains 16 kinds of level on the OUT of chip U5 pin, thereby has also just realized the displacement conversion of level.
The output video data:
Figure 3 shows that structure setting by present embodiment, on an oscillographic passage, demonstrate eight road signals simultaneously, wherein, " triggering " port is oscillographic external sync trigger pip port, link to each other with the Single-chip Controlling port, " input " port is an oscillograph Y-axis signal input part, links to each other with the output port of level shift change-over circuit.
Single-chip microcomputer will collect and be stored in and extend out data taking-up among the RAM, by expansion I/O interface 8255A, behind the level conversion shift circuit, send data oscillograph to show.The OUT pin directly connects the oscillographic input terminal of simulation among Fig. 2, simultaneously, synchronous scanning output signal Tr connects oscillograph external trigger end through buffer circuit, and synchronous scanning output signal Tr0, Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7 are respectively corresponding d0, d1, d2, d3, d4, d5, d6, d7 eight way word logic output signals among Fig. 5.As shown in Figure 4, IN0-IN7 is d0, d1, d2, d3, d4, d5, d6, d7 are eight tunnel level signals of input logic signal correspondence, respectively under synchronous triggering signal Tr0, Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7 effect, behind level shift circuit, select an analog switch U5 to connect the input of oscillograph Y-axis through multichannel.Scan synchronizing signal and level are selected decoding output synchronously, cycle timesharing scan round logic level skew output, and at this moment, oscillograph can be stablized the output layering and show eight road logical signal timing waveforms.Will send synchronizing signal simultaneously, the logic level of measured signal just is reproduced on the oscillograph.
Claims (3)
1, simple type digital circuit logic analyser is characterized in that adopting general purpose oscialloscope, and to be provided with the single-chip microcomputer be the signal acquisition processing circuit of central processing unit, and described signal acquisition processing circuit comprises:
8 or 16 passage multichannel data sample circuits, the multichannel data sampled signal is imported single-chip microcomputer P1 mouth through buffer interface, and is stored among the outer extension memory RAM;
The level shift change-over circuit, the multichannel data sampled signal that is stored in outer extension memory RAM is removed, the single-chip microcomputer expansion I/O interface is delivered in timesharing, the digital sampled signal of timesharing output is carried out the multilevel electrical level displacement conversion of digital signal in the level shift change-over circuit, the multiple signals of changing through level shift show with different zero coordinates on oscillograph by an oscillographic input channel;
Output circuit is a display terminal with described general purpose oscialloscope, and the outer synchronous triggering signal input port EXT and the Y-axis input port of its output interface and display terminal link, the timesharing output logic shift levels that circulates synchronizing cycle signal.
2, simple type digital circuit logic analyser according to claim 1 is characterized in that described sample circuit is provided with many grades of sample frequency.
3, simple type digital circuit logic analyser according to claim 1, it is characterized in that described level shift change-over circuit adopts a slice multi-path digital switch U6 and a slice multiway analog switch U5, the diode D1 that series connection is provided with, D2, D3, D4, D5, D6, D7 and D8 constitute bleeder circuit, between described bleeder circuit and earth terminal GND, series connection is provided with two diode D9 by switching tube Q1 control, D10, the base stage of switching tube Q1 connects multi-path digital switch U6's/the Z end, different voltage division signal inserts the signal input part at multiway analog switch U5 respectively, the eight tunnel level signal d0s corresponding with input logic signal, d1, d2, d3, d4, d5, d6 and d7 insert multi-path digital switch U6, control signal A from eight kinds of different states of characterized 0-7 of single-chip microcomputer, B, C inserts the control end of multi-path digital switch U6 and multiway analog switch U5 respectively, with the input port of the OUT termination general purpose oscialloscope of multiway analog switch U5.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007200430005U CN201116928Y (en) | 2007-08-22 | 2007-08-22 | Simple digital circuit logic analyzer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007200430005U CN201116928Y (en) | 2007-08-22 | 2007-08-22 | Simple digital circuit logic analyzer |
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| CN201116928Y true CN201116928Y (en) | 2008-09-17 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102236354A (en) * | 2010-05-06 | 2011-11-09 | 上海固泰科技有限公司 | Method for testing CAN (Controller Area Network) bus data link layer |
| CN102694544A (en) * | 2012-06-13 | 2012-09-26 | 上海第二工业大学 | Demonstration device for proving logical algebra inversion law |
| CN104297543A (en) * | 2013-07-16 | 2015-01-21 | 苏州普源精电科技有限公司 | Hybrid oscilloscope with channel synchronization function |
| CN107422255A (en) * | 2017-07-13 | 2017-12-01 | 南京信息工程大学 | A kind of digit chip fault detection system and its detection method |
| CN108828323A (en) * | 2018-08-09 | 2018-11-16 | 武汉软件工程职业学院(武汉市广播电视大学) | A kind of simple digital clocking signal analytical equipment |
-
2007
- 2007-08-22 CN CNU2007200430005U patent/CN201116928Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102236354A (en) * | 2010-05-06 | 2011-11-09 | 上海固泰科技有限公司 | Method for testing CAN (Controller Area Network) bus data link layer |
| CN102694544A (en) * | 2012-06-13 | 2012-09-26 | 上海第二工业大学 | Demonstration device for proving logical algebra inversion law |
| CN104297543A (en) * | 2013-07-16 | 2015-01-21 | 苏州普源精电科技有限公司 | Hybrid oscilloscope with channel synchronization function |
| CN104297543B (en) * | 2013-07-16 | 2019-02-01 | 苏州普源精电科技有限公司 | A kind of mixing oscillograph with Channel Synchronous function |
| CN107422255A (en) * | 2017-07-13 | 2017-12-01 | 南京信息工程大学 | A kind of digit chip fault detection system and its detection method |
| CN108828323A (en) * | 2018-08-09 | 2018-11-16 | 武汉软件工程职业学院(武汉市广播电视大学) | A kind of simple digital clocking signal analytical equipment |
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| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080917 Termination date: 20110822 |