CN201107405Y

CN201107405Y - ASIC module for implementing ping-pong operation in radar signal processing

Info

Publication number: CN201107405Y
Application number: CNU2007200810447U
Authority: CN
Inventors: 李磊; 何春; 刘辉华; 宗竹林; 黎亮; 周婉婷; 饶全林; 张�林; 刘伟; 李蜀霞
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2007-09-12
Filing date: 2007-09-12
Publication date: 2008-08-27
Anticipated expiration: 2017-09-12

Abstract

An ASIC module used to realize ping-pong operation in radar signal processing integrates two data processing modules into one integrated module; the peripheral of the integrated module is provided with two buffer SRAMs; the two data processing modules are respectively connected with the two SRAMs by a bus. The utility model uses two SRAMs to buffer at the same time, one of which is for reading and the other is for memory, so that the two data processing modules can work at the same time, which saves the waiting time for transmission data; according to the actual situation, a SRAM can work independently; therefore, paralleled operation and independent operation of the system can be realized; because the two data processing modules are integrated into the same module, the integration and processing efficiency of the system are greatly improved. The ASIC module is mainly applicable in radar signal processing.

Description

Realize the ASIC module of ping-pong operation in the Radar Signal Processing

Technical field

The utility model relates generally to a kind of ASIC module, specifically, relates to realize in a kind of Radar Signal Processing the ASIC module of ping-pong operation.

Background technology

In Radar Signal Processing, process of pulse-compression and Filtering Processing are two crucial processes, and the data transfer between two processes is also quite frequent.In general Radar Signal Processing process, independently pulse compression module that mostly adopts for the data between pulse compression and two processes of filtering and filtration module and plug-in SRAM realize, or FPGA and plug-in SRAM realization, this just causes system handles speed low, integrated poor, power consumption is big.

Along with the development of military confrontation technology, require that Radar Signal Processing process speed is faster, processing mode is more flexible.Radar Signal Processing hardware is realized just having higher requirement, and signal processing is more succinct, it is essential to become rapidly.In order to improve the speed of Radar Signal Processing, the system integration becomes key; Universal for chip simultaneously, can independence or certain functional module of combinatorial operation also be user's needs.

The utility model content

The problem that the utility model solved provides a kind of ASIC module that realizes ping-pong operation, is used for improving concurrency and independence between the Radar Signal Processing data processing module, improves level of integrated system and treatment effeciency thereof.

To achieve these goals, the utility model provides the ASIC module that realizes ping-pong operation in a kind of Radar Signal Processing, comprise integration module, in integration module, be provided with first data processing module and second data processing module, the integration module periphery also is provided with a SRAM and the 2nd SRAM, and first data processing module is connected by bus with the 2nd SRAM with a SRAM respectively with second data processing module.

Two data processing modules are set in the described integration module at least, two SRAM and two buses are set correspondingly at least.

Core concept of the present utility model is that two data processing modules are integrated in the integration module, and in the integration module periphery two buffering SRAM and SRAM is set, and adopts bus to carry out data transfer between data processing module and the SRAM.Utilize the buffer memory effect of SRAM, what two data processing modules replaced reads and writes two SRAM, promptly first data processing module is after SRAM storage data, data processing module second is from a SRAM reading of data, first data processing module is to the 2nd SRAM storage new data simultaneously, after second data processing module finishes from a SRAM reading of data, again from the 2nd SRAM reading of data, and this moment, first data processing module was stored new data to a SRAM once more, so alternately carry out reading and storing of data, promptly realize the parallel work-flow of two data processing modules, perhaps be ping-pong operation.Because the buffer memory effect of SRAM, two processes also can independently be carried out, and needn't require another process to work simultaneously, have promptly realized the independent operation of two data processing modules, and the user can operate as the case may be accordingly; Because two data processing modules are integrated in the same integration module, adopt two buffering SRAM to replace read-write, the stand-by period when having saved reading and writing data greatly, so not only improved the integrated level of system but also improved the data-handling efficiency of system.

The utility model is mainly used in the Radar Signal Processing, and described first data processing module and second data module mainly are meant process of pulse-compression module and Filtering Processing module.

According to embodiment of the present utility model, also can expand the utility model, a plurality of data processing modules can be set in integration module, corresponding with it, a plurality of buffering SRAM and multiple bus are set, thereby the parallel work-flow of the exchanges data between the realization multimode for the signal Processing of other type also provides good use for reference of planning, makes to the utlity model has very high practicality.

After below in conjunction with accompanying drawing, embodiment the utility model being described in detail, other characteristics of the present utility model, advantage will be more obvious.

Description of drawings

Fig. 1 is the module frame chart of prior art.

Fig. 2 is a module frame chart of the present utility model.

Fig. 3 is the module frame chart of the utility model-embodiment.

Embodiment

Describe embodiment of the present utility model in detail below in conjunction with accompanying drawing.

Fig. 1 is the module frame chart of prior art, as seen, data transfer mode between two data processing modules is: first data processing module 2 is after SRAM storage data finish, 3 couples of SRAM of second data processing module carry out data read, only carry out after data read finishes at second data processing module 3, first data processing module 2 could be stored new data to SRAM.Such data transfer mode can not realize that when system works two data processing modules work simultaneously, wasted the stand-by period in the transmittance process greatly, influence the work efficiency of system, because two data processing modules are occupied a chip respectively, make that the integrated level of system is very low simultaneously.

Embodiment

Based on Fig. 2, the course of work and the remarkable result thereof of the utility model in Radar Signal Processing is described, its module frame chart such as Fig. 3.

As Fig. 3, the data processing module in the Radar Signal Processing is divided into process of pulse-compression module 7 and Filtering Processing module 8, mainly is that process of pulse-compression module 7 is to Filtering Processing module 8 Data transmission.After data transfer begins, inceptive impulse compression result at first, deposit it in SRAM4 by bus 9 then, Filtering Processing module 8 reads data among the SRAM4 by bus 12, process of pulse-compression module 7 deposits new data in the 2nd SRAM5 by bus 10 simultaneously, after Filtering Processing module 8 has read data among the SRAM4, have by bus 11 and read data among the 2nd SRAM5, meanwhile, process of pulse-compression module 7 deposits new data in once more by bus 9 in a SRAM4, the storage of so alternately carrying out data with read.The pulse compression result finishes in the identical time with reading out in of filtering data writing of SRAM, what such two processes just can replace reads and writes two SRAM, the work that two modules can walk abreast and need not wait for data transmission procedure between the module, this has just improved the concurrency of pulse compression and filtering widely, accelerate the speed of data processing, improved the efficient that system data is handled.Simultaneously because the pulse compression result is buffered among the SRAM, and this makes that again the data read process of pulse compression result's transmittance process and Filtering Processing module is separate, two processes can be independent carries out work, has increased the dirigibility of processing procedure; Two data processing modules are integrated in the same integration module, have also improved the integrated level of system.

Claims

1. realize the ASIC module of ping-pong operation in the Radar Signal Processing, comprise integration module (1), in integration module (1), be provided with first data processing module (2) and second data processing module (3), it is characterized in that, integration module (1) periphery is provided with a SRAM (4) and the 2nd SRAM (5), and first data processing module (2) is connected by bus with the 2nd SRAM (5) with a SRAM (4) respectively with second data processing module (3).

2. realize the ASIC module of ping-pong operation in the Radar Signal Processing according to claim 1, it is characterized in that, two data processing modules are set in the described integration module (1) at least, two SRAM and two buses are set correspondingly at least.