CN201072644Y - Multifunctional driving circuit for metal net plate type plasma display panel test - Google Patents

Abstract

A multi-functional drive circuit used for inspection testing metal gauze plate-shaped plasma display panel is provided, which belongs to the technical field of display and comprises a logic control circuit (a) and a high-voltage waveform generating circuit (b). The logic control circuit (a) are composed of a programmable logic chip and a drive chip 74HC541. The high-voltage waveform generating circuit (b) comprises a positive-voltage energy recovery module (1), a positive-voltage maintenance module (2), a positive-direction reset module (3), a negative-voltage energy recovery module (4), a negative-voltage maintenance module (5), an isolating afterflow module (6), a negative-direction reset module (7), an addressing module (8), a row chip module (9), a data drive module (10) and a power module (11). The circuit device drives the metal gauze plate-shaped plasma display panel to display image by producing appropriate line data waveform and row scanning waveform.

Description

The test of metal sheet type plasma display panel multifunction drive circuit

Technical field

The utility model relates to a kind of metal mesh plate type plasma display panel, especially a kind of metal mesh plate type plasma display panel scan electrode, data electrode driver circuit, specifically a kind of test of metal sheet type plasma display panel multifunction drive circuit.

Background technology

The plasma panel display (PDP) that early 1990s rises has digitizing, giant-screen, and high resolving power, high definition, wide visual angle and thin thickness, advantage such as in light weight has vast potential for future development in the large screen display field.

The metal mesh plate type plasma display panel of developing at present is a kind of subtend discharge type AC plasma display panel, it is compared with conventional surface discharge type AC plasma display panel, have manufacturing process simply, easier realization high resolving power and manufacturing cost and driving low cost and other advantages, have the stronger market competitiveness.Structurally compare just because of this metal mesh plate type plasma display panel and to have than big difference with conventional surface discharge type AC plasma display panel, thereby be badly in need of the metal mesh plate type plasma display panel of multiple different structure is carried out the various characteristics test, the test job amount is huge, therefore design a kind of multifunction drive circuit device, the smaller screen that has a same structure with large-size screen monitors is carried out characteristic test, to satisfy to the quick test request of metal mesh plate type plasma display panel various characteristics, help metal mesh plate type plasma display panel to carry out technological improvement, improve the market competitiveness and have crucial meaning.

Summary of the invention

The purpose of this utility model is the mass property test problem that exists at existing metal mesh plate type plasma display panel, designs a kind of test of metal sheet type plasma display panel multifunction drive circuit of simple in structure, complete function.

The technical solution of the utility model is:

A kind of test of metal sheet type plasma display panel multifunction drive circuit, it is characterized in that it mainly produces circuit b by logic control circuit a, HT waveform and forms, two output terminals of logic control circuit a are received two input ends that HT waveform produces circuit b respectively, and two output terminals of HT waveform generation circuit b connect the line scanning electrode and the column data electrode of metal mesh plate type plasma display panel respectively; Described logic control circuit a is made up of programmable logic chip, its two output terminals are exported two groups of digital switch signal R1 respectively after driving through chip for driving, G1, B1, R2, G2, B2, COH, COL, CCLK, CSTB, CPOC, CBLK and XEPH, XEPL, XSPH, XSPL, XPRH, XPRH1, XPRH2, XENH, XENL, XSNH, XSNL, XSWP, XSWN, XVG2, XVG21, XVG22, XVG23, XVG1, XAD1, XAD2, XSTB, XBLK, XCLK, XSI, XHIZ, these two groups of digital switch signal controlling HT waveform produce circuit b and produce suitable column data waveform and line scanning waveform respectively and drive metal mesh plate type plasma display panel and carry out image and show; Described HT waveform produces circuit (b) by positive voltage energy recovery module 1, positive voltage is kept module 2, forward reseting module 3, negative voltage energy recovery module 4, negative voltage is kept module 5, isolate afterflow module 6, negative sense reseting module 7, addressed module 8, row chip module 9, data-driven module 10, power module 11 is formed, the input control signal XEPH that they are required, XEPL, XSPH, XSPL, XPRH, XPRH1, XPRH2, XENH, XENL, XSNH, XSNL, XSWP, XSWN, XVG2, XVG21, XVG22, XVG23, XVG1, XAD1, XAD2, XSTB, XBLK, XCLK, XSI, XHIZ, COH, COL, CCLK, CSTB, CPOC and CBLK are provided by logic control circuit a, wherein positive voltage is kept module 2, forward reseting module 3, negative voltage is kept module 5, negative sense reseting module 7, addressed module 8, the high-voltage signal VPS that data-driven module 10 is required, VPP, VNS, VNP, VNA, VER, VA is provided by dc high-voltage source module 11, the output terminal of forward reseting module 3, positive voltage is kept the output terminal of module 2, the output terminal of positive voltage energy recovery module 1 links to each other with an input end of isolating afterflow module 6 together, the output terminal of negative voltage energy recovery module 4, the output terminal that negative voltage is kept module 5 links to each other with another input end of isolating afterflow module 6 together, an output terminal of isolation afterflow module 6 links to each other with an input end of row chip module 9 with an output terminal of addressed module 8, another output terminal of isolating afterflow module 6, another output terminal of addressed module 8 and negative sense reseting module 7 output terminals link to each other with another input end of row chip module 9 together, the line scanning electrode that the output terminal of row chip module 9 is corresponding with metal mesh plate type plasma display panel links to each other, and the column data electrode that the output terminal of data-driven module 10 is corresponding with metal mesh plate type plasma display panel links to each other.

Described digital switch signal R1, G1, B1, R2, G2, B2, COH, COL, CCLK, CSTB, CPOC, CBLK is the input control signal of data-driven module 10, XEPH, XEPL is the input control signal of positive voltage energy recovery module 1, XSPH, XSPL is the input control signal that positive voltage is kept module 2, XPRH, XPRH1, XPRH2 is the input control signal of forward reseting module 3, XENH, XENL is the input control signal of negative voltage energy recovery module 4, XSNH, XSNL is the input control signal that negative voltage is kept module 5, XSWP, XSWN is the input control signal of isolating afterflow module 6, XVG2, XVG21, XVG22, XVG23 is the input control signal of negative sense reseting module 7, XVG1, XAD1, XAD2 is the input control signal of addressed module 8, XSTB, XBLK, XCLK, XSI, XHIZ is the input control signal of row chip module 9.

Described positive voltage energy recovery module 1 is made up of capacitor C 1, field effect transistor Q1, field effect transistor Q2, diode D1, diode D2 and inductance L 1, the input of positive voltage energy recovery module 1 is drawn digital switch signal output part XEPH and the XEPL that meets logic control circuit a from the grid of field effect transistor Q1, Q2 correspondence, and the output of positive voltage energy recovery module 1 is drawn the output terminal of keeping module 2 with output terminal, the positive voltage of forward reseting module 3 and linked to each other with an input end of isolating afterflow module 6 by an end of inductance L 1.

Described positive voltage is kept module 2 and is made up of diode D3, field effect transistor Q3, Q4, positive voltage is kept the input of module 2 and is drawn digital switch signal output part XSPH, the XSPL that meets logic control circuit a from the grid of field effect transistor Q3, Q4 correspondence, and it is that an end of inductance L 1 links to each other with an input end of isolating afterflow module 6 that positive voltage is kept output terminal that the output of module 2 draws output terminal with forward reseting module 3, positive voltage energy recovery module 1 from the tie point of the drain electrode of the source electrode of field effect transistor Q3, Q4.The input end that positive voltage is kept the high-voltage signal VPS of module 2 is drawn from the anode of diode D3 and is connect dc high-voltage source module 11 corresponding output terminals.

Described forward reseting module 3 is by field effect transistor Q5, Q6, Q7 and variable resistor VR1, VR2, VR3 forms, the input of forward reseting module 3 is from field effect transistor Q5, Q6, the grid of Q7 correspondence is drawn the digital switch signal output part XPRH that meets logic control circuit a, XPRH1, XPRH2, the output of forward reseting module 3 is from the source electrode of field effect transistor Q6, the source electrode of Q7, it is the end of L1 that the tie point of the end of variable resistor VR1 is drawn with the output terminal of positive voltage energy recovery module 1, the output terminal that positive voltage is kept module 2 links to each other with an input end of isolating afterflow module 6 together, and the input end of the high-voltage signal VPP of forward reseting module 3 is drawn the corresponding output terminal that connects dc high-voltage source module 11 from the drain electrode of field effect transistor Q5.

Described negative voltage energy recovery module 4 is made up of capacitor C 2, field effect transistor Q8, Q9, diode D4, D5 and inductance L 2, its input is drawn digital switch signal output part XENH, the XENL that meets logic control circuit a by the grid of field effect transistor Q8, Q9 correspondence, its output draw by an end of inductance L 2 and keep the output terminal of module 5 with negative voltage, an input end of isolating afterflow module 6 connects together.

Described negative voltage is kept module 5 and is made up of field effect transistor Q10, Q11 and diode D6, its input is drawn digital switch signal end XSNH, the XSNL that meets logic control circuit a from the grid of field effect transistor Q10, Q11 correspondence, its output from the tie point of the drain electrode of the source electrode of field effect transistor Q10, Q11 draw and with the output terminal of negative voltage energy recovery module 4 be that an end of inductance L 2, an input end of isolating afterflow module 6 connect together.Negative voltage is kept the input end of the high-voltage signal VNS of module 5 and is drawn the corresponding output terminal that connects dc high-voltage source module 11 from the negative electrode of diode D6.3, metal mesh plate type plasma display panel multifunction drive circuit device according to claim 1, it is characterized in that described isolation afterflow module 6 is by field effect transistor Q12, Q13, diode D7, D8 forms, its control input is respectively from field effect transistor Q12, the grid of Q13 correspondence is drawn the digital switch signal output part XSWP that meets corresponding logic control circuit a, XSWN, its other two-way input end is that the end of L1 and the output of negative voltage energy recovery module 4 are the end of L2 from the output that positive voltage energy recovery module 1 was drawn and connect respectively to the source electrode of the drain electrode of field effect transistor Q12 and field effect transistor Q13 respectively, and its two output terminals are in addition drawn from the drain electrode of the source electrode of field effect transistor Q12 and field effect transistor Q13 and connect addressed module 8 and negative sense reseting module 7 respectively.

Described negative sense reset circuit 7 is made up of field effect transistor Q14, Q15, Q16, Q17, diode D12 and variable resistor VR4, VR5, VR6, VR7.Its input is drawn digital switch signal output part XVG2, XVG21, XVG22, the XVG23 that meets logic control circuit a from the grid of field effect transistor Q14, Q15, Q16, Q17 correspondence, and its output is drawn with an output terminal of isolating afterflow module 6, an input end of row chip module 9, an output terminal of addressed module 8 from the anode of diode D12 and linked to each other.The high-voltage signal VNP of negative sense reset circuit 7 draws the corresponding output terminal that connects dc high-voltage source module 11 from the source electrode tie point of field effect transistor Q15, Q16, Q17.

Described addressed module 8 is by field effect transistor Q18, Q19, Q20 and diode D9, D10, D11 forms, its input end is from field effect transistor Q18, Q19, the grid of Q20 correspondence is drawn the digital switch signal output part XAD1 that meets logic control circuit a, XAD2, XVG1, its output is from the negative electrode of diode D9, the tie point of the anode of D10 is drawn and an output terminal of isolating afterflow module 6, the output terminal of negative sense reset circuit 7, an input end of row chip module 9 links to each other, and its another output terminal is drawn and another output terminal of isolating afterflow module 6 from the anode of D11, an input end of row chip module 9 connects together.High-voltage signal input end VNA, the VER of addressed module 8 draws the corresponding output terminal that connects dc high-voltage source module 11 from the tie point of the source electrode of field effect transistor Q18, Q19 and the source electrode of field effect transistor Q20 respectively.

Described capable chip module 9 is made up of row chip IC 1, its input end connects together with an output terminal of isolating afterflow module 6, an output terminal of addressed module 8, and the another one input end connects together with another output terminal of isolating afterflow module 6, the output terminal of negative sense reset circuit 7, another output terminal of addressed module 8; The control signal of row chip module 9 is provided by digital switch signal output part XSTB, XBLK, XCLK, XSI, the XHIZ of logic control circuit a; The line scanning electrode of the output termination metal mesh plate type plasma display panel of row chip module 9.

Described data-driven module 10 is made up of field effect transistor Q21, Q22, diode D13, row chip IC 2, its input is drawn digital switch signal output part COH, the COL that meets logic control circuit a from the grid of field effect transistor Q21, Q22 correspondence, the column data electrode of its output termination metal mesh plate type plasma display panel; The input control signal of row chip IC 2 meets digital switch signal output part CCLK, CSTB, CPOC and the CBLK of logic control circuit a.The input end of the high-voltage signal VA of data-driven module 10 is drawn from the positive pole of diode D13 and is connect dc high-voltage source module 11 corresponding output terminals.

The beneficial effects of the utility model:

(1) by selecting suitable circuit structure and components and parts, make the work compression resistance of this multifunction drive circuit device reach 800V, the work compression resistance here refers to the difference of ceiling voltage shown in Fig. 2 or Fig. 6 and minimum voltage.Simultaneously, this circuit arrangement has bigger carrying load ability, can drive 4 cun of metal mesh plate type plasma display panels, 6 cun, 8 cun screens.

(2) compare with existing driving circuit, by changing forward reseting module 3, the circuit of negative sense reset circuit 7 is formed, make drive waveforms can realize one section at the forward reset period, two sections, three slope over 10 change, reset at negative sense and to realize one section, two sections, three sections, four slope over 10 change, be fit to the metal otter board plasma display panel is carried out waveform optimization, seek and be fit to the reset wave that the metal otter board plasma display panel carries out real-time addressing, improve effective fluorescent lifetime of metal otter board plasma display panel, reduce the driving cost of metal otter board plasma display panel.

(3) compare with existing driving circuit, by the programmed control of logic control circuit and the difference of power supply are connected, can realize that the integral body of address period T2 moves as shown in Figure 2, minimum pulse width shown in Figure 6 is that (this waveform can realize that at the forward reset period one section, two sections, three slope over 10 change for the narrow pulsewidth selective erasing addressing waveforms of 100ns, reset at negative sense and to realize that one section, two sections, three sections, four slope over 10 change), exactly with the result who moves on the address period T2.

Description of drawings

Fig. 1 is a metal otter board plasma display panel multifunction drive circuit structural drawing of the present utility model.

Fig. 2 is the basic driver waveform synoptic diagram that the utility model can produce.

Fig. 3 is a logic control circuit theory diagram of the present utility model.

Fig. 4 is that HT waveform of the present utility model produces schematic block circuit diagram.

Fig. 5 is circuit theory diagrams that match with block diagram shown in Figure 4.

Fig. 6 utilizes circuit arrangement of the present utility model to produce selective erasing addressing waveforms synoptic diagram.

Embodiment

Below in conjunction with drawings and Examples the utility model is further described.

Shown in Fig. 1-6.

A kind of test of metal sheet type plasma display panel multifunction drive circuit, it mainly produces circuit b by logic control circuit a, HT waveform and forms.Two output terminals of logic control circuit a are received two input ends that HT waveform produces circuit b respectively, and two output terminals of HT waveform generation circuit b connect the line scanning electrode and the column data electrode of metal mesh plate type plasma display panel respectively.Logic control circuit a is made up of programmable logic chip (EP2C8T144C8), its two output terminals are exported two groups of digital switch signal R1 respectively after driving through chip for driving 74HC541, G1, B1, R2, G2, B2, COH, COL, CCLK, CSTB, CPOC, CBLK and XEPH, XEPL, XSPH, XSPL, XPRH, XPRH1, XPRH2, XENH, XENL, XSNH, XSNL, XSWP, XSWN, XVG2, XVG21, XVG22, XVG23, XVG1, XAD1, XAD2, XSTB, XBLK, XCLK, XSI, XHIZ, these two groups of digital switch signal controlling HT waveform produce circuit b and produce suitable column data waveform and line scanning waveform respectively and drive metal mesh plate type plasma display panel and carry out image and show.HT waveform produces circuit b by positive voltage energy recovery module 1, positive voltage is kept module 2, forward reseting module 3, negative voltage energy recovery module 4, negative voltage is kept module 5, isolate afterflow module 6, negative sense reseting module 7, addressed module 8, row chip module 9, data-driven module 10, power module 11 is formed, the input control signal XEPH that they are required, XEPL, XSPH, XSPL, XPRH, XPRH1, XPRH2, XENH, XENL, XSNH, XSNL, XSWP, XSWN, XVG2, XVG21, XVG22, XVG23, XVG1, XAD1, XAD2, XSTB, XBLK, XCLK, XSI, XHIZ, COH, COL, CCLK, CSTB, CPOC and CBLK are provided by logic control circuit a, wherein positive voltage is kept module 2, forward reseting module 3, negative voltage is kept module 5, negative sense reseting module 7, addressed module 8, the high-voltage signal VPS that data-driven module 10 is required, VPP, VNS, VNP, VNA, VER, VA is provided by dc high-voltage source module 11, the output terminal of forward reseting module 3, positive voltage is kept the output terminal of module 2, the output terminal of positive voltage energy recovery module 1 links to each other with an input end of isolating afterflow module 6 together, the output terminal of negative voltage energy recovery module 4, the output terminal that negative voltage is kept module 5 links to each other with another input end of isolating afterflow module 6 together, an output terminal of isolation afterflow module 6 links to each other with an input end of row chip module 9 with an output terminal of addressed module 8, another output terminal of isolating afterflow module 6, another output terminal of addressed module 8 and negative sense reseting module 7 output terminals link to each other with another input end of row chip module 9 together, the line scanning electrode that the output terminal of row chip module 9 is corresponding with metal mesh plate type plasma display panel links to each other, and the column data electrode that the output terminal of data-driven module 10 is corresponding with metal mesh plate type plasma display panel links to each other.

Logic control circuit a during concrete enforcement is shown in Fig. 1,3.Wherein: digital switch signal R1, G1, B1, R2, G2, B2, COH, COL, CCLK, CSTB, CPOC, CBLK is the input control signal of data-driven module 10, XEPH, XEPL is the input control signal of positive voltage energy recovery module 1, XSPH, XSPL is the input control signal that positive voltage is kept module 2, XPRH, XPRH1, XPRH2 is the input control signal of forward reseting module 3, XENH, XENL is the input control signal of negative voltage energy recovery module 4, XSNH, XSNL is the input control signal that negative voltage is kept module 5, XSWP, XSWN is the input control signal of isolating afterflow module 6, XVG2, XVG21, XVG22, XVG23 is the input control signal of negative sense reseting module 7, XVG1, XAD1, XAD2 is the input control signal of addressed module 8, XSTB, XBLK, XCLK, XSI, XHIZ is the input control signal of row chip module 9.

HT waveform during concrete enforcement produces circuit b as shown in Figure 5.Wherein: positive voltage energy recovery module 1 is made up of capacitor C 1, field effect transistor Q1, field effect transistor Q2, diode D1, diode D2 and inductance L 1, the input of positive voltage energy recovery module 1 is drawn digital switch signal output part XEPH and the XEPL that meets logic control circuit a from the grid of field effect transistor Q1, Q2 correspondence, and the output of positive voltage energy recovery module 1 is drawn the output terminal of keeping module 2 with output terminal, the positive voltage of forward reseting module 3 and linked to each other with an input end of isolating afterflow module 6 by an end of inductance L 1.Positive voltage is kept module 2 and is made up of diode D3, field effect transistor Q3, Q4, positive voltage is kept the input of module 2 and is drawn digital switch signal output part XSPH, the XSPL that meets logic control circuit a from the grid of field effect transistor Q3, Q4 correspondence, and it is that an end of inductance L 1 links to each other with an input end of isolating afterflow module 6 that positive voltage is kept output terminal that the output of module 2 draws output terminal with forward reseting module 3, positive voltage energy recovery module 1 from the tie point of the drain electrode of the source electrode of field effect transistor Q3, Q4.The input end that positive voltage is kept the high-voltage signal VPS of module 2 is drawn from the anode of diode D3 and is connect dc high-voltage source module 11 corresponding output terminals.Forward reseting module 3 is by field effect transistor Q5, Q6, Q7 and variable resistor VR1, VR2, VR3 forms, the input of forward reseting module 3 is from field effect transistor Q5, Q6, the grid of Q7 correspondence is drawn the digital switch signal output part XPRH that meets logic control circuit a, XPRH1, XPRH2, the output of forward reseting module 3 is from the source electrode of field effect transistor Q6, the source electrode of Q7, it is an end of inductance L 1 that the tie point of the end of variable resistor VR1 is drawn with the output terminal of positive voltage energy recovery module 1, the output terminal that positive voltage is kept module 2 links to each other with an input end of isolating afterflow module 6 together.The input end of the high-voltage signal VPP of forward reseting module 3 is drawn the corresponding output terminal that connects dc high-voltage source module 11 from the drain electrode of field effect transistor Q5.Negative voltage energy recovery module 4 is made up of capacitor C 2, field effect transistor Q8, Q9, diode D4, D5 and inductance L 2, its input is drawn digital switch signal output part XENH, the XENL that meets logic control circuit a by the grid of field effect transistor Q8, Q9 correspondence, its output draw by an end of inductance L 2 and keep the output terminal of module 5 with negative voltage, an input end of isolating afterflow module 6 connects together.Negative voltage is kept module 5 and is made up of field effect transistor Q10, Q11 and diode D6, its input is drawn digital switch signal end XSNH, the XSNL that meets logic control circuit a from the grid of field effect transistor Q10, Q11 correspondence, its output from the tie point of the drain electrode of the source electrode of field effect transistor Q10, Q11 draw and with the output terminal of negative voltage energy recovery module 4 (be that an end of inductance L 2, an input end of isolating afterflow module 6 connect together; Negative voltage is kept the input end of the high-voltage signal VNS of module 5 and is drawn the corresponding output terminal that connects dc high-voltage source module 11 from the negative electrode of diode D6.Isolate afterflow module 6 by field effect transistor Q12, Q13, diode D7, D8 forms, its control input is respectively from field effect transistor Q12, the grid of Q13 correspondence is drawn the digital switch signal output part XSWP that meets corresponding logic control circuit a, XSWN, its other two-way input end is that the end of L1 and the output of negative voltage energy recovery module 4 are the end of L2 from the output that positive voltage energy recovery module 1 was drawn and connect respectively to the source electrode of the drain electrode of field effect transistor Q12 and field effect transistor Q13 respectively, and its two output terminals are in addition drawn from the drain electrode of the source electrode of field effect transistor Q12 and field effect transistor Q13 and connect addressed module 8 and negative sense reseting module 7 respectively.Negative sense reset circuit 7 is made up of field effect transistor Q14, Q15, Q16, Q17, diode D12 and variable resistor VR4, VR5, VR6, VR7.Digital switch signal output part XVG2, XVG21, XVG22, the XVG23 that meets logic control circuit a drawn in its input from the grid of field effect transistor Q14, Q15, Q16, Q17 correspondence, its output is drawn with an output terminal of isolating afterflow module 6, an input end of row chip module 9, an output terminal of addressed module 8 from the anode of diode D12 and is linked to each other, and the high-voltage signal VNP of negative sense reset circuit 7 draws the corresponding output terminal that connects dc high-voltage source module 11 from the source electrode tie point of field effect transistor Q15, Q16, Q17.Addressed module 8 is by field effect transistor Q18, Q19, Q20 and diode D9, D10, D11 forms, its input end is from field effect transistor Q18, Q19, the grid of Q20 correspondence is drawn the digital switch signal output part XAD1 that meets logic control circuit a, XAD2, XVG1, its output is from the negative electrode of diode D9, the tie point of the anode of D10 is drawn and an output terminal of isolating afterflow module 6, the output terminal of negative sense reset circuit 7, an input end of row chip module 9 links to each other, and its another output terminal is drawn and another output terminal of isolating afterflow module 6 from the anode of D11, an input end of row chip module 9 connects together; High-voltage signal input end VNA, the VER of addressed module 8 draws the corresponding output terminal that connects dc high-voltage source module 11 from the tie point of the source electrode of field effect transistor Q18, Q19 and the source electrode of field effect transistor Q20 respectively.Row chip module 9 is made up of row chip IC 1, its input end connects together with an output terminal of isolating afterflow module 6, an output terminal of addressed module 8, and the another one input end connects together with another output terminal of isolating afterflow module 6, the output terminal of negative sense reset circuit 7, another output terminal of addressed module 8; The control signal of row chip module 9 is provided by digital switch signal output part XSTB, XBLK, XCLK, XSI, the XHIZ of logic control circuit a; The line scanning electrode of the output termination metal mesh plate type plasma display panel of row chip module 9.Data-driven module 10 is made up of field effect transistor Q21, Q22, diode D13, row chip IC 2, its input is drawn digital switch signal output part COH, the COL that meets logic control circuit a from the grid of field effect transistor Q21, Q22 correspondence, the column data electrode of its output termination metal mesh plate type plasma display panel; The control signal of row chip IC 2 meets digital switch signal output part CCLK, CSTB, CPOC and the CBLK of logic control circuit a.The input end of the high-voltage signal VA of data-driven module 10 is drawn from the positive pole of diode D13 and is connect dc high-voltage source module 11 corresponding output terminals.

Details are as follows:

The multifunction drive circuit device block diagram of driving metal mesh plate type plasma display panel of the present utility model such as Fig. 1, Fig. 3, shown in Figure 4, a series of metal electrodes have been drawn on the metal mesh plate type plasma display panel, be divided into two classes according to the function difference: column data electrode and line scanning electrode, the number of two class electrodes is relevant with the resolution of metal mesh plate type plasma display panel.When metal mesh plate type plasma display panel is implemented to drive, the output terminal of data-driven module 10, the output terminal of row chip module 9 need be linked to each other with the line scanning electrode with the corresponding column data electrode of smaller screen respectively, metal mesh plate type plasma display panel multifunction drive circuit device applies drive waveforms by giving smaller screen data electrode and scan electrode, reaches to drive the purpose that metal mesh plate type plasma display panel carries out the graph image demonstration.

Metal mesh plate type plasma display panel multifunction drive circuit device produces drive waveforms as shown in Figure 2, drive waveforms is mainly carried out reasonable combination by four parts shown in Figure 2 (T1, T2, T3, T4) and is formed, according to waveform individual features and function, the T1 waveform is called as reset wave, its duration can be 300us-500us, the T2 waveform is called as addressing waveforms, its duration is 100us-250us, the T3 waveform is called as keeps waveform, its duration can be 10us-2ms, the T4 waveform is called as pre-reset wave, and its duration can be 50us-150us.The utility model can provide bigger load current, satisfies the ability that drives 4 cun, 6 cun, 8 cun metal mesh plate type plasma display panels.The driving circuit schematic diagram as shown in Figure 5, it is the specific embodiments of Fig. 4 block diagram, mainly form in the driving circuit scheme by a series of metal oxide semiconductor field effect pipe MOSFET, fast recovery diode, electric capacity and inductance, wherein IC1 represents scanning drive chip (such as the STV7693 chip of ST company), and IC2 represents data driving chip (such as the STV7630 chip of ST company).Actual metal web plate type plasma display panel can be regarded a capacitive load as, is represented (being the Cp among Fig. 5) with Cp here.

As shown in Figure 1, two output terminals of logic control circuit a are connected with two input ends that HT waveform produces circuit b, and two output terminals of HT waveform generation circuit b connect the line scanning electrode and the column data electrode of metal mesh plate type plasma display panel respectively.Shown in Figure 2 is the basic driver waveform that metal mesh plate type plasma display panel multifunction drive circuit device produces, above-mentioned basic driver waveform outputs to the line scanning electrode and the column data electrode of metal mesh plate type plasma display panel, the waveform that outputs to the column data electrode can directly be produced by data driving chip, do not need driving circuit, also can produce by the internal drive circuits of data-driven module, the waveform that outputs to the line scanning electrode is exported by the scanning drive chip output terminal, sign VPS among Fig. 2, VNS, VPP, VNP, VNA, VER, VA is and Fig. 4, Fig. 5, the DC high-voltage power supply that is provided among Fig. 6 mutually one to one voltage indicate, concrete voltage magnitude is driven by metal mesh plate type plasma display panel and requires decision, wherein the difference of ceiling voltage and minimum voltage is the maximum operating voltage scope of this circuit arrangement less than 800V.

Fig. 3 is the theory diagram of multifunction drive circuit device low voltage logic control circuit a, this circuit is made up of with chip for driving 74HC541 programmable logic chip (EP2C8T144C8), its two output terminals are exported two groups of digital switch signal R1, G1, B1, R2, G2, B2, COH, COL, CCLK, CSTB, CPOC, CBLK and XEPH, XEPL, XSPH, XSPL, XPRH, XPRH1, XPRH2, XENH, XENL, XSNH, XSNL, XSWP, XSWN, XVG2, XVG21, XVG22, XVG23, XVG1, XAD1, XAD2, XSTB, XBLK, XCLK, XSI, XHIZ, these two groups of digital switch signal controlling HT waveform produce the suitable waveform of circuit b generation and drive the metal mesh plate type plasma display panel display image.

Fig. 4 be metal mesh plate type plasma display panel multifunction drive circuit device HT waveform produce the circuit block diagram of circuit b, this circuit arrangement is divided by function can be divided into that positive voltage energy recovery module 1, positive voltage keep that module 2, forward reseting module 3, negative voltage energy recovery module 4, negative voltage are kept module 5, isolated afterflow module 6, negative sense reseting module 7, addressed module 8, row chip module 9, data-driven module 10, power module 11.Positive voltage energy recovery module and positive voltage are kept the module co-ordination, on function, produce the needed positive voltage of driving display panel and keep pulse (the positive level pulse of T3 among Fig. 2), and bigger load current is provided, reduce the loss of idle current on circuit; Same negative voltage energy recovery module and negative voltage are kept the module co-ordination, produce the needed negative voltage of driving display panel and keep pulse (the negative level pulse of T3 among Fig. 2); Forward reseting module and negative sense reseting module are worked alone or synergistically, produce to drive required reset wave of display screen (T1 among Fig. 2) and pre-reset wave (T4 among Fig. 2); Addressed module produces and drives the needed addressing waveforms of display screen (T2 among Fig. 2); Isolate the afterflow module and mainly play the effect of isolating the generating positive and negative voltage circuit and being connected circuit module; The row chip module will output on the line scanning electrode of metal mesh plate type plasma display panel with the combined waveform displacement that upper module produces; The data-driven module outputs to the column data waveform on the column data electrode of metal mesh plate type plasma display panel; Power module provides DC high-voltage power supply VPS, VNS, VPP, VNP, VNA, VER, VA for HT waveform produces circuit.

In conjunction with the concrete driving circuit schematic diagram of Fig. 5, the positive voltage energy recovery module is by C1, Q1, Q2, D1, D2 and L1 form, positive voltage is kept module by D3, Q3 and Q4 form, the forward reseting module is by Q5, Q6, Q7 and VR1, VR2, VR3 forms, the negative voltage energy recovery module is by C2, Q8, Q9, D4, D5 and L2 form, negative voltage is kept module by D6, Q10, Q11 forms, isolate the afterflow module by Q12, Q13, D7 and D8 form, the negative sense reset circuit is by Q14, Q15, Q16, Q17, VR4, VR5, VR6, VR7 and D12 form, addressed module is by Q18, Q19, Q20, D9, D10, D11 forms, the data-driven module is by D13, Q21, Q22, IC2 forms, and the row chip module is made up of IC1; Above-mentioned positive voltage energy recovery module is kept module output terminal (being source electrode and the MOSFET Q4 drain electrode tie point of MOSFET Q3) by the end output of inductance L 1 with positive voltage, an input end of forward reseting module output terminal (being the source electrode and MOSFET Q7 source electrode tie point of MOSFET Q6) and isolation afterflow module (being Q12 drain electrode and D8 cathode connection) links to each other, the end output of negative voltage energy recovery module by inductance L 2 and negative voltage are kept module output (being the source electrode of Q10 and the drain electrode tie point of Q11) and input end of isolation afterflow module (being the Q13 source electrode and the anode tie point of D7) and are linked to each other, negative sense reseting module output terminal (being the anode of D12) and an output terminal of isolating the afterflow module (being Q13 drain electrode and D8 anode tie point), an output terminal of addressed module circuit (being D9 negative electrode and D10 anode tie point) interconnects with an input end of row chip module and links to each other, and another output terminal of addressed module circuit (being the D11 anode) links to each other with an output terminal (being Q12 source electrode and D7 cathode connection) of isolating the afterflow module another input end with the row chip module; The data-driven module is output as the tie point of output or the Q21 source electrode and the Q22 drain electrode of row chip IC 2.

The R1 that the control input end of above-mentioned mentioned module is among Fig. 1 to be marked among Fig. 5, G1, B1, R2, G2, B2, COH, COL, CCLK, CSTB, CPOC, CBLK and XEPH, XEPL, XSPH, XSPL, XPRH, XPRH1, XPRH2, XENH, XENL, XSNH, XSNL, XSWP, XSWN, XVG2, XVG21, XVG22, XVG23, XVG1, XAD1, XAD2, XSTB, XBLK, XCLK, XSI, these 37 control signals of XHIZ, these control signals all are to be produced by logic control circuit a, and dc high-voltage source module 11 provides Fig. 2, the VPS that is marked among Fig. 6, VPP, VNS, VNP, VNA, VER, these 7 groups of high pressure of VA.

By carrying out user program, logic control circuit a control HT waveform shown in Figure 5 shown in Figure 3 produces circuit b, can produce the needed basic driver waveform of driving metal mesh plate type plasma display panel shown in Figure 2, also can produce selective erasing addressing waveforms shown in Figure 6.To describe in detail respectively by effectively controlling HT waveform according to the four-stage (T1, T2, T3, T4) of drive waveforms below and produce circuit b generation needed four waveform stages of driving metal mesh plate type plasma display panel shown in Figure 2.

The control flow that basic driver waveform T3 takes place is as follows: before T3, Q4 among the MOSFET, Q10, Q12, Q13 are in and open conducting state, all the other all MOSFET are in and close by state, at this moment line driving chip ground end, power end keep system earth GND, and all scanning drive chips are output as GND; Enter T3 100ns before, at first close Q4, Q13, open Q1 when entering T3, the energy of storage charges to Cp by current direction path C1-Q1-D1-L1-Q12-IC1-Cp on the capacitor C 1, charging process (this process time length is determined by the size of L1 and Cp), be called forward energy and recover the rise time) when finishing, scanning chip output voltage can be very near VPS, close Q1 this moment, open Q3, VPS provides VPS power supply by VPS-D3-Q3-Q12-IC1-Cp to Cp, in order to providing metal mesh plate type plasma display panel internal element discharge required energy, the time span that Q3 opens (being called forward holds time) can and be kept frequency requirement and select flexibly according to the concrete condition of metal mesh plate type plasma display panel; Forward is held time and is closed Q3 when finishing, open Q2 then, the last energy by original charging gained of Cp discharges by current direction path Cp-IC1-D8-L1-D2-Q2-C1 conversely, with energy recovery in C1, when discharge finishes, scanning chip output voltage can be very near GND, this length discharge time (forward energy is recovered fall time) is mainly determined by the size of L1 and Cp, general size is got with the forward energy recovery rise time and is equated substantially, after forward energy is recovered to finish fall time, close Q2, open Q4, Q13 then, make scanning chip IC 1 output to voltage clamp on the Cp at GND, has only Q4 this moment, Q10, Q12, four MOSFET of Q13 are in open mode, and all the other MOSFET are in closed condition, more than whole process constitute the forward of T3 phase and keep pulse; After the 200ns, at first close Q12, Q10, open Q9 then, Cp charges to C2 by current direction path Cp-IC1-Q13-L2-D5-Q9-C2, with energy recovery in C2, this process (is called the negative sense energy and recovers fall time, mainly the size by L2 and Cp is determined) when finishing, scanning chip output voltage can be very near VNS, close Q9 this moment, open Q11, power supply VNS provides VNS power supply by VNS-D6-Q11-Q13-IC1-Cp to Cp, in order to provide the discharge of metal mesh plate type plasma display panel internal element required energy, the time span that Q11 opens (being called negative sense holds time) can and be kept frequency requirement and select flexibly according to the concrete condition of metal mesh plate type plasma display panel, here the symmetry of considering drive waveforms is generally got negative sense and is held time and equal forward and hold time, negative sense is held time and is at first closed Q11 when finishing, open Q8 then, the energy of storage charges to Cp by current direction path C2-Q8-D4-L2-D7-IC1-Cp on the capacitor C 2, this process (be called the negative sense energy and recover the rise time) time span is mainly determined by the size of L2 and Cp, consider the symmetry of waveform, get L1=L2, forward energy is recovered the rise time like this, forward energy is recovered fall time, the negative sense energy recovers fall time, it is equal substantially that the negative sense energy recovers the rise time; The negative sense energy recovery rise time is when finishing, close Q8, open Q10, Q12 then, make scanning chip IC 1 output to voltage clamp on the Cp at GND, have only Q4, Q10, four MOSFET of Q12, Q13 to be in open mode this moment, all the other MOSFET are in closed condition, more than whole process constitute the negative sense of T3 phase and keep pulse; Need to prove that because the power supply of IC1 and the existence of the parasitic diode between the ground, make that the power supply of IC1 and ground voltage are equal substantially in whole T3 period, the T3 process all flows through from IC1 endophyte diode the charge and discharge electric current of Cp.Forward is kept pulse and negative sense and is kept pulse and form one and keep pulsegroup, and a plurality of pulsegroup of keeping are formed one and kept the phase, i.e. T3.

The control flow that basic driver waveform T1 takes place is as follows: enter before the T1, has only Q4, Q10, Q12, four MOSFET of Q13 are in open mode, all the other MOSFET are in closed condition, make line driving chip ground hold, power end keeps system earth GND, all scanning drive chips are output as GND, at first close Q4, Q13, open Q6 then, Q7, finish the preliminary work that the oblique wave that resets rises, open Q5 then, enter first section rising oblique wave of T1 this moment, because resistance VR1, VR2, the VR3 parallel resistance is very little, the slope of first section rising oblique wave is very steep, when first section rising oblique wave finishes, close Q7, enter second section rising oblique wave of T1, because resistance VR1, the parallel resistance of VR2 compares VR1, VR2, the parallel resistance of VR3 is big, second section rising ramp slopes is littler than the slope of first section rising oblique wave, when second section rising oblique wave finishes, closes Q5, enter the 3rd section rising oblique wave of T1, because resistance VR1 compares VR1, the parallel resistance of VR2 is big, and the 3rd section rising ramp slopes is littler than the slope of second section rising oblique wave, and three sections oblique waves rise after the end, scanning chip output voltage can be very near VPP, and above process constitutes the oblique wave rising stage of T1 phase; Afterwards, close Q5, Q12, open Q4 then, Q15, Q16, Q17 carries out the preliminary work that T3 phase oblique wave descends, open Q14 then, enter first section decline oblique wave, because resistance VR4, VR5, VR6, the VR7 parallel resistance is very little, the slope of first section decline oblique wave is very steep, when first section decline oblique wave finishes, close Q17, enter second section decline oblique wave, because resistance VR4, VR5, the VR6 parallel resistance compares VR4, VR5, VR6, the VR7 parallel resistance is little, second section decline ramp slopes is littler than first section decline ramp slopes, when second section decline oblique wave finishes, close Q16, it is oblique to enter the 3rd section decline oblique wave, because resistance VR4, VR5 compares VR4, VR5, the VR6 parallel resistance is little, the 3rd section decline ramp slopes is littler than second section decline ramp slopes, when the 3rd section decline oblique wave finishes, closes Q15, it is oblique to enter the 4th section decline oblique wave, because resistance VR4 compares VR4, the VR5 parallel resistance is little, and the 4th section decline ramp slopes is littler than the 3rd section decline ramp slopes, and above process constitutes the oblique wave decrement phase of T1 phase; Oblique wave rising stage and oblique wave decrement phase are formed whole T1 reset period.When T1 finishes, when scanning chip output voltage reaches VNP, close Q14.

The control flow that basic driver waveform T2 takes place is as follows: at first when basic driver waveform T1 done state takes place by as can be known drive waveforms be in the VNP current potential, have only Q4, Q11 to open.Open Q18, Q19, Q20, at this time go the power supply termination VNA current potential of chip IC 1, ground termination VNP current potential, the voltage difference of VNA-VNP constitutes the operating voltage of row chip, this voltage is determined by the voltage-resistent characteristic of chip, in actual the driving, VNA is greater than VNP, when deciding, VNP can select suitable VNA like this, after the row chip applies operating voltage, the chip controls of being expert at signal XSTB, XBLK, XCLK, XSI, XHIZ control down, row chip displacement output addressing pulse is to the line scanning electrode, the output voltage amplitude of respective column data electrode is the data of VA, can finish the addressing igniting of respective pixel point on the metal mesh plate type plasma display panel like this, and the pulsewidth width of addressing igniting is mainly determined by the characteristic of metal mesh plate type plasma display panel.When addressing finishes, close Q10, Q20 earlier, open Q13 again, make the row chip power, hold and all connect voltage VNA, then close Q18, Q19, open Q10, Q12 then, make scan electrode output clamper to GND.

The control flow that basic driver waveform T4 takes place is as follows: before the T4, have only Q4, Q10, four MOSFET of Q12, Q13 to be in open mode, close Q12, Q13 earlier, open Q15, carry out the preliminary work that T4 begins, open Q14 then, enter the oblique wave decline stage, oblique wave descended after a period of time, close Q14, must accurately provide by experiment this fall time, makes that voltage is to close Q14 near just in time dropping to VNS, forms the decline oblique wave that does not drop to VNP fully.After voltage drops to VNS, close Q14, close Q15 again, open Q12, Q13 then, make scan electrode output clamper to GND.

Required basic waveform T1, T2, T3, the T4 of driving metal mesh plate type plasma display panel can produce circuit b by effective control HT waveform and produce among Fig. 2, constitutes embodiment 1 of the present utility model.

Driving metal mesh plate type plasma display panel selective erasing addressing waveforms shown in Figure 6 also can connect and control Driver Circuit by changing power supply, make and move on the address period among Fig. 2 and produce, need receive GND this moment with VNP, VNA, and this constitutes embodiment 2 of the present utility model.

Can equal the minimum voltage (less than VNS) of system for power supply VNP shown in Figure 5, also can equal VNS, can also equal GND, different power supply connections can produce different wave, but control flow is difference to some extent, selects VNP to equal the minimum voltage (less than VNS) of system in embodiment 1, selects VNP to equal GND in embodiment 2, when VNP equals VNS, constitute embodiment 3 of the present utility model.

In above embodiment, VNA voltage changes, as long as it is constant to satisfy the voltage difference of VNA-VER, this voltage difference is exactly the operating voltage of row chip.

Claims (10)

1. test of metal sheet type plasma display panel multifunction drive circuit, it is characterized in that it mainly produces circuit (b) by logic control circuit (a), HT waveform and forms, two output terminals of logic control circuit (a) are received two input ends that HT waveform produces circuit (b) respectively, and two output terminals of HT waveform generation circuit (b) connect the line scanning electrode and the column data electrode of metal mesh plate type plasma display panel respectively; Described logic control circuit (a) is made up of programmable logic chip, its two output terminals are exported two groups of digital switch signal R1 respectively after driving through chip for driving, G1, B1, R2, G2, B2, COH, COL, CCLK, CSTB, CPOC, CBLK and XEPH, XEPL, XSPH, XSPL, XPRH, XPRH1, XPRH2, XENH, XENL, XSNH, XSNL, XSWP, XSWN, XVG2, XVG21, XVG22, XVG23, XVG1, XAD1, XAD2, XSTB, XBLK, XCLK, XSI, XHIZ, these two groups of digital switch signal controlling HT waveform produce circuit (b) and produce suitable column data waveform and line scanning waveform respectively and drive metal mesh plate type plasma display panel and carry out image and show; Described HT waveform produces circuit (b) by positive voltage energy recovery module (1), positive voltage is kept module (2), forward reseting module (3), negative voltage energy recovery module (4), negative voltage is kept module (5), isolate afterflow module (6), negative sense reseting module (7), addressed module (8), row chip module (9), data-driven module (10), power module (11) is formed, the input control signal XEPH that they are required, XEPL, XSPH, XSPL, XPRH, XPRH1, XPRH2, XENH, XENL, XSNH, XSNL, XSWP, XSWN, XVG2, XVG21, XVG22, XVG23, XVG1, XAD1, XAD2, XSTB, XBLK, XCLK, XSI, XHIZ, COH, COL, CCLK, CSTB, CPOC and CBLK are provided by logic control circuit (a), wherein positive voltage is kept module (2), forward reseting module (3), negative voltage is kept module (5), negative sense reseting module (7), addressed module (8), the high-voltage signal VPS that data-driven module (10) is required, VPP, VNS, VNP, VNA, VER, VA is provided by dc high-voltage source module (11), the output terminal of forward reseting module (3), positive voltage is kept the output terminal of module (2), the output terminal of positive voltage energy recovery module (1) links to each other with an input end of isolating afterflow module (6) together, the output terminal of negative voltage energy recovery module (4), the output terminal that negative voltage is kept module (5) links to each other with another input end of isolating afterflow module (6) together, an output terminal of isolation afterflow module (6) links to each other with an input end of row chip module (9) with an output terminal of addressed module (8), another output terminal of isolating afterflow module (6), another output terminal of addressed module (8) and negative sense reseting module (7) output terminal link to each other with another input end of row chip module (9) together, the line scanning electrode that the output terminal of row chip module (9) is corresponding with metal mesh plate type plasma display panel links to each other, and the column data electrode that the output terminal of data-driven module (10) is corresponding with metal mesh plate type plasma display panel links to each other.

2. test of metal sheet type plasma display panel multifunction drive circuit according to claim 1, it is characterized in that described digital switch signal R1, G1, B1, R2, G2, B2, COH, COL, CCLK, CSTB, CPOC, CBLK is the input control signal of data-driven module (10), XEPH, XEPL is the input control signal of positive voltage energy recovery module (1), XSPH, XSPL is the input control signal that positive voltage is kept module (2), XPRH, XPRH1, XPRH2 is the input control signal of forward reseting module (3), XENH, XENL is the input control signal of negative voltage energy recovery module (4), XSNH, XSNL is the input control signal that negative voltage is kept module (5), XSWP, XSWN is the input control signal of isolating afterflow module (6), XVG2, XVG21, XVG22, XVG23 is the input control signal of negative sense reseting module (7), XVG1, XAD1, XAD2 is the input control signal of addressed module (8), XSTB, XBLK, XCLK, XSI, XHIZ is the input control signal of row chip module (9).

3. test of metal sheet type plasma display panel multifunction drive circuit according to claim 1, it is characterized in that described positive voltage energy recovery module (1) is by capacitor C 1, field effect transistor Q1, field effect transistor Q2, diode D1, diode D2 and inductance L 1 are formed, the input of positive voltage energy recovery module (1) is from field effect transistor Q1, the grid of Q2 correspondence is drawn digital switch signal output part XEPH and the XEPL that connects logic control circuit (a), and the output of positive voltage energy recovery module (1) is drawn output terminal with forward reseting module (3) by an end of inductance L 1, the output terminal that positive voltage is kept module (2) links to each other with an input end of isolating afterflow module (6) together.

4. test of metal sheet type plasma display panel multifunction drive circuit according to claim 1, it is characterized in that described positive voltage keeps module (2) by diode D3, field effect transistor Q3, Q4 forms, positive voltage is kept the input of module (2) from field effect transistor Q3, the grid of Q4 correspondence is drawn the digital switch signal output part XSPH that connects logic control circuit (a), XSPL, positive voltage is kept the source electrode of the output of module (2) from field effect transistor Q3, the tie point of the drain electrode of Q4 is drawn the output terminal with forward reseting module (3), the output terminal of positive voltage energy recovery module (1) is that an end of inductance L 1 links to each other with an input end of isolating afterflow module (6) together, and the input end that positive voltage is kept the high-voltage signal VPS of module (2) is drawn from the anode of diode D3 and connect the corresponding output terminal of dc high-voltage source module (11); Described forward reseting module (3) is by field effect transistor Q5, Q6, Q7 and variable resistor VR1, VR2, VR3 forms, the input of forward reseting module (3) is from field effect transistor Q5, Q6, the grid of Q7 correspondence is drawn the digital switch signal output part XPRH that connects logic control circuit (a), XPRH1, XPRH2, the output of forward reseting module (3) is from the source electrode of field effect transistor Q6, the source electrode of Q7, it is the end of L1 that the tie point of the end of variable resistor VR1 is drawn with the output terminal of positive voltage energy recovery module (1), the output terminal that positive voltage is kept module (2) links to each other with an input end of isolating afterflow module (6) together, and the input end of the high-voltage signal VPP of forward reseting module (3) is drawn the corresponding output terminal that connects dc high-voltage source module (11) from the drain electrode of field effect transistor Q5.

5. test of metal sheet type plasma display panel multifunction drive circuit according to claim 1, it is characterized in that described negative voltage energy recovery module (4) is made up of capacitor C 2, field effect transistor Q8, Q9, diode D4, D5 and inductance L 2, its input is drawn digital switch signal output part XENH, the XENL that connects logic control circuit (a) by the grid of field effect transistor Q8, Q9 correspondence, its output draw by an end of inductance L 2 and keep the output terminal of module (5) with negative voltage, an input end of isolating afterflow module (6) connects together; Described negative voltage is kept module (5) and is made up of field effect transistor Q10, Q11 and diode D6, its input is drawn digital switch signal end XSNH, the XSNL that connects logic control circuit (a) from the grid of field effect transistor Q10, Q11 correspondence, its output from the tie point of the drain electrode of the source electrode of field effect transistor Q10, Q11 draw and with the output terminal of negative voltage energy recovery module (4) be that an end of inductance L 2, an input end of isolating afterflow module (6) connect together; Negative voltage is kept the input end of the high-voltage signal VNS of module (5) and is drawn the corresponding output terminal that connects dc high-voltage source module (11) from the negative electrode of diode D6.

6. metal mesh plate type plasma display panel multifunction drive circuit device according to claim 1, it is characterized in that described isolation afterflow module (6) is by field effect transistor Q12, Q13, diode D7, D8 forms, its control input is respectively from field effect transistor Q12, the grid of Q13 correspondence is drawn the digital switch signal output part XSWP that connects corresponding logic control circuit (a), XSWN, the output (being the end of L1) of positive voltage energy recovery module (1) and the output (being the end of L2) of negative voltage energy recovery module (4) are drawn and connect respectively to its other two-way input end from the drain electrode of field effect transistor Q12 and the source electrode of field effect transistor Q13 respectively, and its in addition two output terminals are drawn from the drain electrode of the source electrode of field effect transistor Q12 and field effect transistor Q13 and connect addressed module (8) and negative sense reseting module (7) respectively.

7. test of metal sheet type plasma display panel multifunction drive circuit according to claim 1 is characterized in that described negative sense reset circuit (7) is made up of field effect transistor Q14, Q15, Q16, Q17, diode D12 and variable resistor VR4, VR5, VR6, VR7; Its input is drawn digital switch signal output part XVG2, XVG21, XVG22, the XVG23 that connects logic control circuit (a) from the grid of field effect transistor Q14, Q15, Q16, Q17 correspondence, and its output is drawn with an output terminal of isolating afterflow module (6), an input end of row chip module (9), an output terminal of addressed module (8) from the anode of diode D12 and linked to each other; The high-voltage signal VNP of negative sense reset circuit (7) draws the corresponding output terminal that connects dc high-voltage source module (11) from the source electrode tie point of field effect transistor Q15, Q16, Q17.

8. test of metal sheet type plasma display panel multifunction drive circuit according to claim 1, it is characterized in that described addressed module (8) is by field effect transistor Q18, Q19, Q20 and diode D9, D10, D11 forms, its input end is from field effect transistor Q18, Q19, the grid of Q20 correspondence is drawn the digital switch signal output part XAD1 that connects logic control circuit (a), XAD2, XVG1, its output is from the negative electrode of diode D9, the tie point of the anode of D10 is drawn and an output terminal of isolating afterflow module (6), the output terminal of negative sense reset circuit (7), an input end of row chip module (9) links to each other, and its another output terminal is drawn and another output terminal of isolating afterflow module (6) from the anode of D11, an input end of row chip module (9) connects together; High-voltage signal input end VNA, the VER of addressed module (8) draws the corresponding output terminal that connects dc high-voltage source module (11) from the tie point of the source electrode of field effect transistor Q18, Q19 and the source electrode of field effect transistor Q20 respectively.

9. test of metal sheet type plasma display panel multifunction drive circuit according to claim 1, it is characterized in that described capable chip module (9) by the row chip IC 1 form, its input end connects together with an output terminal of isolating afterflow module (6), an output terminal of addressed module (8), and the another one input end connects together with another output terminal of isolating afterflow module (6), the output terminal of negative sense reset circuit (7), another output terminal of addressed module (8); The control signal of row chip module (9) is provided by digital switch signal output part XSTB, XBLK, XCLK, XSI, the XHIZ of logic control circuit (a); The line scanning electrode of the output termination metal mesh plate type plasma display panel of row chip module (9).

10. test of metal sheet type plasma display panel multifunction drive circuit according to claim 1, it is characterized in that described data-driven module (10) is made up of field effect transistor Q21, Q22, diode D13, row chip IC 2, its input is drawn digital switch signal output part COH, the COL that connects logic control circuit (a) from the grid of field effect transistor Q21, Q22 correspondence, the column data electrode of its output termination metal mesh plate type plasma display panel; The input control signal of row chip IC 2 meets digital switch signal output part CCLK, CSTB, CPOC and the CBLK of logic control circuit (a); The input end of the high-voltage signal VA of data-driven module (10) is drawn from the positive pole of diode D13 and is connect the corresponding output terminal of dc high-voltage source module (11).

Images