CN100530299C - Drive circuit for metal mesh plate type plasma display panel - Google Patents

Abstract

A novel driving circuit device for metal net plate plasma display panel belongs to the display technical field. The invention mainly consists of an energy restoration module (1), a maintaining module (2), a sweeping module (3), a separation module (4), a reposition module (5), and an addressing module (6). A digital signal generator (7) provides the control input signals XERH, XERL, XSUH, XSUL, XERA, XPAS, XRST, XADD, and XSOT needed by the circuit modules. The invention solves the problem that similar circuits have too many components, high cost, and poor reliability, and has the advantages of simple circuit, few components, and low cost.

Description

The metal mesh plate type plasma display panel driving circuit

Technical field

The present invention relates to a kind of metal mesh plate type plasma display panel, especially a kind of metal mesh plate type plasma display panel scan electrode driving circuit, specifically a kind of driving metal mesh plate type plasma display panel driving circuit.

Background technology

At present, plasma display panel has advantages such as light, thin, that screen is big, the visual angle is wide, inertia is little equally as a concrete flat-panel display device, has vast potential for future development in the large screen display field.

A kind of subtend discharge type AC plasma of metal mesh plate type plasma display panel display panel of developing at present, it is compared with conventional surface discharge type AC plasma display panel, have manufacturing process simply, easier realization high resolving power and manufacturing cost and driving low cost and other advantages, have the stronger market competitiveness.Structurally compare just because of this metal mesh plate type plasma display panel and to have than big difference with conventional surface discharge type AC plasma display panel, need design a kind of brand-new driving circuit at the metal mesh plate type plasma display panel of new construction, drive requirement to satisfy metal mesh plate type plasma display panel, and satisfy high-performance and requirement cheaply, embody technical advance from the angle of design of drive circuit, improve product market competitiveness with circuit cheaply.

Summary of the invention

The objective of the invention is to be badly in need of the problem of high-performance, cost drive circuit at metal mesh plate type plasma display panel, design a kind of simple in structure, cost low the metal mesh plate type plasma display panel driving circuit that is easy to realize.

Technical scheme of the present invention is:

A kind of metal mesh plate type plasma display panel driving circuit, it is characterized in that it is mainly by energy recovery module 1, keep module 2, wipe module 3, isolation module 4, reseting module 5 and addressed module 6 are formed, the required control input signals XERH of above-mentioned each circuit module, XERL, XSUH, XSUL, XERA, XPAS, XRST, XADD and XSOT are provided by digital signal generator 7, wherein energy recovery module 1, keep module 2, wipe module 3, the power supply input signal VPS that reseting module 5 and addressed module 6 are required, VNS, VSETUP and VADD are provided by D.C. regulated power supply 8, the output terminal of energy recovery module 1 and the output terminal of keeping module 2 and the output terminal of wiping module 3 link to each other with one road output terminal of isolation module 4 together, one road output terminal of another road output terminal of isolation module 4 and the output terminal of reseting module 5 and addressed module 6 links to each other with reference to ground input end XVSS with scanning drive chip IC1 together, and another road output terminal of addressed module 6 links to each other with the power input XVDD of scanning drive chip IC1.

Wherein:

Described energy recovery module 1 is by field effect transistor Q1, field effect transistor Q2, diode D1, diode D2, diode D3, diode D4 and inductance L 1 are formed, energy recovery module 1 control input signals is drawn digital switch signal output part XERH and the XERL that connects digital signal generator 7 from the grid of field effect transistor Q1 and field effect transistor Q2, one road power input of energy recovery module 1 links to each other with the power supply output signal VPS of D.C. regulated power supply 8 by diode D3 output terminal, another road power input links to each other with the power supply output signal VNS of D.C. regulated power supply 8 by the input end of diode D4, and the output terminal of energy recovery module 1 is drawn to connect by an end of inductance L 1 and kept module 2.

The described module 2 of keeping is made up of field effect transistor Q3 and field effect transistor Q4, keep module 2 control input signals and draw digital switch signal output part XSUH and the XSUL that connects digital signal generator 7 from the grid of field effect transistor Q3 and field effect transistor Q4, keeping the drain electrode of module 2 one road power inputs by field effect transistor Q3 links to each other with the power supply output signal VPS of D.C. regulated power supply 8, another road power input links to each other with the power supply output signal VNS of D.C. regulated power supply 8 by the source electrode of field effect transistor Q4, keep module 2 output and connect an end of the inductance L 1 the energy recovery module 1, connect simultaneously and wipe module 3 from the tie point of the drain electrode of the source electrode of field effect transistor Q3 and field effect transistor Q4.

The described module 3 of wiping is made up of with field effect transistor Q5 diode D5, variable resistor VR1, capacitor C 1, resistance R 1, wipe module 3 control input signals and draw the digital switch signal output part XERA that connects digital signal generator 7 by variable resistor VR1 diode D5 in parallel from the grid of field effect transistor Q5, wiping the source electrode of module 3 power inputs by field effect transistor Q5 links to each other with the power supply output signal VNS of D.C. regulated power supply 8, wipe module 3 output and connect the output terminal of keeping module 2, connect isolation module 4 simultaneously from the drain electrode tie point of resistance R 1 and field effect transistor Q5.

Described isolation module 4 is made up of field effect transistor Q6, isolation module 4 control input signals are drawn the digital switch signal output part XPAS that connects digital signal generator 7 by the grid of field effect transistor Q6, the source electrode of isolation module 4 one road output terminals by field effect transistor Q6 with wipe module 3 output terminals and link to each other, another road output terminal links to each other with reseting module 5 by the drain electrode of field effect transistor Q6.

Described reseting module 5 is by diode D6, variable resistor VR2, capacitor C 2, resistance R 2 is formed with field effect transistor Q7, reseting module 5 control input signals are drawn the digital switch signal output part XRST that connects digital signal generator 7 by variable resistor VR2 diode D6 in parallel from the grid of field effect transistor Q7, reseting module 5 power inputs meet the power supply output signal VSETUP of D.C. regulated power supply 8 by resistance R 2 and the drain electrode tie point of field effect transistor Q7, reseting module 5 outputs are drawn from the source electrode of field effect transistor Q7 and are connect isolation module 4 one road output terminals, link to each other with addressed module 6 simultaneously.

Described addressed module 6 is by diode D7, resistance R 3, field effect transistor Q9, field effect transistor Q8 and capacitor C 3 are formed, addressed module 6 control input signals are respectively from field effect transistor Q9, the grid of field effect transistor Q8 is drawn the digital switch signal output part XADD that connects corresponding digital signal generator 7 respectively, XSOT, addressed module 6 power inputs are by the power supply output signal VADD of diode D7 input termination D.C. regulated power supply 8, addressed module 6 one tunnel outputs are drawn the power input XVDD that meets scanning drive chip IC1 from the source electrode of field effect transistor Q9 and drain electrode and the capacitor C 3 one end tie points of field effect transistor Q8, another road output is drawn the output terminal that connects reseting module 5 from the source electrode of field effect transistor Q8 and the tie point of capacitor C 3 other ends, meets the reference ground input end XVSS of scanning drive chip IC1 simultaneously.

The present invention has the following advantages:

Circuit of the present invention is compared with existing driving circuit, by optimizing circuit design, reduced the quantity of circuit elements device and control signal in a large number, reduced the cost of driving circuit significantly, the circuit design of simplifying has reduced design complexities, also helps improving the display system overall performance.In specific implementation process, only need type and number by the crucial electronic devices and components of choose reasonable, just can drive the metal mesh plate type plasma display panel of any resolution and screen size size, same driving circuit of the present invention also is applicable to other ac plasma display panel.Circuit of the present invention produces the required basic driver waveform of metal mesh plate type plasma display panel except can be good at, and also has following four outstanding features:

(1) energy recovery circuit simplified design reduces circuit devcie in a large number, has reduced circuit cost.Positive voltage energy recovery circuit and negative voltage energy recovery circuit carried out the function optimization merging during circuit arrangement of the present invention will before design, and the circuit after the merging not only possesses the preceding identical functions of merging, and the Key Circuit components and parts are kept to original design half;

(2) holding circuit simplified design has reduced circuit devcie in a large number, has reduced circuit cost.Positive voltage holding circuit and negative voltage holding circuit carried out the function optimization merging during circuit arrangement of the present invention will before design equally, and the circuit after the merging equally not only possesses the preceding identical functions of merging, and the Key Circuit components and parts are kept to original design half;

(3) because (1) has simplified design with (2) are described with energy recovery circuit and holding circuit, cause in the circuit arrangement of the present invention the buffer circuit part also to be reduced to one the tunnel by previous two-way buffer circuit, reduce circuit devcie, reduced circuit cost;

(4) compare with previous design in the circuit arrangement of the present invention; increase extra storage capacitor C3 at the power input XVDD of scanning drive chip IC1 and between with reference to ground input end XVSS; weaken greatly since display system in addressing work because power supply supply response speed produces on the scanning drive chip IC1 waveform burr phenomena above the chip withstand voltage slowly; so not only played the effect of protection scanning drive chip IC1, and the minimizing of waveform burr phenomena also helps improving display system integral working and stability.

Description of drawings

Fig. 1 is the driving system structure synoptic diagram of metal mesh plate type plasma display panel of the present invention.

Fig. 2 is the needed basic driver waveform of a metal mesh plate type plasma display panel of the present invention synoptic diagram.

Fig. 3 is a drive circuit for metal mesh plate type plasma display panel theory diagram of the present invention.

Fig. 4 is an electrical schematic diagram that matches with block diagram shown in Figure 3.

Fig. 5 utilizes new drive circuit of the present invention to drive the phase of the keeping drive waveforms synoptic diagram that forms.

Embodiment

The present invention is further illustrated for following structure drawings and Examples.

Shown in Fig. 3,4.

A kind of drive circuit for metal mesh plate type plasma display panel, it is mainly by energy recovery module 1, keep module 2, wipe module 3, isolation module 4, reseting module 5 and addressed module 6 are formed, the required control input signals XERH of above-mentioned each circuit module, XERL, XSUH, XSUL, XERA, XPAS, XRST, XADD and XSOT are provided by digital signal generator 7, wherein energy recovery module 1, keep module 2, wipe module 3, the power supply input signal VPS that reseting module 5 and addressed module 6 are required, VNS, VSETUP and VADD are provided by D.C. regulated power supply 8, the output terminal of energy recovery module 1 and the output terminal of keeping module 2 and the output terminal of wiping module 3 link to each other with one road output terminal of isolation module 4 together, one road output terminal of another road output terminal of isolation module 4 and the output terminal of reseting module 5 and addressed module 6 links to each other with reference to ground input end XVSS with scanning drive chip IC1 together, and another road output terminal of addressed module 6 links to each other with the power input XVDD of scanning drive chip IC1.

Driving circuit figure during concrete enforcement as shown in Figure 4.Wherein: energy recovery module 1 is by field effect transistor Q1, field effect transistor Q2, diode D1, diode D2, diode D3, diode D4 and inductance L 1 are formed, energy recovery module 1 control input signals is drawn digital switch signal output part XERH and the XERL that connects digital signal generator 7 (can use FPGA circuit board programming to promote chip such as IR2113S and form) from the grid of field effect transistor Q1 and field effect transistor Q2, one road power input of energy recovery module 1 links to each other with the power supply output signal VPS of D.C. regulated power supply 8 by diode D3 output terminal, another road power input links to each other with the power supply output signal VNS of D.C. regulated power supply 8 by the input end of diode D4, and the output terminal of energy recovery module 1 is drawn to connect by an end of inductance L 1 and kept module 2.Keeping module 2 is made up of field effect transistor Q3 and field effect transistor Q4, keep module 2 control input signals and draw digital switch signal output part XSUH and the XSUL that connects digital signal generator 7 from the grid of field effect transistor Q3 and field effect transistor Q4, keeping the drain electrode of module 2 one road power inputs by field effect transistor Q3 links to each other with the power supply output signal VPS of D.C. regulated power supply 8, another road power input links to each other with the power supply output signal VNS of D.C. regulated power supply 8 by the source electrode of field effect transistor Q4, keep module 2 output and connect an end of the inductance L 1 the energy recovery module 1, connect simultaneously and wipe module 3 from the tie point of the drain electrode of the source electrode of field effect transistor Q3 and field effect transistor Q4.Wiping module 3 is made up of with field effect transistor Q5 diode D5, variable resistor VR1, capacitor C 1, resistance R 1, wipe module 3 control input signals and draw the digital switch signal output part XERA that connects digital signal generator 7 by variable resistor VR1 diode D5 in parallel from the grid of field effect transistor Q5, wiping the source electrode of module 3 power inputs by field effect transistor Q5 links to each other with the power supply output signal VNS of D.C. regulated power supply 8, wipe module 3 output and connect the output terminal of keeping module 2, connect isolation module 4 simultaneously from the drain electrode tie point of resistance R 1 and field effect transistor Q5.Isolation module 4 is made up of field effect transistor Q6, isolation module 4 control input signals are drawn the digital switch signal output part XPAS that connects digital signal generator 7 by the grid of field effect transistor Q6, the source electrode of isolation module 4 one road output terminals by field effect transistor Q6 with wipe module 3 output terminals and link to each other, another road output terminal links to each other with reseting module 5 by the drain electrode of field effect transistor Q6.Reseting module 5 is made up of with field effect transistor Q7 diode D6, variable resistor VR2, capacitor C 2, resistance R 2, reseting module 5 control input signals are drawn the digital switch signal output part XRST that connects digital signal generator 7 by variable resistor VR2 diode D6 in parallel from the grid of field effect transistor Q7, reseting module 5 power inputs meet the power supply output signal VSETUP of D.C. regulated power supply 8 by resistance R 2 and the drain electrode tie point of field effect transistor Q7, reseting module 5 outputs are drawn from the source electrode of field effect transistor Q7 and are connect isolation module 4 one road output terminals, link to each other with addressed module 6 simultaneously.Addressed module 6 is by diode D7, resistance R 3, field effect transistor Q9, field effect transistor Q8 and capacitor C 3 are formed, addressed module 6 control input signals are respectively from field effect transistor Q9, the grid of field effect transistor Q8 is drawn the digital switch signal output part XADD that connects corresponding digital signal generator 7 respectively, XSOT, addressed module 6 power inputs are by the power supply output signal VADD of diode D7 input termination D.C. regulated power supply 8, addressed module 6 one tunnel outputs are drawn the power input XVDD that meets scanning drive chip IC1 from the source electrode of field effect transistor Q9 and drain electrode and the capacitor C 3 one end tie points of field effect transistor Q8, another road output is drawn the output terminal that connects reseting module 5 from the source electrode of field effect transistor Q8 and the tie point of capacitor C 3 other ends, meets the reference ground input end XVSS of scanning drive chip IC1 simultaneously.

Details are as follows:

The drive system block diagram of driving metal mesh plate type plasma display panel of the present invention as shown in Figure 1, a series of metal electrodes have been drawn on the metal mesh plate type plasma display panel, be divided into two classes according to the function difference: electrode is kept in data electrode and scanning, and the number of two class electrodes is relevant with the resolution of metal mesh plate type plasma display panel.When metal mesh plate type plasma display panel is implemented to drive, data driving chip IC2, scanning drive chip IC1 need be linked to each other with scan electrode with corresponding data electrode, the metal mesh plate type plasma display panel driving circuit reaches the purpose that drives metal mesh plate type plasma display panel by scanning drive chip IC1 power end (XVDD) being provided to scanning drive chip and providing metal mesh plate type plasma display panel required basic driver waveform with reference to ground end (XVSS).Effectively drive the required basic driver waveform of metal mesh plate type plasma display panel as shown in Figure 2, needs according to the metal mesh plate type plasma display panel displaying principle, needed drive waveforms is mainly by four part (WP1 shown in Figure 2 when driving metal mesh plate type plasma display panel, WP2, WP3, WP4) carry out reasonable combination and form, according to waveform individual features and function, the WP1 waveform is called as reset wave, its duration can be 300us-500us, the WP2 waveform is called as addressing waveforms, its duration can be 500us-2ms, the WP3 waveform is called as keeps waveform, its duration can be 2us-5ms, the WP4 waveform is called as wipes waveform, and its duration can be 20us-300us.The theory diagram of a kind of novel metal web plate type plasma display panel driving circuit of the present invention as shown in Figure 3, can be good at producing scanning and keep the needed above-mentioned tetrameric basic driver waveform of electrode, and bigger load current is provided, satisfy the requirement of system drive.The concrete electrical schematic diagram of driving circuit as shown in Figure 4, it is the specific embodiments of Fig. 3 block diagram, in the driving circuit scheme mainly by a series of metal oxide semiconductor field effect pipes (MOSFET), the fast diode that recovers, electric capacity and inductance are formed, wherein IC1 represents scanning drive chip (such as the STV7617 chip of ST company), require the more scanning drive chip IC1 of needs according to resolution in the actual metal web plate type plasma display panel display system, here only provide a block diagram to do the explanation of scheme principle, metal mesh plate type plasma display panel can be regarded a capacitive load as in actual driving process, here represented with Cp, IC2 represents data driving chip (such as the STV7630 chip of ST company), require the more data driving chip IC2 of needs according to resolution in the actual metal web plate type plasma display panel display system, here also only provide a block diagram to do the explanation of scheme principle, represented in Fig. 4 lower dotted line frame is an equivalent schematic diagram.The relevant details of other technologies scheme will be described below in the whole driving method detail operations flow process and are described simultaneously among Fig. 1, Fig. 2, Fig. 3, Fig. 4.

As shown in Figure 1, the output of scanning drive chip IC1 and metal mesh plate type plasma display panel scanning are kept electrode is corresponding one by one to be connected.The output of data driving chip IC2 is connected with data electrode is corresponding one by one, the power end VA of data driving chip IC2 connects D.C. regulated power supply, drive requirement according to metal mesh plate type plasma display panel and select the suitable voltage amplitude, directly with systematically link to each other with reference to ground; The power end XVDD of scanning drive chip IC1 with all be connected with reference to ground end XVSS with metal mesh plate type plasma display panel new drive circuit in the present design.Shown in Figure 2 is to drive the required basic driver waveform of metal mesh plate type plasma display panel, above-mentioned basic driver waveform is kept electrode output by data electrode and scanning, the data electrode output waveform can directly be produced by data driving chip IC2, do not need driving circuit, scanning is kept the waveform of electrode output and is exported by scanning drive chip IC1 output terminal, but need metal mesh plate type plasma display panel new drive circuit of the present invention to be connected with scanning drive chip IC1, provide required drive waveforms by the metal mesh plate type plasma display panel new drive circuit, sign VPS among Fig. 2, VNS, VSETUP, VADD, VA all be with Fig. 4 in the D.C. regulated power supply that provided mutually one to one voltage indicate, concrete voltage magnitude is driven by metal mesh plate type plasma display panel and requires decision.

Fig. 3 is the driving circuit theory diagram of the metal mesh plate type plasma display panel invented in order to produce four kinds of basic driver waveforms shown in Figure 2, and this driving circuit scheme is divided by function can be divided into energy recovery module 1, keep module 2, wipe module 3, isolation module 4, reseting module 5, addressed module 6, digital signal generator 7 and D.C. regulated power supply 8.Energy recovery module 1 with keep module 2 co-ordinations, on function, produce and drive that display panel is needed keeps pulse (WP3 among Fig. 2), and effective load current is provided, and reduce the loss of idle current on circuit; Wipe module 3 and produce the needed waveform (WP4 among Fig. 2) of wiping of driving display screen; Reseting module 5 with wipe module 3 collaborative works, produce and drive the needed reset wave of display screen (WP1 among Fig. 2); Addressed module 6 produces and drives the needed addressing waveforms of display screen (WP2 among Fig. 2); Isolation module 4 mainly plays timesharing and isolates the effect that is connected reseting module 5, addressed module 6 and keeps module 2, energy recovery module 1.

Fig. 4 is the electrical schematic diagram of concrete driving circuit of the present invention, energy recovery module 1 is by field effect transistor Q1, Q2, diode D1, D2, D3, D4 and inductance L 1 are formed, keeping module 2 is made up of field effect transistor Q3 and Q4, wipe module 3 by diode D5, variable resistor VR1, capacitor C 1, resistance R 1 and field effect transistor Q5 form, isolation module 4 is made up of field effect transistor Q6, reseting module 5 is by diode D6, variable resistor VR2, capacitor C 2, resistance R 2 and field effect transistor Q7 form, and addressed module 6 is by diode D7, resistance R 3, field effect transistor Q9, Q8 and capacitor C 3 are formed; Above-mentioned energy recovery module 1 is exported by an end of inductance L 1 and is kept module 2 one output terminals (being the drain electrode junction of source electrode and the MOSFET Q4 of MOSFET Q3), output terminal (being the drain electrode of MOSFET Q5 and the junction of resistance R 1 one ends) and isolation module 4 one output terminals (being MOSFET Q6 source electrode) of wiping module 3 link to each other, reseting module 5 is by the source electrode output and isolation module 4 another output terminals (being MOSFET Q6 drain electrode) of MOSFET Q7, addressed module one output terminal (being the junction of source electrode with capacitor C 3 one ends of MOSFET Q8) and scanning drive chip IC1 link to each other with reference to ground end (being XVSS), and addressed module 6 another output terminals (being MOSFETQ8 drain electrode and the junction of the MOSFET Q9 source electrode and capacitor C 3 other ends) link to each other with the power input (being XVDD) of scanning drive chip IC1.

Connection between the above-mentioned mentioned module all is the connection of the output terminal of module, the XERH that the signal input end of each module is among Fig. 4 to be marked, XERL, XSUH, XSUL, XERA, XPAS, XRST, these 9 control signals of XADD and XSOT, these control signals are produced by digital signal generator 7, link to each other one by one with other circuit modules by digital signal generator 7 outputs, the VPS that the power input of each module is among Fig. 4 to be marked, VNS, this 4 road D.C. regulated power supply of VSETUP and VADD, these power supply input signals are provided by D.C. regulated power supply 8, are linked to each other one by one with the related circuit module by D.C. regulated power supply 8 outputs.

The technical scheme operating process is described:

By metal mesh plate type plasma display panel new drive circuit shown in Figure 4, can produce the needed basic driver waveform of driving metal mesh plate type plasma display panel shown in Figure 2, describe in detail respectively by effective control metal mesh plate type plasma display panel new drive circuit shown in Figure 4 according to four kinds of basic driver waveform situations below and produce the needed four kinds of basic driver waveforms of driving metal mesh plate type plasma display panel shown in Figure 2.

Because the control flow when producing basic driver waveform WP1, WP2, WP4 needs the part control flow of basic driver waveform WP3, so at first describe the control flow that produces waveform WP3.Fig. 5 is the basic waveform enlarged drawing of WP3, T1, T2, T3, T4 (are using 200kHz to keep under the frequency waveform situation the corresponding time period of waveform, can be respectively 0.7 μ s, 1.8 μ s, 0.7 μ s, 1.8 μ s), data driving chip output GND makes data electrode ground connection in the time of the basic driver waveform of output WP3, the gated sweep chip for driving is output as with reference to ground, i.e. output is XVSS.Whole control process is the process that an energy recovery utilizes, and is called as energy and recovers.The method that energy recovers not only can be so that crucial MOSFET field effect transistor Q1 and Q2 working near under the soft switch condition, and can save most of displacement current institute's power consumed on circuit that is caused by metal mesh plate type plasma display panel capacitor C p.

The control flow that basic driver waveform WP3 takes place is as follows: before T1, field effect transistor Q4 among the MOSFET, Q6, Q8 are in and open conducting state, all the other all MOSFET are in and close cut-off state, the ground of the reference of all scanning drive chip IC1 at this moment end XVSS and power end XVDD voltage maintenance supply voltage VNS (can select voltage range-100V according to driving needs---250V), all scanning drive chip IC1 are output as VNS; Enter T1 period, at first close Q4, open Q1 then, energy recovery circuit 1 charges to Cp by current direction path GND-Q1-D1-L1-Q6-XVSS-Cp, when T1 finished, scanning drive chip IC1 output end voltage can (can be selected voltage range 100V-250V according to driving needs, generally get the VPS voltage swing and equate with VNS near VPS very much, polarity is opposite), the time span of T1 is mainly determined by the size of L1 and Cp; Enter T2 period, close Q1, open field effect transistor Q3, VPS provides VPS power supply by VPS-Q3-Q6-XVSS-Cp to Cp, in order to providing metal mesh plate type plasma display panel internal element discharge required energy, the time span of T2 can and be kept frequency requirement and select flexibly according to the concrete condition of metal mesh plate type plasma display panel; Enter T3 period, close Q3, open effect pipe Q2 then, Cp is last to be discharged by current direction path Cp-XVSS-Q6-L1-D2-Q2-GND conversely by the charge period energy of gained of original T1, with energy recovery, when T3 finished, scanning drive chip IC1 output end voltage can be very near VNS, the time span of T3 is determined by the size of L1 and Cp that mainly general size is got with T1 and equated substantially; Enter T4 period, close Q2, open Q4, VNS provides VNS power supply by VNS-Q4-Q6-XVSS-Cp to Cp, in order to provide the discharge of metal mesh plate type plasma display panel internal element required energy, the time span of T4 can and be kept frequency requirement and select flexibly according to the concrete condition of metal mesh plate type plasma display panel, and general size is got with T2 and equated substantially.It is top that what set forth is the single detailed process that waveform takes place of keeping, when reality drives metal mesh plate type plasma display panel according to the pulse waveform of keeping of the some repetitions of actual conditions needs, these repetitions keep pulse waveform be top set forth single keep waveform repeat take place, in addition, drive different demands according to metal mesh plate type plasma display panel, need to select suitable T2 and the time span of T4, the pulse waveform of keeping that goes out different frequency is carried out waveform combination.

Data driving chip output GND makes data electrode ground connection, gated sweep chip for driving IC1 be output as with reference to ground in the time of the basic driver waveform of output WP1, i.e. output is XVSS.The control flow that basic driver waveform WP1 takes place is as follows: at first with before above-mentioned WP3 enters T1 and the control flow of T1 identical, drive waveforms rises to VPS by VNS, follow blackout effect pipe Q6, open effect pipe Q7, because the capacitor C 2 (capacitance can be selected 1nf) between effect pipe MOSFET Q7 grid series connection adjustable resistance VR2 (can select the 100K adjustable resistance) and effect pipe Q7 grid and the source electrode and the effect of resistance R 2 (the resistance value scope can be selected 1K-10K), export by the triangle ramp waveform of voltage VPS at the source electrode of effect pipe Q7 to voltage VSETUP (range of voltage values is at VPS-500V), the triangle ramp waveform is by the current pathway of Q7-XVSS-Cp, VPS shown in the WP1 district is to the triangular waveform of VSETUP in scan electrode output terminal generation Fig. 2, satisfy the requirement of the positive voltage forced resetting igniting of metal mesh plate type plasma display panel, the time span of whole triangle acclivity is decided by the characteristic of metal mesh plate type plasma display panel, by adjusting the size of VR2, can obtain the triangle ramp waveform of suitable slope then; Waveform reaches after the VSETUP, follow blackout effect pipe Q7, open effect pipe Q6, current path by Cp-XVSS-Q6-Q3-VPS is returned to VPS with waveform from voltage VSETUP, first then blackout effect pipe Q3, open effect pipe Q5 again, because the capacitor C 1 (capacitance can be selected 1nf) between MOSFET effect pipe Q5 grid series connection adjustable resistance VR1 (can select the 100K adjustable resistance) and effect pipe Q5 grid and the source electrode and the effect of resistance R 1 (the resistance value scope can be selected 1K-10K), drop to the triangle ramp waveform of voltage VNS by voltage VPS in the drain electrode output of effect pipe Q5, the triangle ramp waveform is by the current pathway of Cp-XVSS-Q6-Q5-VNS, VPS shown in the WP1 district is to the triangular waveform of VNS in scan electrode output terminal generation Fig. 2, satisfy of the wipe requirement of the positive voltage forced resetting igniting back of metal mesh plate type plasma display panel to metal mesh plate type plasma display panel, the time span on whole triangle decline slope is decided by the characteristic of metal mesh plate type plasma display panel, by adjusting the size of VR1, can obtain the triangle ramp waveform of suitable slope then.

Data driving chip IC2 and scanning drive chip IC1 all are in shift mode of operation in the time of the basic driver waveform of output WP2.The control flow that basic driver waveform WP2 takes place is as follows: at first when basic driver waveform WP1 done state takes place by as can be known drive waveforms be in the VNS current potential, open effect pipe Q4 earlier, follow blackout effect pipe Q5, Q8, open effect pipe Q9 then, at this time XVSS is in the VNS current potential, XVDD makes XVDD be in the VADD current potential by the current path of VADD-D7-R3-Q9-XVDD, in actual the driving, power taking presses the VADD size between GND and VNS, and concrete size is determined by the characteristic of metal mesh plate type plasma display panel and the voltage-resistent characteristic of scanning drive chip IC1.Interim when WP2, needs carry out the addressing igniting to a certain scan electrode when, by gated sweep chip for driving IC1 output respective scan electrode is XVSS, all the other scan electrodes are XVDD, when the scan electrode that needs the addressing igniting is output as XVSS, the output of control corresponding data chip for driving IC2 allows the respective addressed electrode be output as power supply VA, can finish the addressing igniting of respective pixel point on the metal mesh plate type plasma display panel like this, the pulsewidth width of addressing igniting is determined by the characteristic of metal mesh plate type plasma display panel that mainly scope is generally got 0.5 μ s-10 μ s.In whole WP2 period, can cooperate the VA addressing pulse on the addressing electrode by the aforesaid method of all scan electrodes is exported XVSS successively, finish operation to the addressing igniting of all pixels in the whole metal mesh plate type plasma display panel.When addressing finished, first blackout effect pipe Q9, Q4 opened effect pipe Q8 again.

Data driving chip output GND makes data electrode ground connection, gated sweep chip for driving be output as with reference to ground in the time of the basic driver waveform of output WP4, i.e. output is XVSS.The control flow that basic driver waveform WP4 takes place is identical period second half section with WP1.At first effect pipe Q3, Q6, the Q8 among the MOSFET is in and opens conducting state, all the other all MOSFET are in and close by state, at this moment all scanning drive chip IC1 are in the VPS current potential with reference to ground end XVSS, power end XVDD, and all scanning drive chip IC1 are output as VPS; Follow blackout effect pipe Q3, open effect pipe Q5 again, because the capacitor C 1 between MOSFET effect pipe Q5 grid series connection adjustable resistance VR1 and effect pipe Q5 grid and the source electrode and the effect of resistance R 1, drop to the triangle ramp waveform of voltage VNS by voltage VPS in the drain electrode output of effect pipe Q5, the triangle ramp waveform is by the current pathway of Cp-XVSS-Q6-Q5-VNS, VPS shown in the WP4 district is to the triangular waveform of VNS in scan electrode output terminal generation Fig. 2, satisfy the requirement of wiping of metal mesh plate type plasma display panel, the time span on whole triangle decline slope is decided by the characteristic of metal mesh plate type plasma display panel, and is identical with the time on the triangle decline slope in WP1 period second half section.

As mentioned above, driving required basic waveform WP1, WP2, WP3, the WP4 of metal mesh plate type plasma display panel can produce by effective control driving circuit disclosed in this invention, in actual the driving, take suitable array mode for above-mentioned basic waveform, repeat to take place the wave form of combinations thereof mode then, satisfy that metal mesh plate type plasma display panel is driven requirement.

Claims (4)

1, a kind of metal mesh plate type plasma display panel driving circuit device, it is characterized in that it is mainly by energy recovery module (1), keep module (2), wipe module (3), isolation module (4), reseting module (5) and addressed module (6) are formed, described energy recovery module (1), keep module (2), wipe module (3), isolation module (4), reseting module (5) and the required control input signals XERH of addressed module (6), XERL, XSUH, XSUL, XERA, XPAS, XRST, XADD and XSOT are provided by digital signal generator (7), control input signals XERH and XERL are the control input signals of energy recovery module, control input signals XSUH and XSUL keep the required control input signals of module, control input signals XERA wipes the required control input signals of module, control input signals XPAS is the required control input signals of isolation module, control input signals XRST is the required control input signals of reseting module, and control input signals XADD and XSOT are the required control input signals of addressed module; Energy recovery module (1) wherein, keep module (2), wipe module (3), reseting module (5) and the required power supply input signal VPS of addressed module (6), VNS, VSETUP and VADD are provided by D.C. regulated power supply (8), power supply input signal VPS and VNS are the required power supply input signals of energy recovery module, power supply input signal VPS and VNS keep the required power supply input signal of module, power supply input signal VNS wipes the required power supply input signal of module, power supply input signal VSETUP is the required power supply input signal of reseting module, and power supply input signal VADD is the required power supply input signal of addressed module; The output terminal of energy recovery module (1) and the output terminal of keeping module (2) and the output terminal of wiping module (3) link to each other with one road output terminal of isolation module (4) together, one road output terminal of another road output terminal of isolation module (4) and the output terminal of reseting module (5) and addressed module (6) links to each other with reference to ground input end XVSS with scanning drive chip IC1 together, and another road output terminal of addressed module (6) links to each other with the power input XVDD of scanning drive chip IC1; Described energy recovery module (1) is by field effect transistor Q1, field effect transistor Q2, diode D1, diode D2, diode D3, diode D4 and inductance L 1 are formed, energy recovery module (1) control input signals is drawn digital switch signal output part XERH and the XERL that connects digital signal generator (7) from the grid of field effect transistor Q1 and field effect transistor Q2, one road power input of energy recovery module (1) links to each other with the power supply output signal VPS of D.C. regulated power supply (8) by diode D3 output terminal, another road power input links to each other with the power supply output signal VNS of D.C. regulated power supply (8) by the input end of diode D4, and the output terminal of energy recovery module (1) is drawn to connect by an end of inductance L 1 and kept module (2); The described module (2) of keeping is made up of field effect transistor Q3 and field effect transistor Q4, keep module (2) control input signals and draw digital switch signal output part XSUH and the XSUL that connects digital signal generator (7) from the grid of field effect transistor Q3 and field effect transistor Q4, keeping the drain electrode of module (2) one road power inputs by field effect transistor Q3 links to each other with the power supply output signal VPS of D.C. regulated power supply (8), another road power input links to each other with the power supply output signal VNS of D.C. regulated power supply (8) by the source electrode of field effect transistor Q4, keep module (2) output and connect an end of the inductance L 1 the energy recovery module (1), connect simultaneously and wipe module (3) from the tie point of the drain electrode of the source electrode of field effect transistor Q3 and field effect transistor Q4; Described isolation module (4) is made up of field effect transistor Q6, isolation module (4) control input signals is drawn the digital switch signal output part XPAS that connects digital signal generator (7) by the grid of field effect transistor Q6, the source electrode of isolation module (4) one road output terminals by field effect transistor Q6 with wipe module (3) output terminal and link to each other, another road output terminal links to each other with reseting module (5) by the drain electrode of field effect transistor Q6.

2, metal mesh plate type plasma display panel driving circuit device according to claim 1, it is characterized in that the described module (3) of wiping is by diode D5, variable resistor VR1, capacitor C 1, resistance R 1 is formed with field effect transistor Q5, wipe module (3) control input signals is drawn the termination digital signal generator (7) of the variable resistor VR1 by being parallel with diode D5 from the grid of field effect transistor Q5 digital switch signal output part XERA, wipe the source electrode of module (3) power input by field effect transistor Q5 and link to each other, wipe module (3) output from the drain electrode tie point of resistance R 1 and field effect transistor Q5 also while and the output termination isolation module (4) of keeping module (2) with the power supply output signal VNS of D.C. regulated power supply (8).

3, metal mesh plate type plasma display panel driving circuit device according to claim 1, it is characterized in that described reseting module (5) is by diode D6, variable resistor VR2, capacitor C 2, resistance R 2 is formed with field effect transistor Q7, reseting module (5) control input signals is drawn the digital switch signal output part XRST of the termination digital signal generator (7) of the variable resistor VR2 by being parallel with diode D6 from the grid of field effect transistor Q7, reseting module (5) power input meets the power supply output signal VSETUP of D.C. regulated power supply (8) by resistance R 2 and the drain electrode tie point of field effect transistor Q7, reseting module (5) output from the source electrode of field effect transistor Q7 draw and simultaneously with another road output termination addressed module (6) of isolation module (4).

4, metal mesh plate type plasma display panel driving circuit device according to claim 1, it is characterized in that described addressed module (6) is by diode D7, resistance R 3, field effect transistor Q9, field effect transistor Q8 and capacitor C 3 are formed, addressed module (6) control input signals is respectively from field effect transistor Q9, the grid of field effect transistor Q8 is drawn the digital switch signal output part XADD that connects corresponding digital signal generator (7) respectively, XSOT, addressed module (6) power input is by the power supply output signal VADD of diode D7 input termination D.C. regulated power supply (8), one road output terminal of addressed module (6) is drawn the output terminal that connects reseting module (5) from the source electrode of field effect transistor Q8 and the tie point of capacitor C 3 one ends, meet the reference ground input end XVSS of scanning drive chip IC1 simultaneously, another road output terminal of addressed module (6) is drawn the power input XVDD that meets scanning drive chip IC1 from the source electrode of field effect transistor Q9 and drain electrode and capacitor C 3 other end tie points of field effect transistor Q8.

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