CN100492473C - Improved drive circuit for metal otter board type plasma display panel - Google Patents

Abstract

This invention discloses an improved driving circuit used in metal screen plate plasma display panels composed of a positive voltage energy resuming module, a positive voltage maintaining module, a forward restoration module, a negative voltage energy resuming module, a negative voltage maintaining module, a separation continuous flow module, a negative direction restoration module and an addressing module.

Description

Improved drive circuit for metal otter board type plasma display panel

Technical field

The present invention relates to a kind of metal mesh plate type plasma display panel, especially a kind of metal mesh plate type plasma display panel scan electrode driving circuit, specifically a kind of improved drive circuit for metal otter board type plasma display panel.

Background technology

At present, plasma display panel has advantages such as light, thin, that screen is big, the visual angle is wide, inertia is little equally as a concrete flat-panel display device, has vast potential for future development in the large screen display field.

A kind of subtend discharge type AC plasma of metal mesh plate type plasma display panel display panel of developing at present, it is compared with conventional surface discharge type AC plasma display panel, have manufacturing process simply, easier realization high resolving power and manufacturing cost and driving low cost and other advantages, have the stronger market competitiveness.Structurally compare just because of this metal mesh plate type plasma display panel and to have than big difference with conventional surface discharge type AC plasma display panel, therefore be badly in need of a kind of brand-new display panel driving circuit of design, drive requirement to satisfy metal mesh plate type plasma display panel, and satisfy high-performance and requirement cheaply, embody technical advance from the angle that drives, improve the market competitiveness.

Summary of the invention

The objective of the invention is to be badly in need of at metal mesh plate type plasma display panel the problem of high-performance, cost drive circuit, design a kind of simple in structurely, cost is low, the improved drive circuit for metal otter board type plasma display panel that is easy to realize.

Technical scheme of the present invention is:

A kind of improved drive circuit for metal otter board type plasma display panel, it is characterized in that it is by positive voltage energy recovery module 1, positive voltage is kept module 2, forward reseting module 3, negative voltage energy recovery module 4, negative voltage is kept module 5, isolate afterflow module 6, negative sense reseting module 7, addressed module 8 is formed, the drive input signal XEPH that they are required, XEPL, XSPH, XPRH, XPRL, XENH, XENL, XSNL, XSWP, XSWN, XVG1, XVG2, XAD1 and XAD2 are provided by digital controlled signal generator 10, wherein positive voltage is kept module 2, forward reseting module 3, negative voltage is kept module 5, the high-voltage signal VPS that negative sense reseting module 7 and addressed module 8 are required, VPP, VNS, VNG, VNA is provided by dc high-voltage source module 9, the output terminal of forward reseting module 3 links to each other with the signal input part that positive voltage is kept module 2, the output terminal that positive voltage is kept module 2 links to each other with the input end of isolating afterflow module 6 with the output terminal of positive voltage energy recovery module 1, the output terminal of negative voltage energy recovery module 4 links to each other with the output terminal that negative voltage is kept module 5, negative voltage is kept another input end of the output termination isolation afterflow module 6 of module 5, an output terminal of isolating afterflow module 6 directly links to each other with an input end of addressed module 8, another output terminal of isolating afterflow module 6 links to each other with another input end of addressed module 8 by negative sense reseting module 7, the output of addressed module 8 links to each other with the corresponding input end of scanning drive chip IC1, and the output of the scanning drive chip IC1 scanning corresponding with metal mesh plate type plasma display panel is kept electrode and linked to each other.

Described positive voltage energy recovery module 1 is made up of capacitor C 1, field effect transistor Q1, field effect transistor Q2, diode D1, diode D2 and inductance L 1, the input of positive voltage energy recovery module 1 is drawn digital switch signal output part XEPH and the XEPL that connects digital controlled signal generator 10 from the grid of field effect transistor Q1 and field effect transistor Q2, and the output of positive voltage energy recovery module 1 is drawn by an end of inductance L 1 and connect positive voltage and keep module 2.

Described positive voltage is kept module 2 by diode D3, D12, field effect transistor Q3 forms, the input that positive voltage is kept module 2 is drawn the digital switch signal output part XSPH that connects digital controlled signal generator 10 from the grid of field effect transistor Q3, the output that positive voltage is kept module 2 connects an end of the inductance L 1 the positive voltage energy recovery module 1 from the tie point of the positive pole of the source electrode of field effect transistor Q3 and diode D12, connect simultaneously and isolate afterflow module 6, the power supply exit that positive voltage is kept module 2 is drawn from the drain electrode of field effect transistor Q3 and is connect forward reseting module 3, and the input end that positive voltage is kept the high-voltage signal VPS of module 2 is drawn from the positive pole of diode D3 and connect dc high-voltage source module 9 corresponding output terminals.

Described forward reseting module 3 is made up of capacitor C 3, field effect transistor Q5, field effect transistor Q6 and variable resistor VR1, the input of forward reseting module 3 is drawn by the grid of variable resistor VR1 and field effect transistor Q6 from the grid of field effect transistor Q5 and is drawn digital switch signal output part XPRH, the XPRL that connects corresponding digital controlled signal generator 10 respectively, and the output of forward reseting module 3 is drawn from an end of capacitor C 3 and connect positive voltage to keep the power supply exit of module 2 be the drain electrode of field effect pipe Q3; The input end of the high-voltage signal VPP of forward reseting module 3 is drawn the corresponding output terminal that connects dc high-voltage source module 9 from the drain electrode of field effect transistor Q5.

Described negative voltage energy recovery module 4 is made up of capacitor C 2, field effect transistor Q11, field effect transistor Q12, diode D6, diode D7 and inductance L 2, the input of negative voltage energy recovery module 4 is drawn digital switch signal output part XENH and the XENL end that connects digital controlled signal generator 10 by the grid of field effect transistor Q11, Q12, and the output of negative voltage energy recovery module 4 is kept module 5 by an end of inductance L 2 with negative voltage and linked to each other.

Described negative voltage is kept module 5 and is made up of field effect transistor Q14 and diode D10, D11, negative voltage is kept the input of module 5 and is drawn the digital switch signal end XSNL that connects digital controlled signal generator 10 from the grid of field effect transistor Q14, and the output that negative voltage is kept module 5 is drawn the inductance L 2 that connects the negative voltage energy recovery module 4 and isolated afterflow module 6 from the tie point of the positive pole of the drain electrode of field effect transistor Q14 and diode D11; Negative voltage is kept the input end of the high-voltage signal VNS of module 5 and is drawn the corresponding output terminal that connects dc high-voltage source module 9 from the negative pole of diode D10.

Described isolation afterflow module 6 is by field effect transistor Q8, field effect transistor Q15, diode D4 and diode D5 form, the input of isolating afterflow module 6 is respectively from field effect transistor Q8, the grid of Q15 is drawn the digital switch signal output part XSWP that connects corresponding digital controlled signal generator 10 respectively, XSWL, the output of isolating afterflow module 6 is drawn a end that the output that connects positive voltage energy recovery module 1 respectively is L1 and the output of negative voltage energy recovery module 4 is the end of L2 from the source electrode of the drain electrode of field effect transistor Q8 and field effect transistor Q15, and another road output of isolating afterflow module 6 is drawn from the drain electrode of the source electrode of field effect transistor Q8 and field effect transistor Q15 and connect addressed module 8 and negative sense reseting module 7 respectively.

Described negative sense reset circuit 7 is made up of field effect transistor Q10 and variable resistor VR2, the input of negative sense reset circuit 7 meets the digital switch signal output part XVG1 of digital controlled signal generator 10 through variable resistor VR2 from the grid of field effect transistor Q10, the output of negative sense reset circuit 7 is drawn from the drain electrode of field effect transistor Q10 and is connect addressed module 8, and the high-voltage signal VNG of negative sense reset circuit 7 draws the corresponding output terminal that connects dc high-voltage source module 9 from the source electrode of field effect transistor Q10.

Described addressed module 8 is by field effect transistor Q9, field effect transistor Q16, field effect transistor Q17, diode D8 and diode D9 form, the input end of addressed module 8 is from field effect transistor Q9, Q16, the grid of Q17 is drawn the digital switch signal output part XVG2 that connects digital controlled signal generator 10, XAD1, XAD2, the output of addressed module 8 is from field effect transistor Q9, Q16, the corresponding input end of scanning drive chip IC1 is drawn in the drain electrode of Q17, the high-voltage signal input end VNA of addressed module 8, VNG draws the corresponding output terminal that connects dc high-voltage source module 9 from field effect transistor Q16 with the tie point of the source electrode of field effect transistor Q17 and the source electrode of field effect transistor Q9 respectively.

The present invention has the following advantages:

Circuit of the present invention is compared with existing driving circuit, by replacing and reducing the circuit elements number of devices and reduce control, has reduced the cost of driving circuit.In specific implementation process, only need type and number by the crucial electronic devices and components of choose reasonable, just can drive the metal mesh plate type plasma display panel of any resolution and screen size size, same driving circuit of the present invention also is applicable to other subtend discharge type AC plasma display panel.Circuit of the present invention produces the required basic driver waveform of metal mesh plate type plasma display panel except can be good at, and also has following two outstanding features:

(1) by changing circuit structure, takes the multiplexing functions mode, simplified design, reduced design difficulty;

(2) circuit reduction has reduced circuit devcie, has reduced circuit cost.It is by the simplified design to positive voltage holding circuit module and negative voltage holding circuit module, change the MOSFET circuit module of original multichannel (generally needing 4 tunnel) into single diode structure, reduced control, not only simplified design, and reduced circuit cost, make the circuit cost of keeping the high-power driving part approximately reduce to original half.

Description of drawings

Fig. 1 is the display driving system structural representation of metal otter board plasma display panel involved in the present invention.

Fig. 2 is the needed basic driver waveform of a metal otter board plasma display panel synoptic diagram involved in the present invention.

Fig. 3 is a metal otter board plasma display panel scan electrode driving circuit theory diagram of the present invention.

Fig. 4 is an electrical schematic diagram that matches with block diagram shown in Figure 3.

Fig. 5 utilizes driving circuit of the present invention to drive the phase of the keeping drive waveforms synoptic diagram that forms.

Embodiment

The present invention is further illustrated for following structure drawings and Examples.

Shown in Fig. 3,4.

A kind of improved drive circuit for metal otter board type plasma display panel, it is mainly by positive voltage energy recovery module 1, positive voltage is kept module 2, forward reseting module 3, negative voltage energy recovery module 4, negative voltage is kept module 5, isolate afterflow module 6, negative sense reseting module 7, addressed module 8 is formed, as shown in Figure 3, the drive input signal XEPH that they are required, XEPL, XSPH, XPRH, XPRL, XENH, XENL, XSNL, XSWP, XSWN, XVG1, XVG2, XAD1 and XAD2 are provided by digital controlled signal generator 10, wherein positive voltage is kept module 2, forward reseting module 3, negative voltage is kept module 5, the high-voltage signal VPS that negative sense reseting module 7 and addressed module 8 are required, VPP, VNS, VNG, VNA is provided by dc high-voltage source module 9, the output terminal of forward reseting module 3 links to each other with the signal input part that positive voltage is kept module 2, the output terminal that positive voltage is kept module 2 links to each other with the input end of isolating afterflow module 6 with the output terminal of positive voltage energy recovery module 1, the output terminal of negative voltage energy recovery module 4 links to each other with the input end that negative voltage is kept module 5, negative voltage is kept another input end of the output termination isolation afterflow module 6 of module 5, an output terminal of isolating afterflow module 6 directly links to each other with an input end of addressed module 8, another output terminal of isolating afterflow module 6 links to each other with another input end of addressed module 8 by negative sense reseting module 7, the input of addressed module 8 links to each other with the corresponding input end of scanning drive chip IC1, and the output of the scanning drive chip IC1 scanning corresponding with metal mesh plate type plasma display panel is kept electrode and linked to each other.

Driving circuit figure during concrete enforcement as shown in Figure 4.Wherein: positive voltage energy recovery module 1 is made up of capacitor C 1, field effect transistor Q1, field effect transistor Q2, diode D1, diode D2 and inductance L 1, the input of positive voltage energy recovery module 1 is drawn digital switch signal output part XEPH and the XEPL that connects digital controlled signal generator 10 (using the programming of FPGA circuit board to promote chip such as IR2113S forms) from the grid of field effect transistor Q1 and field effect transistor Q2, and its output is drawn by an end of inductance L 1 and connect positive voltage and keep module 2.Positive voltage is kept module 2 by diode D3, D12, field effect transistor Q3 forms, the input that positive voltage is kept module 2 is drawn the digital switch signal output part XSPH that connects digital controlled signal generator 10 from the grid of field effect transistor Q3, it exports an end that connects the inductance L 1 the positive voltage energy recovery module 1 from the tie point of the positive pole of the source electrode of field effect transistor Q3 and diode D12, connect simultaneously and isolate afterflow module 6, the power supply exit that positive voltage is kept module 2 is drawn from the drain electrode of field effect transistor Q3 and is connect forward reseting module 3, and the input end of its high-voltage signal VPS is drawn from the positive pole of diode D3 and connect dc high-voltage source module 9 corresponding output terminals.Forward reseting module 3 is made up of capacitor C 3, field effect transistor Q5, field effect transistor Q6 and variable resistor VR1, its input is drawn by the grid of variable resistor VR1 and field effect transistor Q6 from the grid of field effect transistor Q5 and is drawn digital switch signal output part XPRH, the XPRL that connects corresponding digital controlled signal generator 10 respectively, and its output is drawn from an end of capacitor C 3 and connect positive voltage to keep the power supply exit of module 2 be the drain electrode of field effect pipe Q3; The input end of the high-voltage signal VPP of forward reseting module 3 is drawn the corresponding output terminal that connects dc high-voltage source module 9 from the drain electrode of field effect transistor Q5.Negative voltage energy recovery module 4 is made up of capacitor C 2, field effect transistor Q11, field effect transistor Q12, diode D6, diode D7 and inductance L 2, its input is drawn digital switch signal output part XENH and the XENL end that connects digital controlled signal generator 10 by the grid of field effect transistor Q11, Q12, and its output is kept module 5 by an end of inductance L 2 with negative voltage and linked to each other.Negative voltage is kept module 5 and is made of its input field effect transistor Q14 and diode D10, D11 and draws the digital switch signal end XSNL that connects digital controlled signal generator 10 from the grid of field effect transistor Q14, and its output is drawn the inductance L 2 that connects the negative voltage energy recovery module 4 and isolated afterflow module 6 from the tie point of the positive pole of the drain electrode of field effect transistor Q14 and diode D11; Negative voltage is kept the input end of the high-voltage signal VNS of module 5 and is drawn the corresponding output terminal that connects dc high-voltage source module 9 from the negative pole of diode D10.Isolate afterflow module 6 by field effect transistor Q8, field effect transistor Q15, diode D4 and diode D5 form, its input is respectively from field effect transistor Q8, the grid of Q15 is drawn the digital switch signal output part XSWP that connects corresponding digital controlled signal generator 10 respectively, XSWL, its output is drawn a end that the output that connects positive voltage energy recovery module 1 respectively is L1 and the output of negative voltage energy recovery module 4 is the end of L2 from the source electrode of the drain electrode of field effect transistor Q8 and field effect transistor Q15, and its another road output is drawn from the drain electrode of the source electrode of field effect transistor Q8 and field effect transistor Q15 and connect addressed module 8 and negative sense reseting module 7 respectively.Negative sense reset circuit 7 is made up of field effect transistor Q10 and variable resistor VR2.Its input meets the digital switch signal output part XVG1 of digital controlled signal generator 10 through variable resistor VR2 from the grid of field effect transistor Q10, its output is drawn from the source electrode of field effect transistor Q10 and is connect addressed module 8, and the high-voltage signal VNG of negative sense reset circuit 7 draws the corresponding output terminal that connects dc high-voltage source module 9 from the source electrode of field effect transistor Q10.Addressed module 8 is made up of field effect transistor Q9, field effect transistor Q16, field effect transistor Q17, diode D8 and diode D9, its input end is drawn digital switch signal output part XVG2, XAD1, the XAD2 that connects digital controlled signal generator 10 from the grid of field effect transistor Q9, Q16, Q17, the corresponding input end that its output is drawn scanning drive chip IC1 from the drain electrode of field effect transistor Q9, Q16, Q17; High-voltage signal input end VNA, the VNG of addressed module 8 draws the corresponding output terminal that connects dc high-voltage source module 9 from field effect transistor Q16 with the tie point of the source electrode of field effect transistor Q17 and the source electrode of field effect transistor Q9 respectively.

Details are as follows:

The drive system block diagram of driving metal mesh plate type plasma display panel of the present invention as shown in Figure 1, a series of metal electrodes have been drawn on the metal mesh plate type plasma display panel, be divided into two classes according to the function difference: electrode is kept in data electrode and scanning, and the number of two class electrodes is relevant with the resolution of metal mesh plate type plasma display panel.When metal mesh plate type plasma display panel is implemented to drive, data driving chip, scanning drive chip need be linked to each other with scan electrode with corresponding data electrode, the metal mesh plate type plasma display panel driving circuit reaches the purpose that drives metal mesh plate type plasma display panel by scanning drive chip power end (XVDD) being provided to scanning drive chip and providing metal mesh plate type plasma display panel required basic driver waveform with reference to ground end (XVSS).Effectively drive the required basic driver waveform of metal mesh plate type plasma display panel as shown in Figure 2, needs according to the metal mesh plate type plasma display panel displaying principle, needed drive waveforms is mainly by four part (WP1 shown in Figure 2 when driving metal mesh plate type plasma display panel, WP2, WP3, WP4) carry out reasonable combination and form, according to waveform individual features and function, the WP1 waveform is called as reset wave, its duration can be 300us-500us, the WP2 waveform is called as addressing waveforms, its duration can be 500us-2ms, the WP3 waveform is called as keeps waveform, its duration can be 5us-5ms, the WP4 waveform is called as wipes waveform, and its duration can be 20us-300us.The scheme block diagram of a kind of modified metal mesh plate type plasma display panel driving circuit of the technical program invention as shown in Figure 3, can finely must produce scanning and keep the needed above-mentioned tetrameric basic driver waveform of electrode, and bigger load current is provided, satisfy the requirement of system drive.The driving circuit schematic diagram as shown in Figure 4, it is the specific embodiments of Fig. 3 block diagram, in the driving circuit scheme mainly by a series of metal oxide semiconductor field effect pipes (MOSFET), the fast diode that recovers, electric capacity and inductance are formed, wherein IC1 represents scanning drive chip (such as the STV7617 chip of ST company), require the more scanning drive chip of needs according to resolution in the actual metal web plate type plasma display panel display system, here only provide a block diagram to do the explanation of scheme principle, metal mesh plate type plasma display panel can be regarded a capacitive load as in actual driving process, here represented with Cp, IC2 represents data chip (such as the STV7630 chip of ST company), in the actual metal web plate type plasma display panel display system according to resolution require the more data driving chip of needs, also only provide a block diagram to do the explanation of scheme principle here.The relevant details of other technologies scheme will be described below in the whole driving method detail operations flow process and are described simultaneously among Fig. 1, Fig. 2, Fig. 3, Fig. 4.

As shown in Figure 1, the output of scanning drive chip and metal mesh plate type plasma display panel scanning are kept electrode is corresponding one by one to be connected.The output of data driving chip is connected with data electrode is corresponding one by one, the power end VA of data driving chip connects D.C. regulated power supply, drive requirement according to metal mesh plate type plasma display panel and select the suitable voltage amplitude, directly with systematically link to each other with reference to ground; The power end XVDD of scanning drive chip all is connected with the metal mesh plate type plasma display panel driving circuit with reference ground end XVSS.Shown in Figure 2 is to drive the required basic driver waveform of metal mesh plate type plasma display panel, above-mentioned basic driver waveform is kept electrode output by data electrode and scanning, the data electrode output waveform can directly be produced by data driving chip, do not need driving circuit, scanning is kept the waveform of electrode output and is exported by the scanning drive chip output terminal, but need the metal mesh plate type plasma display panel driving circuit in the present design to be connected with scanning drive chip, provide required drive waveforms by the metal mesh plate type plasma display panel driving circuit, sign VPS among Fig. 2, VNS, VPP, VNG, VNA, VA all be with Fig. 4 in the DC high-voltage power supply that provided mutually one to one voltage indicate, concrete voltage magnitude is driven by metal mesh plate type plasma display panel and requires decision.

Fig. 3 is the metal mesh plate type plasma display panel driving circuit block diagram of inventing in order to produce four kinds of basic driver waveforms shown in Figure 2, and this driving circuit scheme is divided by function and can be divided into positive voltage energy recovery module, positive voltage and keep module, forward reseting module, negative voltage energy recovery module, negative voltage and keep module, isolate afterflow module, negative sense reseting module, addressed module, dc high-voltage source module and digital controlled signal generator.Positive voltage energy recovery module and positive voltage are kept the module co-ordination, on function, produce the needed positive voltage of driving display panel and keep pulse (high level pulse of WP3 among Fig. 2), and effective load current is provided, and reduce the loss of idle current on circuit; Same negative voltage energy recovery module and negative voltage are kept the module co-ordination, produce the needed negative voltage of driving display panel and keep pulse (low level pulse of WP3 among Fig. 2); Forward reseting module and negative sense reseting module are worked alone or synergistically, produce the needed negative sense of driving display screen and wipe waveform (WP4 among Fig. 2) or reset wave (WP1 among Fig. 2); Addressed module produces and drives the needed addressing waveforms of display screen (WP2 among Fig. 2); Isolate the afterflow module and mainly play the effect of isolating the generating positive and negative voltage circuit and being connected circuit module.

In conjunction with the concrete driving circuit schematic diagram of Fig. 4, the positive voltage energy recovery module is made up of C1, Q1, Q2, D1, D2 and L1, positive voltage is kept module and is made up of D3, Q3 and D12, the forward reseting module is made up of C3, Q5, Q6 and VR1, the negative voltage energy recovery module is made up of C2, Q11, Q12, D6, D7 and L2, negative voltage is kept module and is made up of D11, Q14 and D10, isolating the afterflow module is made up of Q8, Q15, D4 and D5, the negative sense reset circuit is made up of Q10 and VR2, and addressed module is made up of Q9, Q16, Q17, D8 and D9; Above-mentioned positive voltage energy recovery module is kept module one output terminal (being the source electrode and diode D12 anode junction of MOSFET Q3) by the end output of inductance L 1 with positive voltage and is isolated afterflow module one output terminal (being Q8 drain electrode and D4 negative electrode junction) and links to each other, the forward reseting module is kept another output terminal of module (being the drain electrode and D3 negative electrode junction of Q3) by an end of capacitor C 3 with positive voltage and is linked to each other, the end output of negative voltage energy recovery module by inductance L 2 and negative voltage are kept module output (being the drain electrode of Q14 and the anode junction of D11) and isolation afterflow module one output terminal (being the Q15 source electrode and the anode junction of D5) and are linked to each other, negative sense reseting module output terminal (being the drain electrode of Q10) and an output terminal of isolating the afterflow module (being Q15 drain electrode and D4 anode junction), part addressed module circuit is (by D8, D9, Q16, the Q17 composition) output terminal (being D8 negative electrode and D9 anode junction) interconnects and the power input (being XVDD) of scanning drive chip links to each other, and the output terminal of remaining addressed module circuit (Q9) (being the Q9 drain electrode) links to each other with the reference ground input end (being XVSS) of output terminal (being Q8 source electrode and D5 negative electrode junction) of isolating the afterflow module and scanning drive chip.

Connection between the above-mentioned mentioned module all is the connection of the output terminal of module, these 14 control signals of XEPH, XEPL, XSPH, XPRH, XPRL, XSWP, XENH, XENL, XSNL, XSWN, XVG1, XVG2, XAD1 and XAD2 that the input end of each module is among Fig. 4 to be marked, these control signals are produced by the digital controlled signal generator, link to each other VPS, VPP, VNS, VNG, these 5 groups of high pressure of VNA that the dc high-voltage source module provides among Fig. 4 to be marked one by one with other circuit modules by digital signal generator output.

Carry out the technical scheme operating process describe before by 2 explanations: the one, the voltage VGC1 size that connects for an end of capacitor C shown in Figure 41 can have two kinds of selections, VGC1 can equal VPS, also can equal system earth GND, the operating process that two kinds of selections bring is difference to some extent, but principle of work is identical with the effect of generation, here select VGC1 to equal GND for the purpose of convenient, the same voltage VGC2 size that connects for an end of capacitor C shown in Figure 42 can have two kinds of selections, VGC2 can equal VNS, also can equal system earth GND, the operating process that two kinds of selections bring is difference to some extent, but principle of work is identical with the effect of generation, selects VGC2 to equal GND for the purpose of making things convenient for here; The 2nd, in the circuit steady operation shown in Fig. 4, the voltage swing that can measure the other end VCC1 of capacitor C 1 equals VPS/2, and the voltage swing of the other end VCC2 of capacitor C 2 equals VNS/2.

By controlling metal mesh plate type plasma display panel driving circuit shown in Figure 4, can produce the needed basic driver waveform of driving metal mesh plate type plasma display panel shown in Figure 2, will describe in detail respectively by effective control metal mesh plate type plasma display panel driving circuit shown in Figure 4 according to four kinds of basic driver waveform situations below and produce the needed four kinds of basic driver waveforms of driving metal mesh plate type plasma display panel shown in Figure 2.

Because the control flow when producing basic driver waveform WP1, WP2, WP4 needs the part control flow of basic driver waveform WP3, so at first describe the control flow that produces waveform WP3.Fig. 5 is the basic waveform enlarged drawing of WP3, T1, T2, T3, T4, T5, T6, T7, T8 are corresponding time period of waveform (can be respectively 400ns, 2us, 400ns, 400ns, 400ns, 2us, 400ns, 400ns), and data driving chip output GND makes data electrode ground connection in the time of the basic driver waveform of output WP3.Whole control process is the process that an energy recovery utilizes, and is called as energy and recovers.The method that energy recovers not only can be so that crucial MOSFET Q3, Q8, Q14, Q15 working near under the soft switch condition, and can save most of displacement current institute's power consumed on circuit that is caused by metal mesh plate type plasma display panel capacitor C p.

The control flow that basic driver waveform WP3 takes place is as follows: before T1, Q8 among the MOSFET, Q15 are in and open conducting state, all the other all MOSFET are in and close by state, at this moment all scanning drive chips pass through diode D11 and the effect of D12 voltage clamp with reference to ground end XVSS, power end XVDD, voltage keeps system earth GND substantially, and all scanning drive chips are output as GND; Enter T1 period, at first close Q8, Q15, open Q1 then, the energy of storage charges to Cp by current direction path C1-Q1-D1-L1-Q8-XVSS-Cp on the capacitor C 1, when T1 finishes, scanning chip output voltage can be very near VPS, and the time span of T1 is mainly determined by the size of L1 and Cp; Enter T2 period, close Q1, open Q3, VPS provides VPS power supply by VPS-D3-Q3-Q8-XVSS-Cp to Cp, in order to providing metal mesh plate type plasma display panel internal element discharge required energy, the time span of T2 can and be kept frequency requirement and select flexibly according to the concrete condition of metal mesh plate type plasma display panel; Enter T3 period, close Q3, open Q2 then, Cp is last to be discharged by current direction path Cp-XVDD-D4-L1-D2-Q2-C1 conversely by the charge period energy of gained of original T1, in C1, when T3 finished, scanning chip output voltage can be very near GND with energy recovery, the time span of T3 is determined by the size of L1 and Cp that mainly general size is got with T1 and equated substantially; Enter T4 period, close Q2, Q8, open Q15 then, the power end XVDD of scanning drive chip links to each other with GND with D11 by the scanning drive chip parasitic diode by diode D11, reference ground end XVSS, make scanning chip output remain GND, the time size in T4 period can be chosen arbitrarily according to the needs of keeping frequency; Enter T5 period, open Q12, there are the voltage of VNS/2 in screen capacitor C p and storage capacitor C2, and Cp charges to C2 by current direction path Cp-XVDD-Q15-L2-D7-Q12-C2, with energy recovery in C2, when T5 finishes, scanning chip output voltage can be very near VNS, and the time span of T5 is mainly determined by the size of L2 and Cp, generally allows circuit working in symmetry status when the design physical circuit, get L2 and equal L1, the T5 size equates substantially with T1, T3 like this; Enter T6 period, close Q12, open Q14, power supply VNS provides VNS power supply by VNS-D10-Q14-Q15-XVDD-Cp to Cp, in order to provide the discharge of metal mesh plate type plasma display panel internal element required energy, this moment is because the effect of diode D5 and scanning drive chip endophyte diode, XVSS also remains VNS, the time span of T6 can and be kept frequency requirement and select flexibly according to the concrete condition of metal mesh plate type plasma display panel, considers that here the symmetry of drive waveforms generally equals T2 to taking by weighing T6; Enter T7 period, at first close Q14, open Q11 then, the energy of storage charges to Cp by current direction path C2-Q11-D6-L2-D5-XVSS-Cp on the capacitor C 2, when T7 finishes, scanning chip output voltage can be very near GND, and the time span of T7 is determined by the size of L2 and Cp that mainly the time that same symmetry is chosen T7 equates substantially with T5 here; Enter T8 period, close Q11, Q15, open Q8 then, the power end XVDD of scanning drive chip links to each other with GND by D12 with D12, reference ground end XVSS by diode D4, make the output of scanning chip remain GND, the time size in T8 period can be chosen arbitrarily according to the needs of keeping frequency, and symmetry is chosen T8 and equaled T4 here.It is top that what set forth is the single detailed process that waveform takes place of keeping, when reality drives metal mesh plate type plasma display panel according to the pulse waveform of keeping of the some repetitions of actual conditions needs, to keep waveform a situation arises be identical with top set forth single in the generation of keeping pulse waveform of these repetitions, in addition, drive different demands according to metal mesh plate type plasma display panel, need to select suitable T2, T4, the time span of T6, T8, the pulse waveform of keeping that goes out different frequency is carried out waveform combination.

The control flow that basic driver waveform WP1 takes place is as follows: at first with before above-mentioned WP3 enters T1. and the control flow of T1 identical, drive waveforms rises to VPS by GND, then close Q6, open Q5, because the effect of MOSFET Q5 grid series connection adjustable resistance VR1, export by GND to vpp voltage triangle ramp waveform at the source electrode of Q5, the triangle ramp waveform is by the effect of C3 capacitive coupling, on VPS voltage, superpose, current pathway by C3-Q3-Q8-XVSS-Cp, VPS shown in the WP1 district is to the stack triangular waveform of VPS+VPP in scan electrode output terminal generation Fig. 2, satisfy the requirement of the positive voltage forced resetting igniting of metal mesh plate type plasma display panel, the time span of whole triangle acclivity is decided by the characteristic of metal mesh plate type plasma display panel, by adjusting the size of VR1, can obtain the triangle ramp waveform of suitable slope then; Waveform reaches after the VPS+VPP, then close Q5, open Q6, by the effect of C3 capacitive coupling output waveform is returned to VPS from VPS+VPP, close Q8 then earlier, Q3, open Q15 again, Q10, scan electrode output terminal drive waveforms drops to VNG in triangle ramp waveform mode by VPS along Cp-XVDD-Q10-VNG, the order of magnitude of voltage VNG can be selected arbitrarily to adjust, get VNG and equal VNS in Fig. 2, the time span on the triangle slope of decline is by the decision of the characteristic of metal mesh plate type plasma display panel, the value of the grid adjustable resistance VR2 by adjusting Q10, can change waveform slope, satisfy driving requirement.

The control flow that basic driver waveform WP2 takes place is as follows: at first when basic driver waveform WP1 done state takes place by as can be known drive waveforms be in the VNG current potential, open Q9 earlier, close Q15, Q10, open Q16 then, Q17, at this time XVSS is in the VNG current potential, XVDD is in the VNA current potential, in actual the driving, the VNA order of magnitude is less than VNG, the difference of the order of magnitude of VNG and VNA is determined by the characteristic of metal mesh plate type plasma display panel and the voltage-resistent characteristic of scanning chip, when deciding, VNG can select suitable VNA like this, interim when WP2, needs carry out the addressing igniting to a certain scan electrode when, by gated sweep chip output respective scan electrode is XVSS, all the other scan electrodes are XVDD, when the scan electrode that needs the addressing igniting is output as XVSS, the output of control respective addressed chip allows the respective addressed electrode be output as power supply VA, can finish the addressing igniting of respective pixel point on the metal mesh plate type plasma display panel like this, the pulsewidth width of addressing igniting is mainly determined by the characteristic of metal mesh plate type plasma display panel.In whole WP2 period, can cooperate the VA addressing pulse on the addressing electrode by the aforesaid method of all scan electrodes is exported XVSS successively, finish operation to the addressing igniting of all pixels in the whole metal mesh plate type plasma display panel.When addressing finishes, close Q9 earlier, open Q15 again, right XVSS equals XVDD and equals VNA, then closes Q16, Q17; Control method is opened Q11 with the T7 period among the WP3 then, and the energy of storage charges to Cp by current direction path C2-Q11-D6-L2-D5-XVSS-Cp on the capacitor C 2, is spending the T7 time period, and scanning chip output voltage can be very near GND; Control flow fully and the control method of the T8 time period among the WP3 makes scan electrode be output as GND among the last WP2.

Control flow and WP1 that basic driver waveform WP4 takes place are similar period second half section.At first the Q8 among the MOSFET, Q15 are in and open conducting state, all the other all MOSFET are in and close by state, at this moment all scanning drive chips link to each other with system earth GND by diode with reference to ground end XVSS, power end XVDD, and all scanning drive chips are output as GND; Then close Q8, open Q10, scan electrode output terminal drive waveforms drops to VNG in triangle ramp waveform mode by GND along Cp-XVDD-Q10-VNG; Waveform is returned to the control procedure of GND by VNG, at first closes Q10, and the T7 among ensuing control flow and the WP3, T8 are identical period.

As mentioned above, driving required basic waveform WP1, WP2, WP3, the WP4 of metal mesh plate type plasma display panel can produce by effective control Driver Circuit, in actual the driving, take suitable array mode for above-mentioned basic waveform, repeat to take place the wave form of combinations thereof mode then, satisfy that metal mesh plate type plasma display panel is driven requirement.

The used digital controlled signal generator of the digital controlled signal generator 10 that the present invention is used to produce 14 control signal XEPH, XEPL, XSPH, XPRH, XPRL, XENH, XENL, XSNL, XSWP, XSWN, XVG1, XVG2, XAD1 and XAD2 and existing flat panel TV is identical, and is also same as the prior art in order to the dc high-voltage source module 9 that produces 5 high-voltage signal VPS, VPP, VNS, VNG, VNA.

Claims (9)

1, a kind of improved drive circuit for metal otter board type plasma display panel, it is characterized in that it is by positive voltage energy recovery module (1), positive voltage is kept module (2), forward reseting module (3), negative voltage energy recovery module (4), negative voltage is kept module (5), isolate afterflow module (6), negative sense reseting module (7), addressed module (8) is formed, the drive input signal XEPH that they are required, XEPL, XSPH, XPRH, XPRL, XENH, XENL, XSNL, XSWP, XSWN, XVG1, XVG2, XAD1 and XAD2 are provided by digital controlled signal generator (10), wherein positive voltage is kept module (2), forward reseting module (3), negative voltage is kept module (5), negative sense reseting module (7) and the required high-voltage signal VPS of addressed module (8), VPP, VNS, VNG, VNA is provided by dc high-voltage source module (9), the output terminal of forward reseting module (3) links to each other with the signal input part that positive voltage is kept module (2), the output terminal that positive voltage is kept module (2) links to each other with the input end of isolating afterflow module (6) with the output terminal of positive voltage energy recovery module (1), the output terminal of negative voltage energy recovery module (4) links to each other with the output terminal that negative voltage is kept module (5), negative voltage is kept another input end of the output termination isolation afterflow module (6) of module (5), an output terminal of isolating afterflow module (6) directly links to each other with an input end of addressed module (8), another output terminal of isolating afterflow module (6) links to each other with another input end of addressed module (8) by negative sense reseting module (7), the output of addressed module (8) links to each other with the corresponding input end of scanning drive chip IC1, and the output of the scanning drive chip IC1 scanning corresponding with metal mesh plate type plasma display panel is kept electrode and linked to each other.

2, improved drive circuit for metal otter board type plasma display panel according to claim 1, the described positive voltage energy recovery module of its feature (1) is by capacitor C 1, field effect transistor Q1, field effect transistor Q2, diode D1, diode D2 and inductance L 1 are formed, the input of positive voltage energy recovery module (1) is drawn digital switch signal output part XEPH and the XEPL that connects digital controlled signal generator (10) from the grid of field effect transistor Q1 and field effect transistor Q2, and the output of positive voltage energy recovery module (1) is drawn by an end of inductance L 1 and connect positive voltage and keep module (2).

3, improved drive circuit for metal otter board type plasma display panel according to claim 1, the described positive voltage of its feature is kept module (2) by diode D3, D12, field effect transistor Q3 forms, the input that positive voltage is kept module (2) is drawn the digital switch signal output part XSPH that connects digital controlled signal generator (10) from the grid of field effect transistor Q3, the output that positive voltage is kept module (2) connects an end of the inductance L 1 the positive voltage energy recovery module (1) from the tie point of the positive pole of the source electrode of field effect transistor Q3 and diode D12, connect simultaneously and isolate afterflow module (6), the power supply exit that positive voltage is kept module (2) is drawn from the drain electrode of field effect transistor Q3 and is connect forward reseting module (3), and the input end that positive voltage is kept the high-voltage signal VPS of module (2) is drawn from the positive pole of diode D3 and connect the corresponding output terminal of dc high-voltage source module (9).

4, improved drive circuit for metal otter board type plasma display panel according to claim 1, it is characterized in that described forward reseting module (3) is by capacitor C 3, field effect transistor Q5, field effect transistor Q6 and variable resistor VR1 form, the input of forward reseting module (3) is drawn by the grid of variable resistor VR1 and field effect transistor Q6 from the grid of field effect transistor Q5 and is drawn the digital switch signal output part XPRH that connects corresponding digital controlled signal generator (10) respectively, XPRL, the output of forward reseting module (3) is drawn from an end of capacitor C 3 and is connect positive voltage to keep the power supply exit of module (2) be the drain electrode of field effect pipe Q3; The input end of the high-voltage signal VPP of forward reseting module (3) is drawn the corresponding output terminal that connects dc high-voltage source module (9) from the drain electrode of field effect transistor Q5.

5, improved drive circuit for metal otter board type plasma display panel according to claim 1, it is characterized in that described negative voltage energy recovery module (4) is by capacitor C 2, field effect transistor Q11, field effect transistor Q12, diode D6, diode D7 and inductance L 2 are formed, the input of negative voltage energy recovery module (4) is by field effect transistor Q11, the grid of Q12 is drawn digital switch signal output part XENH and the XENL end that connects digital controlled signal generator (10), and the output of negative voltage energy recovery module (4) is kept module (5) by an end of inductance L 2 with negative voltage and linked to each other.

6, improved drive circuit for metal otter board type plasma display panel according to claim 1, it is characterized in that described negative voltage keeps module (5) by field effect transistor Q14 and diode D10, D11 forms, negative voltage is kept the input of module (5) and is drawn the digital switch signal end XSNL that connects digital controlled signal generator (10) from the grid of field effect transistor Q14, and the output that negative voltage is kept module (5) is drawn the inductance L 2 that connects the negative voltage energy recovery module (4) and isolated afterflow module (6) from the tie point of the positive pole of the drain electrode of field effect transistor Q14 and diode D11; Negative voltage is kept the input end of the high-voltage signal VNS of module (5) and is drawn the corresponding output terminal that connects dc high-voltage source module (9) from the negative pole of diode D10.

7, improved drive circuit for metal otter board type plasma display panel according to claim 1, it is characterized in that described isolation afterflow module (6) is by field effect transistor Q8, field effect transistor Q15, diode D4 and diode D5 form, the input of isolating afterflow module (6) is respectively from field effect transistor Q8, the grid of Q15 is drawn the digital switch signal output part XSWP that connects corresponding digital controlled signal generator (10) respectively, XSWL, the output of isolating afterflow module (6) is drawn a end that the output that connects positive voltage energy recovery module (1) respectively is L1 and the output of negative voltage energy recovery module (4) is the end of L2 from the source electrode of the drain electrode of field effect transistor Q8 and field effect transistor Q15, and another road output of isolating afterflow module (6) is drawn from the drain electrode of the source electrode of field effect transistor Q8 and field effect transistor Q15 and connect addressed module (8) and negative sense reseting module (7) respectively.

8, improved drive circuit for metal otter board type plasma display panel according to claim 1, it is characterized in that described negative sense reset circuit (7) is made up of field effect transistor Q10 and variable resistor VR2, the input of negative sense reset circuit (7) meets the digital switch signal output part XVG1 of digital controlled signal generator (10) through variable resistor VR2 from the grid of field effect transistor Q10, the output of negative sense reset circuit (7) is drawn from the drain electrode of field effect transistor Q10 and is connect addressed module (8), and the high-voltage signal VNG of negative sense reset circuit (7) draws the corresponding output terminal that connects dc high-voltage source module (9) from the source electrode of field effect transistor Q10.

9, improved drive circuit for metal otter board type plasma display panel according to claim 1, it is characterized in that described addressed module (8) is by field effect transistor Q9, field effect transistor Q16, field effect transistor Q17, diode D8 and diode D9 form, the input end of addressed module (8) is from field effect transistor Q9, Q16, the grid of Q17 is drawn the digital switch signal output part XVG2 that connects digital controlled signal generator (10), XAD1, XAD2, the output of addressed module (8) is from field effect transistor Q9, Q16, the corresponding input end of scanning drive chip IC1 is drawn in the drain electrode of Q17, the high-voltage signal input end VNA of addressed module (8), VNG draws the corresponding output terminal that connects dc high-voltage source module (9) from field effect transistor Q16 with the tie point of the source electrode of field effect transistor Q17 and the source electrode of field effect transistor Q9 respectively.

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