CN201057548Y - Accurate measuring apparatus for time of burst event - Google Patents
Accurate measuring apparatus for time of burst event Download PDFInfo
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- CN201057548Y CN201057548Y CN 200720031895 CN200720031895U CN201057548Y CN 201057548 Y CN201057548 Y CN 201057548Y CN 200720031895 CN200720031895 CN 200720031895 CN 200720031895 U CN200720031895 U CN 200720031895U CN 201057548 Y CN201057548 Y CN 201057548Y
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Abstract
The utility model relates to a precision measuring device used during the period of emergency event, comprising a singlechip system, a frequency standard shaping circuit, a signal shaping circuit, a control circuit with an input end connected to the signal shaping circuit and an output end connected to the singlechip system, a frequency dividing circuit with an input end connected to the frequency standard shaping circuit and to the control circuit, and a data flip-latch with an input end connected to the frequency dividing circuit and an output end connected to the singlechip system. The utility model precisely defines time through a GPS receiver, time-code information and standard second emitted by an OEM board or produced by other time service systems, and synchronously adopts microsecond and millisecond counting units formed by a frequency source of high-stability crystal oscillator and the standard second, thus realizing the measurement of the beginning time and end time of external emergent event and the whole maintaining process of the event, with the measured precision reaching a millisecond. The utility model has the advantage of ration design, simple structure, small size, low production cost, stable and reliable working and precise measured time, and can be popularized and used in such departments as transportation and electricity power etc.
Description
Technical field
The utility model belongs to and has or the clock technology field of operating the device of arbitrary device after at interval at preselected time or preselected time is housed, the mechanism that makes the continuous running that the clock and watch moment and operation interrelate that is specifically related to only move in the moment of a preliminary election or adjustable time interval at one end.
Background technology
The accurate moment of measuring a certain accident generation is the indispensable parts of department such as traffic, electric power, continuous development along with science and technology, all trades and professions are had higher requirement to measuring equipment, measure accurately that moment that a certain accident takes place not only requires the initial moment of generation of the incident of measuring but also finish time of wanting measurement event.The accurate moment equipment that the measurement accident of using at present takes place mainly contains " P08812 electrical network with the synchronous clock of GPS ", this equipment can only measurement event the initial moment and the duration and the finish time that can't measurement event, want to fully understand the accident overall process and the accurate finish time, the P08812 electrical network can't be finished with the synchronous clock of GPS.
Summary of the invention
Technical problem to be solved in the utility model is to overcome the shortcoming of the accurate moment equipment that above-mentioned measurement accident takes place, provide a kind of reasonable in design, simple in structure, production cost is low, working stability is reliable, the accurate accident of Measuring Time device for accurately measuring constantly.
Solving the problems of the technologies described above the technical scheme that is adopted is that it comprises: the Single Chip Microcomputer (SCM) system that complete machine is controlled; 10MHZ frequency signal and standard second signal to input carry out the frequency marking shaping circuit that shaping is amplified; Accident moment signal to input carries out shaping amplifying signal shaping circuit; Control circuit, the input termination signal transformation circuit of this circuit, output terminal connects Single Chip Microcomputer (SCM) system; Frequency dividing circuit, the input termination frequency marking shaping circuit and the control circuit of this circuit; Data latches, the input termination frequency dividing circuit of this circuit, output terminal connect Single Chip Microcomputer (SCM) system.
Control circuit of the present utility model is: 2 pin of integrated circuit U10A and 9 pin of integrated circuit U10B connect the frequency marking shaping circuit, 14 pin of integrated circuit U10A connect an end of capacitor C 4,15 pin connect the other end of capacitor C 4 and connect the 5V positive source by resistance R 11,3 pin connect the 5V positive source, 13 pin connect integrated circuit U11A input end 1 pin, another termination 5V positive source of resistance R 11,6 pin of integrated circuit U10B connect an end of capacitor C 5,7 pin connect the other end of capacitor C 5 and connect the 5V positive source by resistance R 12,10 pin and 11 pin connect the 5V positive source, 5 pin connect integrated circuit U11A input end 2 pin, another termination 5V positive source of resistance R 12, output terminal 3 pin of integrated circuit U11A connect 2 pin of integrated circuit U12A, 3 pin of integrated circuit U12A connect frequency dividing circuit, 1 pin and 4 pin connect the 5V positive source, 5 pin connect 11 pin and the data latches of integrated circuit U12B, and 10 pin and 12 pin of integrated circuit U12B connect the 5V positive source, 8 pin and 13 pin connect Single Chip Microcomputer (SCM) system.
Frequency marking shaping circuit of the present utility model comprises frequency shaping circuit and second signal transformation circuit, the frequency signal of 10MHz is by the input end input of frequency shaping circuit, the standard second signal is by the input end input of signal transformation circuit second, the output termination frequency dividing circuit of frequency shaping circuit and second signal transformation circuit.
Time-code information and standard second that the utility model employing GPS receiver, OEM plate are sent or time-code and the standard second that adopts other time dissemination system to produce are determined precise time, and employing is that microsecond, millisecond meter counting unit and the standard second that frequency source is formed carried out synchronously with the high stability crystal oscillator, realize measuring beginning and the finish time and the lasting overall process of incident of outside accident, the Measuring Time precision reaches 1 microsecond.The utlity model has advantages such as reasonable in design, simple in structure, that volume is little, production cost is low, working stability is reliable, Measuring Time is accurate, can promote the use of in departments such as traffic, electric power.
Description of drawings
Fig. 1 is an electrical principle block scheme of the present utility model.
Fig. 2 is the electronic circuit schematic diagram of an embodiment of the utility model.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described, but the utility model is not limited to these embodiment.
Fig. 1 is an electrical principle block scheme of the present utility model, referring to Fig. 1.The utility model is to be connected and composed by frequency marking shaping circuit, frequency dividing circuit, data latches, signal transformation circuit, control circuit, Single Chip Microcomputer (SCM) system.The output termination frequency dividing circuit of frequency marking shaping circuit, the output terminal connection control circuit of signal transformation circuit, the output termination frequency dividing circuit and the Single Chip Microcomputer (SCM) system of control circuit, the output termination data latches of frequency dividing circuit, the output terminal of data latches connects Single Chip Microcomputer (SCM) system.The frequency signal of standard second (1PPS) 10MHz of GPS output obtains microsecond, millisecond and 1Hz signal by frequency marking shaping circuit, frequency dividing circuit, the zero clearing of frequency dividing circuit is to be finished by the burst pulse that shaping circuit produces by the pulse per second (PPS) of GPS (1PPS), thereby guarantees the synchronous of local microsecond, millisecond and 1Hz and standard time.The utility model is only exported information such as date Hour Minute Second at ordinary times.When outer step accident takes place, event signal send control circuit after eliminating interference by signal transformation circuit, produce data latching pulse and Single Chip Microcomputer (SCM) system interruption pulse, this computer-chronograph reads the initial moment and the finish time that incident produces, Single Chip Microcomputer (SCM) system is read in internal memory with this moment (being accurate to 1 microsecond), and with broadcast type the moment of incident is sent from serial ports.
In Fig. 2, the frequency marking shaping circuit of present embodiment is connected and composed by integrated circuit U13A, integrated circuit U14D, triode T1, triode T2, triode T4, diode D1, diode D4, resistance R 1～resistance R 5, resistance R 10, resistance R 14, resistance R 15, capacitor C 1, capacitor C 6, the model of integrated circuit U13A is 74HC221A, and the model of integrated circuit U14D is 74HCO4.The frequency signal of 10MHz is by the end input of capacitor C 1, the other end of capacitor C 1 connects the negative pole of the base stage of triode T1 and diode D1 and connects the 5V positive source by resistance R 2 by resistance R 1, the base stage of the collector connecting transistor T2 of triode T1 also connects the 5V positive source by resistance R 3, the collector of triode T2 connects frequency dividing circuit and connects the 5V positive source by resistance R 4, the emitter of the emitter of triode T1, triode T2, the positive pole of diode D1 energising resistance R5 ground connection.Triode T1, triode T2, diode D1, resistance R 1～resistance R 5, capacitor C 1 connect into the frequency shaping circuit.
The standard second signal is by the end input of resistance R 14, the base stage of another termination triode T4 of resistance R 14 and the negative pole of diode D4, the collector of triode T4 connects the input end of integrated circuit U14D and connects the 5V positive source by resistance R 15,2 pin of the output termination integrated circuit U13A of integrated circuit U14D, the grounded emitter of the positive pole of diode D4 and triode T4.14 pin of integrated circuit U13A connect an end of capacitor C 6, the other end that 15 pin connect capacitor C 6 and by resistance R 10 connect the 5V positive source, 13 pin connect frequency dividing circuit.Integrated circuit U13A, integrated circuit U14D, triode T4, diode D4, resistance R 10, resistance R 14, resistance R 15, capacitor C 6 connect and compose a second signal transformation circuit.
The signal transformation circuit of present embodiment is connected and composed by integrated circuit U14A, integrated circuit U14B, triode T3, diode D2, diode D3, resistance R 7, resistance R 8, resistance R 9, capacitor C 3, bit code switch SW-1, and the model of integrated circuit U14A and integrated circuit U14B is 74HCO4.Accident signal is constantly imported by the positive pole of the negative pole diode D3 of diode D2, the positive pole of diode D3 connects an end of the base stage of triode T3 and capacitor C 3 by resistance R 8 and connects an end of bit code switch SW-1 by resistance R 7, negative pole connects the 5V positive source, another termination 5V positive source of bit code switch SW-1, the other end ground connection of the positive pole of diode D2 and capacitor C 3, the collector of triode T3 connects the input end of integrated circuit U14A and connects the 5V positive source by resistance R 9, the input end of the output termination integrated circuit U14B of integrated circuit U14A, the output terminal 4 pin connection control circuits of integrated circuit U14B.
The control circuit of present embodiment is connected and composed by integrated circuit U10A, integrated circuit U10B, integrated circuit U11A, integrated circuit U12A, integrated circuit U12B, resistance R 11, resistance R 12, capacitor C 4, capacitor C 5, the model of integrated circuit U10A and integrated circuit U10B is 74HC221, the model of integrated circuit U11A is 74HC32, and the model of integrated circuit U12A and integrated circuit U12B is 74HC74A.2 pin of integrated circuit U10A and 9 pin of integrated circuit U10B connect output terminal 4 pin of integrated circuit U14B, and 14 pin of integrated circuit U10A connect that an end of capacitor C 4,15 pin connect the other end of capacitor C 4 and connect by resistance R 11 that 5V positive source, 3 pin connect the 5V positive source, 13 pin connect integrated circuit U11A input end 1 pin.6 pin of integrated circuit U10B connect an end of capacitor C 5, the other end that 7 pin connect capacitor C 5 and connect by resistance R 12 that 5V positive source, 10 pin and 11 pin connect the 5V positive source, 5 pin connect integrated circuit U11A input end 2 pin.Output terminal 3 pin of integrated circuit U11A connect 2 pin of integrated circuit U12A.3 pin of integrated circuit U12A connect frequency dividing circuit, 1 pin and 4 pin and connect 11 pin and the data latches that 5V positive source, 5 pin meet integrated circuit U12B.10 pin of integrated circuit U12B and 12 pin connect 5V positive source, 13 pin and 8 pin and connect Single Chip Microcomputer (SCM) system.
The frequency dividing circuit of present embodiment is connected and composed by integrated circuit U1A～integrated circuit U5A, integrated circuit U1B～integrated circuit U3B, the model of integrated circuit U1A～integrated circuit U4A, integrated circuit U1B～integrated circuit U3B is 74HC390, and the model of integrated circuit U5A is 74HC221.Collector, 4 pin that 1 pin of integrated circuit U1A meets triode T2 connect 3 pin, 7 pin connect 15 pin of integrated circuit U1B and 3 pin of integrated circuit U12A.12 pin of integrated circuit U1B connect 1 pin that 13 pin, 9 pin meet integrated circuit U2A, and the 2QA of integrated circuit U1B～2QD end is by the bus interface data latches.4 pin of integrated circuit U2A connect 15 pin that 3 pin, 7 pin meet integrated circuit U2B, and the 1QA of integrated circuit U2A～1QD end is by the bus interface data latches.12 pin of integrated circuit U2B connect 1 pin that 13 pin, 9 pin meet integrated circuit U3A, integrated circuit U2B 2QA～2QD end by the bus interface data latches.4 pin of integrated circuit U3A connect 15 pin that 3 pin, 7 pin meet integrated circuit U3B, and the 1QA of integrated circuit U3A～1QD end is by the bus interface data latches.12 pin of integrated circuit U3B connect 1 pin that 13 pin, 9 pin meet integrated circuit U4A, and the 2QA of integrated circuit U3B～2QD end is by the bus interface data latches.4 pin of integrated circuit U4A connect 1 pin that 3 pin, 7 pin meet integrated circuit U5A, and the 1QA of integrated circuit U4A～1QD end is by the bus interface data latches.14 pin of 2 pin of integrated circuit U1A～integrated circuit U4A and integrated circuit U1B～integrated circuit U3B connect 13 pin of integrated circuit U13A.14 pin of integrated circuit U5A connect an end of capacitor C 2, the other end that 15 pin connect capacitor C 2 and by resistance R 6 connect the 5V positive source, 13 pin connect data latches.
The data latches of present embodiment is connected and composed by integrated circuit U6, integrated circuit U7, integrated circuit U8, and the model of integrated circuit U6, integrated circuit U7, integrated circuit U8 is 74HC374.The 1D of integrated circuit U6～4D end holds 1QA～1QD end, 1Q～8Q by bus interface integrated circuit U2A to hold and Single Chip Microcomputer (SCM) system by 1Q～8Q end of bus interface integrated circuit U7 and 1Q～8Q of integrated circuit U8 by 2QA～2QD end, the 5D～8D of bus interface integrated circuit U1B.The 1D of integrated circuit U7～4D end is by 2QA～2QD end of bus interface integrated circuit U2B, 1QA～1QD end that 5D～8D end passes through bus interface integrated circuit U3A.The 1D of integrated circuit U8～4D end is by 2QA～2QD end of bus interface integrated circuit U3B, 1QA～1QD end that 5D～8D end passes through bus interface integrated circuit U4A.11 pin, 1 pin that 11 pin of integrated circuit U6 and integrated circuit U7 and integrated circuit U8 meet integrated circuit U12B connect Single Chip Microcomputer (SCM) system.
The Single Chip Microcomputer (SCM) system of present embodiment is connected and composed by integrated circuit U9, integrated circuit U14C, resistance R 13, capacitor C 7～capacitor C 9, crystal oscillator JZ, and integrated circuit U9 is that the one-chip computer model is 89C52.Outside time code signal is through the input end input of resistance R 13 by integrated circuit U14C, 10 pin of the output termination integrated circuit U9 of integrated circuit U14C, 12 pin of integrated circuit U9 connect 13 pin of integrated circuit U5A, 7 pin connect 13 pin of integrated circuit U12B, 13 pin connect 8 pin of integrated circuit U12B, P00～P07 end is by 1Q～8Q end of bus interface integrated circuit U8,24 pin connect 1 pin of integrated circuit U8,25 pin connect 1 pin of integrated circuit U7,26 pin connect 1 pin of integrated circuit U6,18 pin connect the oscillatory circuit that is connected with capacitor C 9 and crystal oscillator JZ by capacitor C 8 with 19 pin, 9 pin connect an end of capacitor C 7,11 pin serial ports output to computing machine or receiving equipment, another termination 5V positive source of capacitor C 7.
Principle of work of the present utility model is as follows:
The 10MHz frequency signal is imported through the base stage of resistance R 1 to triode T1 by capacitor C 1, triode T1 and triode T2 carry out shaping to the signal of input and amplify 1 pin output to integrated circuit U1A, and the frequency signal that produces 1Hz after division chain that integrated circuit U1A～integrated circuit U4A, integrated circuit U1B～integrated circuit U3B forms and the monostable shaping of integrated circuit U5A send the interruption " INTO " of integrated circuit U9.External perimysium reference signal second is imported, is carried out the shaping amplification through triode T4 and integrated circuit U14D by resistance R 14 simultaneously, 2 pin to integrated circuit U13A, integrated circuit U13A carries out monostable shaping to the standard second signal that amplifies through shaping, producing narrow pulse signal send the clear terminal zero clearing of integrated circuit U1A～integrated circuit U4A to come the synchronization frequency division chain respectively, integrated circuit U1A～integrated circuit U4A output terminal send input end 1D～8D of integrated circuit U6～integrated circuit U8 respectively, and integrated circuit U6～integrated circuit U8 latchs the information of signal by external event of input.The information that integrated circuit U6～integrated circuit U8 latchs is read data bus P00～P07 end of integrated circuit U9 respectively by P2.4～P2.6 position control end of single-chip microcomputer U9 from output terminal 1Q～8Q.Signal is by the incoming level of bit code switch SW-1 selection signal constantly in accident, if incident is an idle contact, input bit code switch SW-1 pushes the position of ON, if incident is the pulse input, then bit code switch SW-1 pushes the position of OFF.Accident moment signal is through the base stage of resistance R 8 to triode T3, amplify the elimination interference through triode T3 and output to integrated circuit U14A, through integrated circuit U14A and integrated circuit U14B integer, the forward position pulse zero hour of accident is as integrated circuit U10A trigger pulse, the finish time, trailing edge was as integrated circuit U10B trigger pulse, the pulse signal of two monostable outputs outputs to integrated circuit U11A simultaneously, integrated circuit U11A to the pulse signal of two monostable outputs carry out " or " back outputs to 2 pin of integrated circuit U12A by 2 pin of integrated circuit U12A, the clock pulse signal of integrated circuit U12A is provided by integrated circuit U1A, 5 pin of integrated circuit U12A output to integrated circuit U6～integrated circuit U8 and latch the zero hour of incident and trigger integrated circuit U12B and produce negative pulse, the interruption " INT1 " of integrated circuit U9 is provided, P23～P25 of integrated circuit U9 brings in the zero hour of reading the incident generation of latching simultaneously, the P16 end output pulse signal of integrated circuit U9 resets integrated circuit U12B, at this moment integrated circuit U12A exports the end pulse signal that the next pulse signal is an incident again, and also reset integrated circuit U12B the finish time that the incident that reads equally takes place.The beginning of such accident and end accurately constantly just go on record, and send by the serial port of single-chip microcomputer.The zero hour and the finish time of an accident are complete, can preserve with the form of file.
Claims (3)
1. accident device for accurately measuring constantly is characterized in that it comprises:
The Single Chip Microcomputer (SCM) system that complete machine is controlled;
10MHZ frequency signal and standard second signal to input carry out the frequency marking shaping circuit that shaping is amplified;
Accident moment signal to input carries out shaping amplifying signal shaping circuit;
Control circuit, the input termination signal transformation circuit of this circuit, output terminal connects Single Chip Microcomputer (SCM) system;
Frequency dividing circuit, the input termination frequency marking shaping circuit and the control circuit of this circuit;
Data latches, the input termination frequency dividing circuit of this circuit, output terminal connect Single Chip Microcomputer (SCM) system.
2. according to the described accident of claim 1 device for accurately measuring constantly, it is characterized in that said control circuit is: 2 pin of integrated circuit U10A and 9 pin of integrated circuit U10B connect the frequency marking shaping circuit, 14 pin of integrated circuit U10A connect an end of capacitor C 4,15 pin connect the other end of capacitor C 4 and connect the 5V positive source by resistance R 11,3 pin connect the 5V positive source, 13 pin connect integrated circuit U11A input end 1 pin, another termination 5V positive source of resistance R 11,6 pin of integrated circuit U10B connect an end of capacitor C 5,7 pin connect the other end of capacitor C 5 and connect the 5V positive source by resistance R 12,10 pin and 11 pin connect the 5V positive source, 5 pin connect integrated circuit U11A input end 2 pin, another termination 5V positive source of resistance R 12, output terminal 3 pin of integrated circuit U11A connect 2 pin of integrated circuit U12A, 3 pin of integrated circuit U12A connect frequency dividing circuit, 1 pin and 4 pin connect the 5V positive source, 5 pin connect 11 pin and the data latches of integrated circuit U12B, and 10 pin and 12 pin of integrated circuit U12B connect the 5V positive source, 8 pin and 13 pin connect Single Chip Microcomputer (SCM) system.
3. according to the described accident of claim 1 device for accurately measuring constantly, it is characterized in that said frequency marking shaping circuit comprises frequency shaping circuit and second signal transformation circuit, the frequency signal of 10MHz is by the input end input of frequency shaping circuit, the standard second signal is by the input end input of signal transformation circuit second, the output termination frequency dividing circuit of frequency shaping circuit and second signal transformation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200720031895 CN201057548Y (en) | 2007-05-30 | 2007-05-30 | Accurate measuring apparatus for time of burst event |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200720031895 CN201057548Y (en) | 2007-05-30 | 2007-05-30 | Accurate measuring apparatus for time of burst event |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201057548Y true CN201057548Y (en) | 2008-05-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200720031895 Expired - Fee Related CN201057548Y (en) | 2007-05-30 | 2007-05-30 | Accurate measuring apparatus for time of burst event |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201057548Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385334A (en) * | 2011-09-14 | 2012-03-21 | 成都天奥电子股份有限公司 | Distributed switching system of redundant timing system and switching method thereof |
-
2007
- 2007-05-30 CN CN 200720031895 patent/CN201057548Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385334A (en) * | 2011-09-14 | 2012-03-21 | 成都天奥电子股份有限公司 | Distributed switching system of redundant timing system and switching method thereof |
| CN102385334B (en) * | 2011-09-14 | 2013-09-04 | 成都天奥电子股份有限公司 | Distributed switching system of redundant timing system and switching method thereof |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080507 |