CN201054548Y - High-voltage start circuit for AC-DC converter - Google Patents
High-voltage start circuit for AC-DC converter Download PDFInfo
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- CN201054548Y CN201054548Y CNU2007201517735U CN200720151773U CN201054548Y CN 201054548 Y CN201054548 Y CN 201054548Y CN U2007201517735 U CNU2007201517735 U CN U2007201517735U CN 200720151773 U CN200720151773 U CN 200720151773U CN 201054548 Y CN201054548 Y CN 201054548Y
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Abstract
The utility model provides a high voltage starting circuit of AC-DC converter, which belongs to the electronic technical field, and comprises a PWM control IC and a power supply circuit, and is characterized in that one pin of the PWM control IC is connected with a starting high voltage through a lead, and the PWM control IC internally includes a first field effect transistor, an opening circuit and a closing circuit. By technically improving the internal circuit of the core PWM control IC of the high voltage starting circuit, the utility model automatically closes the internal circuit of the PWM control IC after the system completes high voltage starting, and ensures no creepage path between the starting high voltage and the earth. The utility model overcomes the defects of the prior technology of power loss caused by the creepage, and improves the efficiency of the whole system. Besides, by adopting the traditional components, the utility model has the advantages of low cost, simple circuit structure and stable system, as well as fairly high technical and economic benefits.
Description
Technical field
The utility model relates to a kind of start-up circuit, is specifically related to a kind of high-voltage starting circuit of the AC-DC of being applied to transducer.
Background technology
As shown in Figure 1, be the circuit structure diagram of AC-DC transducer in the prior art.When circuit start, starting resistor HV is by the pin VCC charging of resistance R hv and 4 pairs of PWM control IC of capacitor C, when the voltage of pin VCC reaches the starting resistor of UVLO module of PWM control IC inside, the work of PWM control IC, the second winding L s2 of transformer T1 produces voltage, main energy source is provided for the PWM control IC by diode D2, resistance R 1 and capacitor C 4.But behind the circuit working, can produce leakage current Istartup on the resistance R hv always, cause power loss.The computing formula of wasted power is as follows:
P＝Istartup
2*Rhv
Under the constant situation of resistance R hv two ends pressure drop, in order to improve overall system efficiency, should reduce leakage current Istartup, increase resistance R hv, but increase the startup response time lengthening that resistance R hv can make system.
The utility model content
In view of this, main purpose of the present utility model is to provide a kind of high-voltage starting circuit of AC-DC transducer, it carries out technological improvement by the internal circuit to the PWM control IC, after the PWM control IC is finished startup, close leakage current, avoided the influence of resistance R hv in the prior art simultaneously, reached the efficient of raising system and accelerate the purpose of the startup response time of system.
For achieving the above object, the technical solution adopted in the utility model is as follows:
A kind of high-voltage starting circuit of AC-DC transducer comprises PWM control IC and power supply circuits, it is characterized in that:
One pin of described PWM control IC is connected with the startup high pressure by lead, when the PWM control IC starts, produces a starting current on lead;
Described PWM control IC inside comprises first field effect transistor, open circuit and shut-off circuit; Wherein,
First field effect transistor includes first end, second end and the 3rd end, and first field effect transistor carries out the transition to cut-off state by conducting state after system powers on, its first end ground connection, and second end directly is connected with the startup high pressure, and the 3rd end provides first supply power voltage;
Open circuit is used for opening the internal circuit of PWM control IC after system powers on;
Shut-off circuit is used for closing leakage path after the PWM control IC is finished startup, makes described starting current become 0.
Described open circuit comprises the latch of second field effect transistor, PMOS pipe Q3 and inverter Q6 composition and is used for initialized capacitor C 1 and capacitor C 2, wherein,
The positive pole of capacitor C 1 is connected with the source electrode of PMOS pipe Q3 and the drain electrode of second field effect transistor, and negative pole is connected with the drain electrode of PMOS pipe Q3 and the grid of second field effect transistor;
The positive pole of capacitor C 2 is connected minus earth with the grid of PMOS pipe Q3;
The grid of PMOS pipe Q3 also is connected with the output of inverter Q6;
The input of inverter Q6 is connected with the grid of second field effect transistor, and its positive power source terminal voltage is provided by described first supply power voltage, its negative power end ground connection.
Described shut-off circuit comprises second field effect transistor, UVLO module, NMOS pipe Q4, NMOS pipe Q5 and inverter Q7, wherein,
The grid of NMOS pipe Q4 is connected its source ground with the output of inverter Q7;
The grid of NMOS pipe Q5 is connected with the input of inverter Q7, and its drain electrode is connected source ground with the grid of second field effect transistor;
The pin VCC of UVLO module is connected with the source electrode of second field effect transistor, and second supply power voltage is provided, and this second supply power voltage provides the positive power source terminal voltage of inverter Q7;
The negative power end ground connection of inverter Q7;
The pin SHD of UVLO module is connected pin GND ground connection with the grid of NMOS pipe Q5.
Described open circuit comprises the latch of second field effect transistor, PMOS pipe Q3 and inverter Q6 composition and is used for initialized capacitor C 1 and capacitor C 2;
Described shut-off circuit comprises second field effect transistor, UVLO module, NMOS pipe Q4, NMOS pipe Q5 and inverter Q7;
The 3rd end of described first field effect transistor is connected with the drain electrode of second field effect transistor;
The positive pole of capacitor C 1 is connected with the source electrode of PMOS pipe Q3 and the drain electrode of second field effect transistor, and negative pole is connected with the drain electrode of PMOS pipe Q3 and the grid of second field effect transistor;
The positive pole of capacitor C 2 is connected minus earth with the grid of PMOS pipe Q3;
The grid of PMOS pipe Q3 also is connected with the output of inverter Q6;
The input of inverter Q6 is connected with the grid of second field effect transistor, and its positive power source terminal voltage is provided by described first supply power voltage, its negative power end ground connection;
The grid of NMOS pipe Q4 is connected its source ground with the output of inverter Q7;
The grid of NMOS pipe Q5 is connected with the input of inverter Q7, and its drain electrode is connected source ground with the grid of second field effect transistor;
The pin VCC of UVLO module is connected with the source electrode of second field effect transistor, and second supply power voltage is provided, and this second supply power voltage provides the positive power source terminal voltage of inverter Q7;
The negative power end ground connection of inverter Q7;
The pin SHD of UVLO module is connected pin GND ground connection with the grid of NMOS pipe Q5;
The drain electrode of NMOS pipe Q4 is connected with the output of inverter Q6.
The 3rd end of described first field effect transistor provides first supply power voltage after by a diode forward conducting.
Described power supply circuits comprise a diode D2, a resistance R 1 and a capacitor C 4, be used for finishing the startup back and give described PWM control IC power supply in system, wherein the positive pole of diode D2 connects a Transformer Winding of AC-DC transducer, its negative pole is connected through the positive pole of resistance R 1 with capacitor C 4, the positive pole of capacitor C 4 also is connected with the pin VCC of described PWM control IC, the minus earth of capacitor C 4.
Described first supply power voltage provides a link, and this link is used to strengthen the stability of described first supply power voltage by a capacitor C 3 ground connection.
Described first field effect transistor is a N channel junction field-effect pipe.
Described second field effect transistor is the NMOS pipe.
The utility model is that the internal circuit to the core PWM control IC of high-voltage starting circuit carries out technological improvement, has set up first field effect transistor, open circuit and shut-off circuit in PWM control IC inside.First field effect transistor is a N channel junction field-effect pipe, its first end ground connection, and second end is connected with the startup high pressure by lead.High pressure rises to first end that makes first field effect transistor and the pressure reduction between second end reaches its pinch-off voltage when starting, first field effect transistor is ended, its the 3rd terminal voltage maintains near the absolute value of this pinch-off voltage, the positive power source terminal voltage of first supply power voltage as inverter Q6 is provided, also can after the diode forward conducting, provides first supply power voltage.Capacitor C 1, C2 are used for initializing circuit in the open circuit, and the latch that PMOS pipe Q3 and inverter Q6 form is used for the initial condition and the change procedure state of latch cicuit.The voltage of capacitor C 1, C2 is 0V before the PWM control IC starts, start moment in the PWM control IC, the voltage at capacitor C 1, C2 two ends remains unchanged, PMOS pipe Q3 conducting, inverter Q6 output low level, the grid potential of second field effect transistor raises gradually, the second field effect transistor conducting, and PWM control IC operating circuit is opened.After the second field effect transistor conducting, its source potential raises gradually, and the positive power source terminal voltage of inverter Q7 is provided.When this current potential is elevated to when making the UVLO module that action take place, the current potential of UVLO module pin SHD is uprised by low, NMOS pipe Q5 conducting, inverter Q7 upset, NMOS pipe Q4 closes, the latch upset that PMOS pipe Q3 and inverter Q6 form, second field effect transistor is ended, start high pressure between the ground without any leakage path, the internal circuit of PWM control IC is closed, system finishes the high voltage startup process.
The beneficial effects of the utility model are, carry out technological improvement by internal circuit to the core PWM control IC of high-voltage starting circuit, automatically close PWM control IC internal circuit after making system finish high voltage startup, start high pressure between the ground without any leakage path, overcome the shortcoming of bringing power loss in the prior art owing to leakage current, improved overall system efficiency.The utility model adopts traditional components and parts, and is with low cost, and circuit structure is simple, and system stability has higher technical economic benefit.
Description of drawings
Below in conjunction with the drawings and specific embodiments the utility model is further elaborated.
Fig. 1 is the high-voltage starting circuit figure of AC-DC transducer in the prior art;
Fig. 2 is the high-voltage starting circuit figure of the AC-DC transducer of the utility model embodiment;
Fig. 3 is the open circuit of the utility model embodiment and the schematic diagram of shut-off circuit.
Embodiment
Consult Fig. 2, it is the high-voltage starting circuit figure of the AC-DC transducer of the utility model embodiment.As shown in the figure, High Level AC Voltage changes sinusoidal signal into the pulsating direct current signal through the rectifier bridge rectification, obtains more level and smooth high-voltage dc signal through filter capacitor Chv filtering again, provides to start high pressure HV.The High Level AC Voltage input range obtains the high direct voltage scope between 30V～500V between 64V～264V.Start high pressure HV and directly be connected, starting current Istartup is provided with the pin HV of PWM control IC by lead.By the action of inner open circuit of PWM control IC and shut-off circuit, system finishes startup, and closes the leakage path of startup high pressure HV to ground automatically, and starting current Istartup becomes 0.The pin VCC of PWM control IC is by capacitor C 4 ground connection, and this pin also is connected with the negative pole of diode D2 by resistance R 1.The positive pole of diode D2 is connected with the end of the same name of the second winding L s2 of the transformer T1 of AC-DC transducer, and by this winding earth.The pin OUT of PWM control IC is connected with the grid of NMOS pipe Q8.The source electrode of NMOS pipe Q8 is by resistance R 2 ground connection, and its drain electrode is connected with the end of the same name of the first winding L p of the transformer T1 of AC-DC transducer, and is connected with the startup high pressure by this winding.High direct voltage obtains output voltage V out after transformer T1 step-down and Filtering Processing.
When rising to, the current potential of the pin VCC of the UVLO module of PWM control IC inside makes the action of UVLO module, the work of PWM control IC, its pin OUT output drive signal control NMOS pipe Q8 conducting, the first winding L p of transformer T1 goes up and produces electric current, the end of the same name of the second winding L s2 obtains positive potential by electromagnetic induction, by the power supply circuits of forming by diode D2, resistance R 1 and capacitor C 4 the PWM control IC is powered, provide the PWM control IC main energy source, keep its operating state.
The pin GND ground connection of PWM control IC, Voltage Feedback pin Vfb is connected with a feedback circuit, feedback circuit comprises resistance R 3, photoelectrical coupler U1 and voltage stabilizing didoe D3, output voltage V out feeds back the error amplifier that is input to PWM control IC inside through resistance R 3, photoelectrical coupler U1, relatively produces error voltage in the back with reference voltage.Current detecting pin Isense is connected with the source electrode of NMOS pipe Q8; being used for voltage and error voltage that the first winding L p electric current with transformer T1 produces on resistance R 2 compares; produce the width of modulating pulse; error signal is controlled the peak current of circuit, reached the purpose of current-limiting protection.The internal circuit of PWM control IC except that the utility model technological improvement part, all adopts circuit connection structure commonly used in the prior art, and operation principle is not given unnecessary details at this.
Below in conjunction with Fig. 3, the open circuit of the utility model technological improvement part PWM control IC inside and the circuit structure and the operation principle of shut-off circuit are elaborated.As shown in Figure 3, be the open circuit of the utility model embodiment and the schematic diagram of shut-off circuit.
Open circuit comprises the second field effect transistor Q2, PMOS pipe Q3, inverter Q6 and is used for initialized capacitor C 1 and capacitor C 2.PMOS pipe Q3 and inverter Q6 form latch structure.Shut-off circuit comprises the second field effect transistor Q2, UVLO module, NMOS pipe Q4, NMOS pipe Q5 and inverter Q7.The first field effect transistor Q1 has the first end grid, the drain electrode of second end and the 3rd end source electrode, its first end grounded-grid, the drain external pin HV of corresponding PWM control IC of second end, be connected with the startup high pressure by lead, the 3rd end source electrode is connected with the drain electrode of the second field effect transistor Q2 by diode D1, and the negative pole of diode D1 provides the first supply power voltage VCC1.The negative pole of diode D1 is used to strengthen the stability of the first supply power voltage VCC1 also by capacitor C 3 ground connection, prevents that the voltage signal shake from bringing misoperation.The positive pole of capacitor C 1 is connected with the source electrode of PMOS pipe Q3 and the drain electrode of the second field effect transistor Q2, and negative pole is connected with the drain electrode of PMOS pipe Q3 and the grid of the second field effect transistor Q2.The positive pole of capacitor C 2 is connected minus earth with the grid of PMOS pipe Q3.The grid of PMOS pipe Q3 also is connected with the output of inverter Q6.The input of inverter Q6 is connected with the grid of the second field effect transistor Q2, and its positive power source terminal voltage is provided by the first supply power voltage VCC1, its negative power end ground connection.The grid of NMOS pipe Q4 is connected its source ground with the output of inverter Q7.The grid of NMOS pipe Q5 is connected with the input of inverter Q7, and its drain electrode is connected source ground with the grid of the second field effect transistor Q2.The pin VCC of UVLO module is connected with the source electrode of the second field effect transistor Q2, and the second supply power voltage VCC is provided, and the second supply power voltage VCC provides the positive power source terminal voltage of inverter Q7, the negative power end ground connection of Q7.The pin SHD of UVLO module is connected pin GND ground connection with the grid of NMOS pipe Q5.The drain electrode of NMOS pipe Q4 is connected with the output of inverter Q6.
The first field effect transistor Q1 is a N channel junction field-effect pipe in this embodiment, and its drain electrode and source electrode are symmetrical, can exchange.The second field effect transistor Q2 is the NMOS pipe.The preceding first field effect transistor Q1 that powers on of system is in conducting state, after powering on, pressure reduction between the startup high pressure rises to the grid that makes the first field effect transistor Q1 and drains reaches its pinch-off voltage, the first field effect transistor Q1 ends, its source potential maintains near the absolute value of pinch-off voltage of field effect transistor, by diode D1 forward conduction, obtain the first supply power voltage VCC1, magnitude of voltage is about 17V.Capacitor C 3 is used for the burr of elimination electric current, strengthens the stability of the first supply power voltage VCC1.
Before system start-up, the voltage on capacitor C 1 and the capacitor C 2 is 0V.In system start-up moment, the voltage at capacitor C 1 and capacitor C 2 two ends remains unchanged, and the anodal current potential of capacitor C 1 and capacitor C 2 still is 0V, PMOS pipe Q3 conducting this moment, inverter Q6 output low level.Because PMOS pipe Q3 conducting, the grid potential of the second field effect transistor Q2 raises and makes the second field effect transistor Q2 conducting, and PWM control IC internal circuit is opened.After the second field effect transistor Q2 conducting, the second supply power voltage VCC is elevated to about 15V gradually, the positive power source terminal voltage of inverter Q7 is provided, the UVLO module is moved, this moment, the current potential of UVLO module pin SHD was uprised by low, made NMOS pipe Q5 conducting, inverter Q7 upset, the output current potential of inverter Q7 ends NMOS pipe Q4 by high step-down.After the NMOS pipe Q5 conducting, its drain potential is by high step-down, and PMOS manages the latch state turnover of Q3 and inverter Q6 composition, the second field effect transistor Q2 ends, start high pressure between the ground without any leakage path, the internal circuit of PWM control IC is closed, system finishes the high voltage startup process.
As above it is not restricted to listed utilization in specification and the execution mode although embodiment of the present utility model is open, and it can be applied to the various fields of the present utility model that are fit to fully.The switching tube of open circuit and shut-off circuit mainly adopts the NMOS pipe in the utility model, and this is owing to for using the PMOS pipe, use the NMOS pipe can reduce area of chip to a great extent, saves cost.For those skilled in the art, can easily realize replacement between N pipe and the P pipe and other modification, therefore under the universal that does not deviate from equivalency range and limited, the utility model is not limited to specific details and the embodiment that illustrates here.
Claims (9)
1. the high-voltage starting circuit of an AC-DC transducer comprises PWM control IC and power supply circuits, it is characterized in that:
One pin of described PWM control IC is connected with the startup high pressure by lead, when the PWM control IC starts, produces a starting current on lead;
Described PWM control IC inside comprises first field effect transistor, open circuit and shut-off circuit, wherein,
First field effect transistor includes first end, second end and the 3rd end, and first field effect transistor carries out the transition to cut-off state by conducting state after system powers on, its first end ground connection, and second end directly is connected with the startup high pressure, and the 3rd end provides first supply power voltage;
Open circuit is used for opening the internal circuit of PWM control IC after system powers on;
Shut-off circuit is used for closing leakage path after the PWM control IC is finished startup, makes described starting current become 0.
2. the high-voltage starting circuit of AC-DC transducer according to claim 1 is characterized in that described open circuit comprises the latch of second field effect transistor, PMOS pipe Q3 and inverter Q6 composition and is used for initialized capacitor C 1 and capacitor C 2, wherein,
The positive pole of capacitor C 1 is connected with the source electrode of PMOS pipe Q3 and the drain electrode of second field effect transistor, and negative pole is connected with the drain electrode of PMOS pipe Q3 and the grid of second field effect transistor;
The positive pole of capacitor C 2 is connected minus earth with the grid of PMOS pipe Q3;
The grid of PMOS pipe Q3 also is connected with the output of inverter Q6;
The input of inverter Q6 is connected with the grid of second field effect transistor, and its positive power source terminal voltage is provided by described first supply power voltage, its negative power end ground connection.
3. the high-voltage starting circuit of AC-DC transducer according to claim 1 is characterized in that described shut-off circuit comprises second field effect transistor, UVLO module, NMOS pipe Q4, NMOS pipe Q5 and inverter Q7, wherein,
The grid of NMOS pipe Q4 is connected its source ground with the output of inverter Q7;
The grid of NMOS pipe Q5 is connected with the input of inverter Q7, and its drain electrode is connected source ground with the grid of second field effect transistor;
The pin VCC of UVLO module is connected with the source electrode of second field effect transistor, and second supply power voltage is provided, and this second supply power voltage provides the positive power source terminal voltage of inverter Q7;
The negative power end ground connection of inverter Q7;
The pin SHD of UVLO module is connected pin GND ground connection with the grid of NMOS pipe Q5.
4. the high-voltage starting circuit of AC-DC transducer according to claim 1 is characterized in that,
Described open circuit comprises the latch of second field effect transistor, PMOS pipe Q3 and inverter Q6 composition and is used for initialized capacitor C 1 and capacitor C 2;
Described shut-off circuit comprises second field effect transistor, UVLO module, NMOS pipe Q4, NMOS pipe Q5 and inverter Q7;
The 3rd end of described first field effect transistor is connected with the drain electrode of second field effect transistor;
The positive pole of capacitor C 1 is connected with the source electrode of PMOS pipe Q3 and the drain electrode of second field effect transistor, and negative pole is connected with the drain electrode of PMOS pipe Q3 and the grid of second field effect transistor;
The positive pole of capacitor C 2 is connected minus earth with the grid of PMOS pipe Q3;
The grid of PMOS pipe Q3 also is connected with the output of inverter Q6;
The input of inverter Q6 is connected with the grid of second field effect transistor, and its positive power source terminal voltage is provided by described first supply power voltage, its negative power end ground connection;
The grid of NMOS pipe Q4 is connected its source ground with the output of inverter Q7;
The grid of NMOS pipe Q5 is connected with the input of inverter Q7, and its drain electrode is connected source ground with the grid of second field effect transistor;
The pin VCC of UVLO module is connected with the source electrode of second field effect transistor, and second supply power voltage is provided, and this second supply power voltage provides the positive power source terminal voltage of inverter Q7;
The negative power end ground connection of inverter Q7;
The pin SHD of UVLO module is connected pin GND ground connection with the grid of NMOS pipe Q5;
The drain electrode of NMOS pipe Q4 is connected with the output of inverter Q6.
5. according to the high-voltage starting circuit of claim 1 or 4 described AC-DC transducers, the 3rd end that it is characterized in that described first field effect transistor provides first supply power voltage after by a diode forward conducting.
6. the high-voltage starting circuit of AC-DC transducer according to claim 1, it is characterized in that described power supply circuits comprise a diode D2, a resistance R 1 and a capacitor C 4, be used for finishing the startup back and give described PWM control IC power supply in system, wherein the positive pole of diode D2 connects a Transformer Winding of AC-DC transducer, its negative pole is connected through the positive pole of resistance R 1 with capacitor C 4, the positive pole of capacitor C 4 also is connected with the pin VCC of described PWM control IC, the minus earth of capacitor C 4.
7. according to the high-voltage starting circuit of claim 1 or 2 or 4 arbitrary described AC-DC transducers, it is characterized in that described first supply power voltage provides a link, this link is used to strengthen the stability of described first supply power voltage by a capacitor C 3 ground connection.
8. according to the high-voltage starting circuit of claim 1 or 4 arbitrary described AC-DC transducers, it is characterized in that described first field effect transistor is a N channel junction field-effect pipe.
9. according to the high-voltage starting circuit of claim 2 or 3 or 4 arbitrary described AC-DC transducers, it is characterized in that described second field effect transistor is the NMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201517735U CN201054548Y (en) | 2007-06-26 | 2007-06-26 | High-voltage start circuit for AC-DC converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2007201517735U CN201054548Y (en) | 2007-06-26 | 2007-06-26 | High-voltage start circuit for AC-DC converter |
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| CNU2007201517735U Expired - Fee Related CN201054548Y (en) | 2007-06-26 | 2007-06-26 | High-voltage start circuit for AC-DC converter |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100589312C (en) * | 2007-06-26 | 2010-02-10 | 绿达光电(苏州)有限公司 | HV starting circuit for AC-DC converter |
| CN101369773B (en) * | 2007-08-10 | 2012-09-05 | 技领半导体(上海)有限公司 | Method, device and system for start-up time reduction in switching regulators |
| CN102832797A (en) * | 2012-08-24 | 2012-12-19 | 电子科技大学 | High-voltage current source multiplexing sampling circuit and switch power supply |
| CN103887969A (en) * | 2014-03-04 | 2014-06-25 | 东莞博用电子科技有限公司 | High-voltage power supply circuit applied to integrated circuit |
-
2007
- 2007-06-26 CN CNU2007201517735U patent/CN201054548Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100589312C (en) * | 2007-06-26 | 2010-02-10 | 绿达光电(苏州)有限公司 | HV starting circuit for AC-DC converter |
| CN101369773B (en) * | 2007-08-10 | 2012-09-05 | 技领半导体(上海)有限公司 | Method, device and system for start-up time reduction in switching regulators |
| CN102832797A (en) * | 2012-08-24 | 2012-12-19 | 电子科技大学 | High-voltage current source multiplexing sampling circuit and switch power supply |
| CN103887969A (en) * | 2014-03-04 | 2014-06-25 | 东莞博用电子科技有限公司 | High-voltage power supply circuit applied to integrated circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Supec (Suzhou) Co., Ltd. Assignor: Grenergy Opto. (Suzhou) Inc. Contract fulfillment period: 2008.8.1 to 2013.7.31 Contract record no.: 2008990000687 Denomination of utility model: HV starting circuit for AC-DC converter Granted publication date: 20080430 License type: Exclusive license Record date: 20081013 |
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| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2008.8.1 TO 2013.7.31; CHANGE OF CONTRACT Name of requester: KAIYUAN IC (SUZHOU) CO., LTD. Effective date: 20081013 |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080430 Termination date: 20100626 |