CN200993963Y

CN200993963Y - Highvoltage power integrated circuit isolating structure

Info

Publication number: CN200993963Y
Application number: CN 200620165096
Authority: CN
Inventors: 易扬波; 徐申; 李海松; 孙伟锋; 夏晓娟; 李�杰; 时龙兴
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2006-12-15
Filing date: 2006-12-15
Publication date: 2007-12-19
Anticipated expiration: 2016-12-15

Abstract

The utility model discloses a high pressure power integrate circuit isolation structure separated between the high pressure device and the low pressure device of a bulk silicon process power integrate circuit, and is composed of a P-shaped substrate, which is provided with an N-shaped epitaxy, and two field oxides and a heavily doped N-shaped zone are arranged on the N-shaped epitaxy, and the heavily doped N-shaped zone is arranged between the two field oxides; two P-shaped isolation traps are arranged in the N-shaped epitaxy, below the two field oxides respectively, and the two P-shaped isolation traps divide the N-shaped epitaxy into three pieces; the heavily doped N-shaped zone is arranged between the two P-shaped isolation traps, and a heavily doped P-shaped zone is arrange above the two P-shaped isolation traps; the heavily doped N-shaped zone and the heavily doped P-shaped zone are connected with a zero potential. The utility model can prevent the parasitism of the silicon controlled structure in the bulk silicon high pressure power integrates circuit.

Description

The high-voltage power integrated circuit isolation structure

Technical field

The utility model is a kind of isolation structure that is applicable between bulk silicon technological power integrated circuit high tension apparatus and the low-voltage device, relates in particular to a kind of high-voltage power integrated circuit isolation structure.

Background technology

In power integrated circuit, P-type mos (PMOS) and N type metal oxide semiconductor (NMOS) are formed CMOS (Complementary Metal Oxide Semiconductor) (CMOS) circuit.Since the parasitic PNP bipolar transistor of PMOS, NMOS parasitic npn bipolar transistor, controllable silicon (SCR) structure that combines and just constituted PNPN.When SCR structure is triggered, the resistance of this structure is greatly reduced, there is big electric current to flow through structure.All there is intrinsic triggering thresholding in every kind of SCR structure, and control controllable silicon trigger method is a lot.

Under some operating state of power integrated circuit, charge carrier injects to low-pressure section in high-voltage section branch, triggers the parasitic SCR structure of low voltage CMOS.The utility model reduces to inject charge carrier by introducing the isolation structure between the high-low pressure, prevents that SCR structure from triggering.

At present a lot of high-low pressure isolation structures need particular semiconductor preparation technology, on development technology flow process and inapplicable.

Summary of the invention

The utility model is a kind of high-voltage power integrated circuit isolation structure of isolating between bulk silicon technological power integrated circuit high tension apparatus and the low-voltage device that is applicable to, the utility model can prevent effectively that parasitic SCR structure triggers in the body silicon high-voltage power integrated circuit.

The utility model adopts following technical scheme:

A kind of high-voltage power integrated circuit isolation structure, comprise: P type substrate, be provided with N type extension at P type substrate, on N type extension, be provided with 2 field oxides, be provided with heavy doping N type district on the N type extension and this heavy doping N type district is positioned between 2 field oxides, in N type extension, be provided with 2 P type isolation wells, these 2 P type isolation wells lay respectively at the below of 2 field oxides, and these 2 P type isolation wells are separated into 3 with N type extension, above-mentioned heavy doping N type district is positioned between 2 P type isolation wells, upper end at 2 P type isolation wells is respectively equipped with the heavy doping p type island region, and above-mentioned heavy doping N type district and heavy doping p type island region are connected with zero potential.

Compared with prior art, the utlity model has following advantage:

(1) structure of the present utility model effectively absorbed power integrated circuit when work be injected into substrate from high voltage structures, be re-introduced into the charge carrier of low-pressure structure, thereby improve the difficulty that the parasitic controllable silicon of low voltage CMOS structure triggers.

(2) in the utility model structure, the extension island connecting to neutral current potential between two P type isolation wells makes the charge carrier of absorption flow into the earth, rather than flows into low-tension supply, can avoid like this causing the chip reliability problem because charge carrier injects low-tension supply.

(3) isolation structure of the present utility model only utilizes the design of chip layout can prevent that controllable silicon from triggering, and therefore all technologies and former technological process compatibility do not need to revise intrinsic technological process, need not increase the technology cost.

Description of drawings

Fig. 1 is the isolation structure profile.

Fig. 2 is the utility model isolation structure substrate current schematic diagram.

Fig. 3 is a conventional isolation structures substrate current schematic diagram.

Embodiment

With reference to Fig. 1, a kind of high-voltage power integrated circuit isolation structure, comprise: P type substrate 1, be provided with N type extension 2 at P type substrate 1, on N type extension 2, be provided with 2

field oxides

3,4, on N type extension 2, be provided with heavy doping N type district 5 and this heavy doping N type district 5 is positioned at 2 field oxides 3, between 4, in N type extension 2, be provided with 2 P

type isolation wells

6,7, these 2 P

type isolation wells

6,7 lay respectively at 2

field oxides

3,4 below, and these 2 P

type isolation wells

6,7 are separated into 3 with N type extension 2, above-mentioned heavy doping N type district 5 is positioned at 2 P type isolation wells 6, between 7, at 2 P

type isolation wells

6,7 upper end is respectively equipped with heavy doping p type island region 8,9, above-mentioned heavy doping N type district 5 and heavy doping p type island region 8,9 are connected with zero

potential.In field oxide

3,4, heavy doping p type island region 8,9 and heavy doping N type district 5, be provided with dielectric layer 10, be provided with connecting to neutral current potential metal 11 and this connecting to neutral current potential metal 11 is connected with heavy doping N type district 5 and heavy doping p type island region 8,9 at dielectric layer 10.

Provided the utility model structured substrate current diagram in Fig. 2, Fig. 3 has provided traditional single P type isolation well substrate current schematic diagram, illustrates that the utility model structure absorbs the ability that serves as a contrast low current and significantly improves.

The utility model in the preparation, at first select P type substrate, make dark N type extension, the P type isolation well for preparing the break-through extension then, prepare field oxide then, carry out injection of heavy doping N type district and heavy doping p type island region then and inject, then dielectric layer deposited and etching, next be the preparation and the Passivation Treatment of connecting to neutral current potential metal lead wire, the complete and former extension power integrated circuit preparation technology compatibility of whole technical process.

Claims

1, a kind of high-voltage power integrated circuit isolation structure, comprise: P type substrate (1), be provided with N type extension (2) at P type substrate (1), on N type extension (2), be provided with 2 field oxides (3,4), it is characterized in that on N type extension (2), being provided with heavy doping N type district (5) and this heavy doping N type district (5) is positioned at 2 field oxides (3,4) between, in N type extension (2), be provided with 2 P type isolation wells (6,7), these 2 P type isolation wells (6,7) lay respectively at 2 field oxides (3,4) below, and these 2 P type isolation wells (6,7) N type extension (2) is separated into 3, above-mentioned heavy doping N type district (5) is positioned at 2 P type isolation wells (6,7) between, at 2 P type isolation wells (6,7) upper end is respectively equipped with heavy doping p type island region (8,9), above-mentioned heavy doping N type district (5) and heavy doping p type island region (8,9) be connected with zero potential.

2, high-voltage power integrated circuit isolation structure according to claim 1, it is characterized in that in field oxide (3,4), heavy doping p type island region (8,9) and heavy doping N type district (5), being provided with dielectric layer (10), be provided with connecting to neutral current potential metal (11) and this connecting to neutral current potential metal (11) is connected with heavy doping N type district (5) and heavy doping p type island region (8,9) at dielectric layer (10).