CN200990651Y - Video frequency division amplifier - Google Patents
Video frequency division amplifier Download PDFInfo
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- CN200990651Y CN200990651Y CNU2006201453584U CN200620145358U CN200990651Y CN 200990651 Y CN200990651 Y CN 200990651Y CN U2006201453584 U CNU2006201453584 U CN U2006201453584U CN 200620145358 U CN200620145358 U CN 200620145358U CN 200990651 Y CN200990651 Y CN 200990651Y
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Abstract
The utility model relates to video frequency control technique, providing a video frequency dividing amplifier pointing against the picture misplacement problem of the prior art caused by the difference of the field synchronizing signal. The video frequency dividing amplifier comprises a main amplifier and a plurality of driven amplifiers; the main amplifier and the driven amplifiers all comprise a frame buffer module; the main amplifier also comprises a main reading and writing control module which is used for controlling the concurrent reading of the main and the driven amplifiers and treating the picture data based on that the main and the driven amplifiers delay the longest field synchronizing signal to generate united reading field synchronizing signal. Determining the united reading field synchronizing signal in advance can control the concurrent reading of all the amplifiers and treat the corresponding picture data of the same group picture, and eliminate the inaccuracy between the field synchronizing signals so as to solve the picture displacement problem caused by the inaccuracy.
Description
Technical field
The utility model relates to the video control technology, more particularly, relates to a kind of video and cuts apart amplifier.
Background technology
In digital video control field, when the output resolution ratio of image surpasses the physical resolution of special image processing and amplifying chip itself (for example 1920 * 1080P) time, the normal mode that adopts multi-disc special image processing and amplifying chips parallel working makes up the large-scale full color display of ultrahigh resolution.In this type of design, a two field picture is divided into m * n equal portions, the amplifier that comprises special image processing and amplifying chip by m * n carry out that high-quality interpolation is amplified and optimization process after, mail to m * n demonstration subregion, the demonstration of realization ultrahigh resolution image.
Yet, in actual application, the delay that each amplifier can occur being uneven in length when handling vision signal.Nonsynchronous phenomenon will appear in the read-write field sync signal of each control amplifier, and so, when showing moving image, each smaller screen that constitutes large-size screen monitors the image offset phenomenon can occur at intersection, has a strong impact on whole display effect.For example, Fig. 1 is the read-write sequence figure of 2 image amplifiers of prior art.As shown in Figure 1, VS is the primary field synchronizing signal of normal video image, and VS1 is the field sync signal of first amplifier, and section time of delay of its relative primary field synchronizing signal VS is t1.VS2 is the field sync signal of second amplifier, and section time of delay of its relative primary field synchronizing signal VS is t2, owing to t2＞t1, causes the field sync signal of two amplifiers to have delay error Δ t=t2-t1, i.e. figure bend zone A.As can be seen from the figure, in hatched example areas A, first amplification controller is being handled the 2nd field data S2, and second amplification controller is also being handled the 1st field data S1, and wrong frame has appearred in the data flow of two amplifiers, i.e. image offset.In like manner, when the every field data of this reprocessing, this image offset that is caused by delay error all can occur.When showing still image, because the data of continuous multiple frames image are identical, human eye still is difficult for discovering this by the asynchronous image offset phenomenon that causes of field sync signal.But showing moving image, especially when the rate travel of moving image is the integral multiple of field frequency,, will produce tangible image offset, influence the quality and the appreciation effect of image greatly at the boundary of two amplifier display frames.
Therefore, need the nonsynchronous problem of field sync signal that technical scheme solves each amplifier.
The utility model content
The technical problems to be solved in the utility model is, in the prior art because the asynchronous image offset problem that causes of field sync signal provides a kind of video to cut apart amplifier.
The technical scheme that its technical problem that solves the utility model adopts is: construct a kind of video and cut apart amplifier, comprise main amplifier and some from amplifier, described master and slave amplifier all comprises frame buffer module, and described main amplifier also comprises,
Master's read-write control module is used for postponing the longest field sync signal generation unification based on described master and slave amplifier and reads field sync signal, controls described master and slave amplifier according to this and reads also image data processing synchronously.
Cut apart in the amplifier at video described in the utility model, described main read-write control module comprises:
Signal receiving module is used to receive the primary field synchronizing signal and from the field sync signal of described master and slave amplifier;
Computing module, the delay that is used to calculate the described relatively primary field synchronizing signal of described master and slave amplifier field sync signal;
Comparison module is used for determining that described master and slave amplifier field sync signal postpones the longest field sync signal;
The signal generation module after being used for field sync signal that described delay is the longest and postponing a time of delay section, generates and unifiedly reads field sync signal, mails to described from amplifier.
Cut apart in the amplifier at video described in the utility model, describedly comprise from the read-write control module, be used to send its field sync signal, receive simultaneously from the unification of described main read-write control module and read field sync signal from amplifier.
Cut apart in the amplifier at video described in the utility model, described one time of delay section comprise two address locations clock cycle at interval at least.
Cut apart in the amplifier at video described in the utility model, described frame buffer module is a high speed single frames memory module.
Implement video of the present utility model and cut apart amplifier, has following beneficial effect, by pre-determining the unified field sync signal of reading, all amplifiers of may command read and handle the same group of correspondence image data in the image simultaneously, eliminate the error between the field sync signal, and then solve thus that error causes the image offset problem.
Description of drawings
The utility model is described in further detail below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the read-write sequence figure of 2 image amplifiers of prior art;
Fig. 2 is the logical construction schematic diagram that the utility model video is cut apart amplifier;
Fig. 3 is that the utility model video is cut apart the structural representation that amplifier main amplifier master reads and writes control module;
Fig. 4 is the generation schematic diagram that field signal is read in the utility model unification;
Fig. 5 is the read-write schematic diagram of the long delay amplifier of the utility model;
Fig. 6 is the read-write schematic diagram of the non-long delay amplifier of the utility model.
Embodiment
The utility model has been introduced a kind of video and has been cut apart amplifier, below just with specific embodiment it is introduced in conjunction with the accompanying drawings.
Fig. 2 is the logical construction schematic diagram that the utility model video is cut apart amplifier.As shown in Figure 2, video of the present invention is cut apart amplifier and is comprised that 1 main amplifier and 3 are from amplifier.Main amplifier further comprises main read-write control module; Further comprise from the read-write control module from amplifier; Master and slave read-write control module all can adopt FPGA (field programmable gate array) to realize, also can adopt single-chip microcomputer to realize; In addition, master and slave amplifier includes frame buffer module, can use high speed single frames stores synchronized body to realize.In running, the main read-write control module of main amplifier receives the field sync signal since amplifier, as VS2, VS3 and VS4, and the field sync signal VS1 of self and the field sync signal VS2, the VS3 that receive and VS4 and primary field synchronizing signal VS compared, find out with primary field synchronizing signal VS and compare the longest field sync signal time of delay, after then the field sync signal that finds being postponed a time period, generate unification and read field sync signal VS_read, mail to all from amplifier.After this, master and slave amplifier is just read field sync signal VS_read according to the unification of this calibration, reads synchronously and image data processing.
It should be noted that, though video shown in Figure 2 is cut apart amplifier and only comprised 3 from amplifier, those skilled in the art should be understood that in actual applications, be not limited only to 3 from the quantity of amplifier, can set quantity according to concrete needs from amplifier.
Fig. 3 is that video of the present invention is cut apart the structural representation that amplifier main amplifier master reads and writes control module.As shown in Figure 3, main read-write control module comprises signal receiving module, is used to receive the primary field synchronizing signal and from the field sync signal of master and slave amplifier; Computing module, the delay that is used to calculate the relative primary field synchronizing signal of master and slave amplifier field sync signal; Comparison module is used for determining that master and slave amplifier field sync signal postpones the longest field sync signal; The signal generation module is used for after postponing the longest field sync signal and postponing a time period, generates unifiedly to read field sync signal, mails to from amplifier.
The implementation procedure of cutting apart the synchronous reading video data of master and slave amplifier in the amplifier below in conjunction with concrete operations explanation video of the present invention.
Fig. 4 is the generation schematic diagram that field signal is read in the utility model unification.As shown in Figure 4, VS is the primary field synchronizing signal, and VS1 is the field sync signal of writing of main amplifier, and VS2～VS4 is 3 field sync signals of writing from amplifier.With primary field synchronizing signal VS is standard, and the main read-write control module of main amplifier is easy to judge the delay t3＞t4＞t2＞t1 of VS1～VS4 with respect to VS, and postponing the longest field sync signal is VS3.So main read-write control module postpones Δ t again with VS3, makes its effective zero-time section that lags behind the VS3 write data slightly, generates a new field sync signal VS_read, this signal is the unified field sync signal of reading.In comparison procedure, if find there to be the field sync signal of two same delay, and the delay of the two is the longest, then is preceding being as the criterion with ordering, or can select wherein any one at random.Though the field sync signal of reading of master and slave amplifier all is calibrated to and unified reads field sync signal, the field sync signal of writing of each single amplifier still remains unchanged, and promptly the field time section of writing of each controller is not quite similar, and is asynchronous.As can be seen from the figure, although each controller is to carry out according to original separately field sync signal when writing same field data, starting and ending point is all inequality, but starting point of reading and end point all are unified, though the position difference that each controller is write, but all at the video data of reading same same position, promptly realized each controller read field signal synchronously, guarantee the consistency that each controller image shows, shown the inconsistent phenomenon that the subregion intersection occurs at each when having avoided showing moving image.
Digital video is cut apart the digital video after amplifier amplifies optimization, all line by line scan, in technical solution of the present invention, the frame buffer module of each control amplifier adopts high speed single frames stores synchronized bulk-mode, dynamically or static state all can, as long as satisfy the capacity of frame data.But single frames stores synchronized body read-while-write is read several clock cycle of sequential and address space in advance but should arrange to write sequential in actual applications, to guarantee the hysteresis and the validity of read data.Below we suppose that high speed single frames stores synchronized body address space is from 00H to 0FFH, do not consider the flyback of field signal for sake of convenience, and with Fig. 5 and Fig. 6, further specify the read-write control of high speed single frames stores synchronized body address space.
Fig. 5 is the read-write schematic diagram of the long delay amplifier of the utility model.As shown in Figure 5, read effective starting point H point that field sync signal VS_read lags behind the VS3 write data slightly, the time period length of hysteresis is Δ t.At the H point, long delay amplifier 3 begins to write the start element of the 2nd field data, and the J point after the H point postpones Δ t, and amplifier 3 is read under the control of field sync signal VS_read unified, begins to read the start element of the 2nd field picture data with other amplifier.I point in the drawings, the write address pointer of control amplifier 3 points to the last address of second field data, and the K point after the I point postpones Δ t is read address pointer just points to the 2nd field picture data with other amplifier last address.In a word, effective zero-time section Δ t that field sync signal VS_read lags behind the VS3 write data is all the time read in the unification of long delay control amplifier 3, and this Δ t staggers two address locations clock cycle at interval at least.
Fig. 6 is the read-write schematic diagram of the non-long delay amplifier of the utility model.As shown in the figure, the long delay amplifier 4 of VS4 right and wrong write field sync signal, VS_read is the unified field sync signal of reading, and the VS_read that hypothesis generates lags behind a VS4 40H address space.Among Fig. 6, the D point is the starting point of the 2nd field picture valid data, and this amplifier 4 begins to write the start element 00H of the 2nd field data, reads sequential this moment just in the content of D ' reading the 1st field picture data 0C0H unit.E ' spot magnifier 4 is under the control of reading field sync signal VS_read among the figure, begins to read the start element 00H of the 2nd field picture data with other amplifier, writes sequential is then write the 2nd field data address at the E point 40H unit.Among the figure F ' spot magnifier 4 read the 0BFH unit that address pointer points to the 2nd field picture data, and F point write address pointer points to the 0FFH unit, last address of the 2nd field data.Among the figure G ' spot magnifier 4 read the 0FFH unit, last address that address pointer points to the 2nd field picture data, and G point write address pointer has pointed to the 3FH unit of the 3rd field data.It should be noted that, read under the field sync signal VS_read effect unified, all control amplifiers read sequential and to read the address pointer sensing identical, but the clock periodicity that lags behind each control amplifier write address pointer is not quite similar.
Because top technical scheme adopts the single stores synchronized bulk-mode of high speed as frame buffer module, so the maximum field sync signal delay that allows can reach 16.66ms, promptly the field frequency cycle less than 60Hz gets final product.If the maximum field sync signal delay greater than a field frequency cycle, then can adopt two frames or multiframe memory bank mode.
This programme is cut apart a kind of field synchronization controlling mechanism of introducing in the amplifier at video, the field sync signal of primary field synchronizing signal and each master and slave amplifier generation is concentrated the access main amplifier, by main amplifier each field sync signal and primary field synchronizing signal are done time-delay relatively, automatically select the wherein the longest field sync signal of time-delay, after suitably postponing, generate the unified field sync signal of reading, and export to master and slave amplifier, guarantee the consistency that each amplifier image shows with this, respectively shown the inconsistent phenomenon that the subregion intersection occurs when effectively having avoided showing moving image.In addition, the frame buffer module that each amplifier adopts in this programme can use the single stores synchronized bulk-mode of high speed to realize, has further avoided because memory bank switches the image offset that causes.It allows the sequential of writing of each control amplifier can be asynchronous, design is comparatively simplified, and reduced design cost.At last, this digital video is cut apart amplifier field synchronization mechanism applicable to LED, LCD or CRT large-size screen monitors.
Claims (5)
1, a kind of video is cut apart amplifier, comprises main amplifier and some from amplifier, it is characterized in that, described master and slave amplifier all comprises frame buffer module, and described main amplifier also comprises,
Master's read-write control module is used for postponing the longest field sync signal generation unification based on described master and slave amplifier and reads field sync signal, controls described master and slave amplifier according to this and reads also image data processing synchronously.
2, video according to claim 1 is cut apart amplifier, it is characterized in that, described main read-write control module comprises:
Signal receiving module is used to receive the primary field synchronizing signal and from the field sync signal of described master and slave amplifier;
Computing module, the delay that is used to calculate the described relatively primary field synchronizing signal of described master and slave amplifier field sync signal;
Comparison module is used for determining that described master and slave amplifier field sync signal postpones the longest field sync signal;
The signal generation module after being used for field sync signal that described delay is the longest and postponing a time of delay section, generates and unifiedly reads field sync signal, mails to described from amplifier.
3, video according to claim 1 is cut apart amplifier, it is characterized in that, describedly comprises from the read-write control module from amplifier, is used to send its field sync signal, receives simultaneously from the unification of described main read-write control module and reads field sync signal.
4, video according to claim 2 is cut apart amplifier, it is characterized in that, described one time of delay section comprise two address locations clock cycle at interval at least.
5, video according to claim 1 is cut apart amplifier, it is characterized in that, described frame buffer module is a high speed single frames memory module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201453584U CN200990651Y (en) | 2006-12-28 | 2006-12-28 | Video frequency division amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201453584U CN200990651Y (en) | 2006-12-28 | 2006-12-28 | Video frequency division amplifier |
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| CN200990651Y true CN200990651Y (en) | 2007-12-12 |
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| CNU2006201453584U Expired - Fee Related CN200990651Y (en) | 2006-12-28 | 2006-12-28 | Video frequency division amplifier |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107948546A (en) * | 2017-11-09 | 2018-04-20 | 中国航空无线电电子研究所 | A kind of low latency video mix device |
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2006
- 2006-12-28 CN CNU2006201453584U patent/CN200990651Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107948546A (en) * | 2017-11-09 | 2018-04-20 | 中国航空无线电电子研究所 | A kind of low latency video mix device |
| CN107948546B (en) * | 2017-11-09 | 2020-07-31 | 中国航空无线电电子研究所 | Low-delay video mixing device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071212 Termination date: 20111228 |