CN1987993A

CN1987993A - Regulating method for monitor clock phase

Info

Publication number: CN1987993A
Application number: CN 200510121207
Authority: CN
Inventors: 赖万金
Original assignee: Innolux Shenzhen Co Ltd; Innolux Display Corp
Current assignee: Innolux Shenzhen Co Ltd; Innolux Corp
Priority date: 2005-12-23
Filing date: 2005-12-23
Publication date: 2007-06-27
Anticipated expiration: 2025-12-23
Also published as: CN100414603C

Abstract

This invention relates to an adjustment method for clock phase of a monitor including: setting an initial voltage value, when the input voltage of a level synchronous digital image signal is greater than said initial value, a proportion zoomer receives said digital image signal, setting several circulations and dividing each phase clock of the level synchronous scan lines into several sections and taking the input voltage value of the image signal corresponding to each mean point as the voltage start value of the next circulation, registering numbers of clock phases owned by the level synchronous scan lines and mean share points for altering phase numbers to determine the start value of the final voltage and compare the state of phase numbers of the level synchronous scan lines and position state of the register points to determine the starting value of the final voltage.

Description

The method of adjustment of monitor clock phase

[technical field]

The invention relates to a kind of method of adjustment of monitor clock phase.

[background technology]

Monitor (Monitor) is a kind of equipment of display image signals, and this picture signal is earlier by after digital sampling and/or the conversion (scaling), is received and is shown by the display card of monitor.The monitor technique functions comes from small-sized negative electrode iconoscope (Cathode Ray Tube, CRT), at present at liquid crystal indicator (Liquid Crystal Display, LCD) be widely used as digital display technique in, liquid crystal indicator is a kind of typical flat-panel display devices of making large-size monitor that is suitable for.The quality ordinary representation of monitor is on its resolution, as SVGA (800 * 600), XGA (1024 * 768) and SXGA (1280 * 1024).

Please refer to Fig. 1, is a kind of calcspar of monitor system of prior art.This monitor system 10 comprises a microcontroller 11, a phase-locked loop (Phase Locked Loop) 12, one analog to digital converter (Analog/Digital converter, A/D converter) 13, one proportional zoom device (Scaler) 14.This microcontroller 11 is determined image model and produces control signal corresponding according to this image model to handle to carry out appropriate signals according to level that receives and vertical synchronizing signal (Horizontal/Vertical synchronizing, H/V sync).This phase-locked loop 12 is to produce time clock according to the control signal that this microcontroller 11 transmits.This analog to digital converter 13 is according to the time clock sampling simulation picture signal (this picture signal is the R/G/B signal) of this phase-locked loop 12, and is converted to data image signal output.This proportional zoom device 14 uses the time clock of this phase-locked loop 12, and according to the control signal that this microcontroller 11 transmits, convergent-divergent comes from the data image signal of this analog to digital converter 13 to meet the resolution of liquid crystal display device module.This proportional zoom device 14 receives or the signal of output is the letter frame (Frame Unit) that transmits continuously one by one, and these letter frames constitute by the sweep trace of a rule, and every sweep trace is made of many pixels, and each pixel is a clock phase place.

The principle that this proportional zoom device 14 receives the data image signal of these analog to digital converter 13 outputs sees also Fig. 2, and Fig. 2 (A) is this data image signal input voltage waveform figure, and Fig. 2 (B) is the time clock oscillogram that this phase-locked loop 12 produces.Horizontal-drive signal with resolution XGA (1024 * 768) is an example, can produce 1024 time clock in this phase-locked loop 12 of a horizontal-drive signal cycle, therefore have 1024 pixels on this horizontal synchronization sweep trace, promptly have 1024 clock phases, wherein this data image signal input voltage is set to 0.7V usually.

See also Fig. 3, Fig. 3 (A) is data image signal input voltage waveform figure in the reality, Fig. 3 (B) is the synoptic diagram of the voltage initial value clock phase quantity that this horizontal synchronization sweep trace has when being b, and Fig. 3 (C) is the synoptic diagram of the voltage initial value clock phase quantity that this horizontal synchronization sweep trace has when being c.The data image signal input voltage has lag characteristic in the reality, usually in order to reduce the time delay of these proportional zoom device 14 reception data image signals, lower voltage initial value can be set, when input voltage during greater than this voltage initial value, this proportional zoom device 14 begins to receive data image signal.When the voltage initial value is b, have 1025 clock phase quantity on this horizontal synchronization sweep trace, shown in Fig. 3 (B); When the voltage initial value is c, have 1024 clock phase quantity on this horizontal synchronization sweep trace, shown in Fig. 3 (C).Therefore, when elected power taking pressed initial value incorrect, the lag characteristic of input voltage slightly changed, and the clock phase quantity that this horizontal synchronization sweep trace has will change, and makes the demonstration reliability decrease of monitor.

[summary of the invention]

In order to solve the not high problem of demonstration reliability of monitor in the prior art, be necessary to provide the method for adjustment that can improve the monitor clock phase that shows reliability.

A kind of method of adjustment of monitor clock phase, it may further comprise the steps:

Set an initial voltage initial value, when the input voltage of horizontal synchronization data image signal during greater than this initial initial value, the proportional zoom device begins to receive this horizontal synchronization data image signal;

Set some circulations, each phase clock of horizontal synchronization sweep trace be divided into some parts, write down the input voltage value that each equal portions is put pairing data image signal, and with the input voltage value of each equal portions point correspondence as next round-robin voltage initial value;

The recording clock number of phases, recording level synchronous scanning line has the quantity of clock phase;

The equal portions point that the recording clock number of phases changes has the quantity of clock phase based on the horizontal synchronization sweep trace, the equal portions point that recording level synchronous scanning line clock phase quantity changes;

Determine final voltage initial value, the input voltage value of comparing each measuring point correspondence is during as the voltage initial value, the situation of horizontal synchronization sweep trace clock phase quantity and the position situation of each measuring point, when slightly changing with the lag characteristic of input voltage, this horizontal synchronization sweep trace still has the equal portions of default clock phase quantity and puts pairing input voltage value as final voltage initial value.

Compared with prior art, in the method for adjustment of this monitor clock phase, the final voltage initial value of determining is even because of lag characteristic causes determining that voltage slightly changes and also can making the horizontal synchronization sweep trace have default clock phase quantity of input, therefore improve the demonstration reliability of monitor.

[description of drawings]

Fig. 1 is a kind of calcspar of monitor system of prior art.

Fig. 2 (A) is numerical digit picture signal input voltage waveform figure.

Fig. 2 (B) is the time clock oscillogram that the phase-locked loop produces.

Fig. 3 (A) is data image signal input voltage waveform figure in the reality.

Fig. 3 (B) is a voltage initial value when being b, the synoptic diagram of the clock phase quantity that this horizontal synchronization sweep trace has.

Fig. 3 (C) is a voltage initial value when being c, the synoptic diagram of the clock phase quantity that this horizontal synchronization sweep trace has.

Fig. 4 is the process flow diagram of the method for adjustment of monitor clock phase of the present invention.

[embodiment]

Please refer to Fig. 4, is the process flow diagram of the method for adjustment of monitor clock phase of the present invention.The method of adjustment 100 of this monitor clock phase may further comprise the steps:

Step 101 is set an initial voltage initial value, and this initial value can be far below 0.7V, and when the input voltage of horizontal synchronization data image signal during greater than this initial initial value, the proportional zoom device begins to receive this horizontal synchronization data image signal;

Step 102, set some circulations, horizontal-drive signal with resolution XGA (1024 * 768) is an example, each phase clock of horizontal synchronization sweep trace is divided into 64 parts, write down each equal portions and put the input voltage value of pairing data image signal, and the input voltage value that each equal portions point is corresponding is as next round-robin voltage initial value;

Step 103, the quantity of recording clock phase place has the quantity of clock phase on the recording level synchronous scanning line;

Step 104, the equal portions point that the quantity of recording clock phase place changes has the quantity of clock phase based on the horizontal synchronization sweep trace, the equal portions point that the quantity of recording level synchronous scanning line clock phase changes, and with this equal portions that are recorded point as measuring point;

Step 105, determine final voltage initial value, the input voltage value of comparing each measuring point correspondence is during as the voltage initial value, the situation of the clock phase quantity of horizontal synchronization sweep trace and the position situation of each measuring point, when slightly changing with the lag characteristic of input voltage, this horizontal synchronization sweep trace still has the pairing input voltage value of default clock phase quantity as final voltage initial value.

Compared with prior art, in the method for adjustment 100 of this monitor clock phase, determine a final voltage initial value, when causing input voltage to compare starting potential slightly to change because of lag characteristic, also can make the horizontal synchronization sweep trace have default clock phase quantity, therefore improve the demonstration reliability of monitor.

In this step 103, the distance that can open horizontal alignment function calculated level synchronous scanning line two ends has the quantity of clock phase with recording level synchronous scanning line; Simultaneously, add one in step 105 back and close the horizontal alignment functional steps.

Claims

1. the method for adjustment of a monitor clock phase, it may further comprise the steps:

The equal portions point that the recording clock number of phases changes has the quantity of clock phase based on the horizontal synchronization sweep trace, the equal portions point that recording level synchronous scanning line clock phase quantity changes, and this equal portions that are recorded point is as measuring point;

2. the method for adjustment of monitor clock phase as claimed in claim 1 is characterized in that: the step of recording clock number of phases is that the distance of opening horizontal alignment function calculated level synchronous scanning line two ends has the quantity of clock phase with recording level synchronous scanning line.

3. the method for adjustment of monitor clock phase as claimed in claim 2 is characterized in that: add one and close the horizontal alignment functional steps after the step of determining final voltage initial value.

4. the method for adjustment of monitor clock phase as claimed in claim 1, it is characterized in that: this data image signal is digital R/G/B signal.

5. the method for adjustment of monitor clock phase as claimed in claim 1, it is characterized in that: each phase clock is divided into 64 parts.