CN1979314A - Pixel structure - Google Patents
Pixel structure Download PDFInfo
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- CN1979314A CN1979314A CN 200510124256 CN200510124256A CN1979314A CN 1979314 A CN1979314 A CN 1979314A CN 200510124256 CN200510124256 CN 200510124256 CN 200510124256 A CN200510124256 A CN 200510124256A CN 1979314 A CN1979314 A CN 1979314A
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- dot structure
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Abstract
The invention is a pixel structure, comprising substrate, first metal layer, dielectric layer, semiconductor layer, second metal layer, patternized floating metal layer and pixel electrode, where the first metal layer is arranged on the substrate and comprises a grid and a scanning line connected with the grid; the dielectric layer is arranged on the substrate and covers the first metal layer; the semiconductor layer is arranged on the dielectric layer above the grid; the second metal layer comprises source/drain and data line, where the source/drain is arranged on the semiconductor layer and overlaps the grid; the data line is connected with the source and overlaps the scanning line; the pixel electrode is connected with the drain; the patternized floating metal layer is arranged between the dielectric layer and the semiconductor layer and under the source/drain, where part of the patternized floating metal layer is in a region above the grid and incompletely covers the region.
Description
Technical field
The present invention relates to the dot structure (pixel structure) of a kind of thin-film transistor array base-plate (TFT array substrate), and particularly relate to a kind of dot structure that reduces the stray capacitance (parasitic capacitor) between the first metal layer and second metal level.
Background technology
At the quick progress of multimedia society, be indebted to the tremendous progress of semiconductor element or display device mostly.With regard to display, (cathode ray tube CRT) because of having excellent display quality and its economy, monopolizes monitor market in recent years to cathode-ray tube (CRT) always.Yet, operate the environment of a plurality of terminating machine/display equipments on the table for the individual, or with the incision of the viewpoint of environmental protection, if predicted with the trend of saving the energy, cathode-ray tube (CRT) is because of still existing a lot of problems in space utilization and the energy resource consumption, and can't effectively provide solution for the demand of light, thin, short, little and low consumpting power.Therefore, have that high image quality, space utilization efficient are good, (thin film transistor liquid crystal display TFT-LCD) becomes the main flow in market to the Thin Film Transistor-LCD of low consumpting power, advantageous characteristic such as radiationless gradually.
Thin Film Transistor-LCD mainly is made of thin-film transistor array base-plate, colorful filter array substrate and liquid crystal layer, and wherein thin-film transistor array base-plate is formed by the thin film transistor (TFT) of a plurality of arrayed and with the pixel electrode (pixel electrode) of the corresponding setting of each thin film transistor (TFT).And thin film transistor (TFT) is intended for the on-off element of liquid crystal display.In addition, in order to control other pixel, usually can be by scan wiring (scan line) and data wiring (data line) choosing specific pixel, and by suitable operating voltage is provided, to show the video data of this pixel of correspondence.
Fig. 1 is a kind of vertical view of dot structure of known thin-film transistor array base-plate, and Fig. 2 is the cross section view of I-I ' line among Fig. 1.Please refer to Fig. 1 and Fig. 2, the dot structure 100 of known thin-film transistor array base-plate comprises substrate 110, the first metal layer 120, dielectric layer 130, semiconductor layer 140, second metal level 150, protective seam 160 and pixel electrode 170.Wherein, the first metal layer 120 is arranged on the substrate 110, and the first metal layer 120 comprises grid 122 and the scan wiring 124 that is electrically connected with grid 122.Dielectric layer 130 is arranged on the substrate 110, and covers the first metal layer 120, and semiconductor layer 140 is arranged on the dielectric layer 130 of grid 122 tops.In addition, second metal level 150 comprises source/drain 152/154 and data wiring 156, and source/drain 152/154 is arranged on the semiconductor layer 140, and overlaps with grid 122.Data wiring 156 is electrically connected with source electrode 152, and overlaps with scan wiring 124.In addition, protective seam 160 is arranged on the substrate 110, and covers the first metal layer 120 and second metal level 150.Protective seam 160 has opening 162, and exposing drain electrode 154, and pixel electrode 170 opening 162 by protective seam 160 154 is electrically connected with draining.
In the known dot structure 100, overlap between the first metal layer 120 and second metal level 150, therefore the overlapping at the first metal layer 120 and second metal level 150 can produce stray capacitance.In other words, all can there be stray capacitance between grid 122 and the source/drain 152/154 and between scan wiring 124 and the data wiring 156, and these stray capacitances also can influence pixel voltage except meeting causes distorted signals, and then reduce the display quality of LCD.
Summary of the invention
Purpose of the present invention just provides a kind of dot structure, with the parasitic capacitance effect between the reduction the first metal layer and second metal level, and then the display quality of raising LCD.
Based on above-mentioned and other purposes, the present invention proposes a kind of dot structure, and it comprises substrate, the first metal layer, dielectric layer, semiconductor layer, second metal level, the unsteady metal level of patterning and pixel electrode.Wherein, the first metal layer is arranged on the substrate, and the first metal layer comprises grid and the scan wiring that is electrically connected with grid.Dielectric layer is arranged on the substrate, and covers the first metal layer, and semiconductor layer is arranged on the dielectric layer of grid top.In addition, second metal level comprises source/drain and data wiring, and source/drain is arranged on the semiconductor layer, and overlaps with grid.Data wiring is electrically connected with source electrode, and overlaps with scan wiring.Pixel electrode is electrically connected with drain electrode.In addition, the unsteady metal level of patterning is arranged between dielectric layer and the semiconductor layer, and is positioned at the source/drain below, and wherein partially patterned unsteady metal level is positioned at the zone of grid top, and the zone of complete cover gate top.
Above-mentioned dot structure for example also comprises bed course, and it is arranged at the dielectric layer top between scan wiring and the data wiring, and the patterning metal level that floats also comprises and being arranged between bed course and the dielectric layer.In addition, bed course and semiconductor layer for example are to belong to same rete.
In the above-mentioned dot structure, the first metal layer for example also comprises shared distribution, and this shared distribution is parallel to scan wiring in fact, and overlaps with data wiring.In addition, above-mentioned dot structure for example also comprises bed course, it is arranged at dielectric layer top and the top of the dielectric layer between shared distribution and the data wiring between scan wiring and the data wiring, and the patterning metal level that floats also comprises and being arranged between bed course and the dielectric layer.In addition, bed course and semiconductor layer for example are to belong to same rete.
In the above-mentioned dot structure, the pattern of the unsteady metal level of patterning for example is identical with the pattern of second metal level.In addition, dot structure for example also comprises bed course, and it is arranged at patterning and floats between metal level and the data wiring.In addition, bed course and semiconductor layer for example belong to same rete.Wherein, the material of the unsteady metal level of patterning for example is an opaque metal.
In the above-mentioned dot structure, the material of the unsteady metal level of patterning for example is a transparent metal.
In the above-mentioned dot structure, the material of the unsteady metal level of patterning for example is an opaque metal.
In the above-mentioned dot structure, the unsteady metal layer thickness of patterning for example is between 100 dusts (angstrom)～1800 dust.
In the above-mentioned dot structure, the unsteady metal layer thickness of patterning for example is between 500 dusts～1500 dusts.
In the above-mentioned dot structure, semiconductor layer for example comprises channel layer and is arranged at ohmic contact layer on the channel layer.
Above-mentioned dot structure for example also comprises protective seam, and it is arranged on the substrate, and covers the first metal layer and second metal level.In addition, protective seam for example has opening, exposes drain electrode, and pixel electrode is electrically connected with drain electrode by opening.
The present invention is provided with the unsteady metal level of patterning between the first metal layer and second metal level, with float between the metal level in the first metal layer and patterning and second metal level and the unsteady metal level of patterning between produce stray capacitance respectively, and this two stray capacitance is connected mutually.Therefore, the present invention can reduce the parasitic capacitance effect between the first metal layer and second metal level, and then improves the display quality of LCD.
State with other purposes, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is a kind of vertical view of dot structure of known thin-film transistor array base-plate.
Fig. 2 is the cross section view of I-I ' line among Fig. 1.
Fig. 3 is the vertical view of the dot structure of first embodiment of the invention.
Fig. 4 A is the cross section view of II-II ' line among Fig. 3.
Fig. 4 B is the cross section view of III-III ' line among Fig. 3.
Fig. 5 is the vertical view of the another kind of dot structure of first embodiment of the invention.
Fig. 6 is the cross section view of IV-IV ' line among Fig. 5.
Fig. 7 is the vertical view of the dot structure of second embodiment of the invention.
Fig. 8 is the cross section view of V-V ' line among Fig. 7.
The main element description of symbols
100,200,200a, 200b: dot structure
110,210: substrate
120,220: the first metal layer
122,222: grid
124,224: scan wiring
130,230: dielectric layer
140,240,240a: semiconductor layer
150,250: the second metal levels
152,252: source electrode
154,254: drain electrode
156,256: data wiring
160,280: protective seam
162,282: opening
170,270: pixel electrode
226: shared distribution
245,245a: bed course
260: the patterning metal level that floats
Embodiment
First embodiment
Fig. 3 is the vertical view of the dot structure of first embodiment of the invention, and Fig. 4 A is the cross section view of II-II ' line among Fig. 3.Please refer to Fig. 3 and Fig. 4 A, the dot structure 200 of present embodiment comprises substrate 210, the first metal layer 220, dielectric layer 230, semiconductor layer 240, second metal level 250, the unsteady metal level 260 of patterning and pixel electrode 270.Wherein, the first metal layer 220 is arranged on the substrate 210, and the first metal layer 220 comprises grid 222 and the scan wiring 224 that is electrically connected with grid 222.Dielectric layer 230 is arranged on the substrate 210, and covers the first metal layer 230, and semiconductor layer 240 is arranged on the dielectric layer 230 of grid 222 tops.In addition, second metal level 250 comprises source/drain 252/254 and data wiring 256, and source/drain 252/254 is arranged on the semiconductor layer 240, and overlaps with grid 222.Data wiring 256 is electrically connected with source electrode 252, and overlaps with scan wiring 224.Pixel electrode 270 is electrically connected with drain electrode 254.In addition, the unsteady metal level 260 of patterning is arranged between dielectric layer 230 and the semiconductor layer 240, and be positioned at source/drain 252/254 below, wherein partially patterned unsteady metal level 260 is positioned at the zone of grid 222 tops, and the complete zone of cover gate 222 tops not.
Above-mentioned dot structure 200 for example also comprises protective seam 280, and it is arranged on the substrate 210, and covers the first metal layer 220 and second metal level 250.This protective seam 280 for example has opening 282, and this opening 282 exposes drain electrode 254, and pixel electrode 270 is electrically connected with drain electrode 254 by opening 282.In addition, the material of pixel electrode 270 for example be indium tin oxide (Indium Tin Oxide, ITO), indium-zinc oxide (Indium Zinc Oxide, IZO) or other transparent conductive materials.Semiconductor layer 240 for example comprises channel layer and is arranged at ohmic contact layer on the channel layer.In addition, the material of the unsteady metal level 260 of patterning for example is transparent metal (as ITO, IZO etc.) or opaque metal (as aluminium, nickel, chromium etc.), and its thickness for example is between 100 dusts～1800 dusts, more preferably between 500 dusts～1500 dusts.
Owing to can have stray capacitance between grid 222 and the source/drain 252/254, and these stray capacitances not only can cause distorted signals, also can influence pixel voltage, and then reduce the display quality of LCD.In view of this, present embodiment is in the unsteady metal level 260 of patterning is set between grid 222 and the source electrode 252 and between grid 222 and the drain electrode 254, produce stray capacitance so that patterning floats between metal level 260 and the grid 222 and patterning floats respectively between metal level 260 and the source electrode 252, and this two stray capacitance is connected mutually.Simultaneously, patterning floats between metal level 260 and the grid 222 and patterning floats also can produce stray capacitance respectively between metal level 260 and the drain electrode 254, and the also series connection mutually of this two stray capacitance.
Hold above-mentioned because the capacitance after two capacitances in series is less than this two electric capacity other capacitance, so the dot structure 200 of present embodiment can improve the parasitic capacitance effect between the grid and source/drain in the known technology.Thereby, not only can improve the display quality of LCD, also can improve the nargin of display panel design.
Fig. 4 B is the cross section view of III-III ' line among Fig. 3.Please refer to Fig. 3 and Fig. 4 B, the above-mentioned notion of utilizing capacitances in series also can be widely used in the overlapping of the first metal layer 220 and second metal level 250 except can be applicable between grid 222 and the source/drain 252/254.In other words, the unsteady metal level 260 of patterning also can be arranged at the overlapping of scan wiring 224 and data wiring 256.In more detail, dot structure 200 for example also comprises bed course 245, and it is arranged at dielectric layer 230 tops between scan wiring 224 and the data wiring 256, and the patterning metal level 260 that floats also comprises and being arranged between bed course 245 and the dielectric layer 230.Thereby the stray capacitance influence that transmission is caused to signal between scan wiring 224 and the data wiring 256 is reduced, with the display quality of further raising LCD.In addition, in the present embodiment, bed course 245 for example is to belong to same rete with semiconductor layer 240.
Fig. 5 is the vertical view of the another kind of dot structure of first embodiment of the invention, and Fig. 6 is the cross section view of IV-IV ' line among Fig. 5.Please refer to Fig. 5 and Fig. 6, the dot structure 200a of present embodiment is similar to dot structure 200, difference is in the first metal layer 220 of dot structure 200a and also comprises shared distribution 226, and this shared distribution 226 is parallel to scan wiring 224 in fact, and overlaps with data wiring 256.In addition, in order to reduce the stray capacitance influence that transmission is caused to signal between shared distribution 226 and the data wiring 256.In dot structure 200a, bed course 245 also comprises dielectric layer 230 tops that are arranged between shared distribution 226 and the data wiring 256, and the patterning metal level 260 that floats also comprises and being arranged between bed course 245 and the dielectric layer 230.
Second embodiment
Fig. 7 is the vertical view of the dot structure of second embodiment of the invention, and Fig. 8 is the cross section view of V-V ' line among Fig. 7.Please refer to Fig. 7 and Fig. 8, in order to save the photo etched mask cost, employed photo etched mask employed photo etched mask when forming second metal level 250 is identical when forming patterning in the present embodiment and floating metal level 260, so the pattern of the unsteady metal level 260 of patterning is identical with the pattern of second metal level 250.In addition, the pattern of metal level 260 is identical with the pattern of second metal level 250 because patterning floats, so compare with the semiconductor layer 240 of first embodiment, the semiconductor layer 240a of present embodiment need extend the unsteady metal level 260 of patterning that covering is positioned at drain electrode 254 belows, is electrically connected with drain electrode 254 to prevent the unsteady metal level 260 of patterning.In addition, the bed course 245a of present embodiment need cover the unsteady metal level 260 of the patterning that is positioned at data wiring 256 belows, is electrically connected with data wiring 256 to prevent the unsteady metal level 260 of patterning.
Hold above-mentioned, when patterning floats the material selection transparent metal of metal level 260, the semiconductor layer 240 that is positioned at drain electrode 254 belows has most zone because of there not being covering of grid 222, and can directly be subjected to light (as the light that backlight sent of LCD) irradiation and deterioration, cause the phenomenon of light leakage current.Therefore, the unsteady metal level 260 selected materials of the patterning of present embodiment are opaque metal, with metal level 260 shield lights of floating by patterning, make the semiconductor layer 240 that is positioned at drain electrode 254 belows be difficult for deterioration, and then improve the phenomenon of light leakage current, improve the display quality of LCD.
In sum, dot structure of the present invention has following advantage at least:
1. the present invention utilizes capacitance after two capacitances in series less than the principle of this two electric capacity capacitance separately, the patterning metal level that floats is set, to produce two stray capacitances of mutual series connection between the first metal layer and second metal level.So the present invention can reduce the parasitic capacitance effect between the first metal layer and second metal level, so not only can improve the display quality of LCD, also can improve the nargin of display panel design.
2. in a second embodiment, use identical photo etched mask to form the unsteady metal level of patterning and second metal level, can save the cost of photo etched mask, therefore can under the prerequisite that reduces the parasitic capacitance effect between first and second metal level, reduce production costs.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and change, so the present invention's protection domain is as the criterion when looking the claim person of defining.
Claims (17)
1. dot structure is characterized in that comprising:
Substrate;
The first metal layer is arranged on this substrate, and this first metal layer comprises:
Grid;
Scan wiring is electrically connected with this grid;
Dielectric layer is arranged on this substrate, and covers this first metal layer;
Semiconductor layer is arranged on this dielectric layer of this grid top;
Second metal level comprises:
Source/drain is arranged on this semiconductor layer, and this source/drain and this grid overlap;
Data wiring is electrically connected with this source electrode, and wherein this scan wiring and this data wiring overlap;
The patterning metal level that floats is arranged between this dielectric layer and this semiconductor layer, and is positioned at this source/drain below, and wherein this patterning of part metal level that floats is positioned at the zone of this grid top, and does not cover the zone of this grid top fully; And
Pixel electrode is electrically connected with this drain electrode.
2. dot structure according to claim 1 is characterized in that also comprising bed course, is arranged at this dielectric layer top between this scan wiring and this data wiring, and this patterning metal level that floats also comprises and being arranged between this bed course and this dielectric layer.
3. dot structure according to claim 2 is characterized in that this bed course and this semiconductor layer belong to same rete.
4. dot structure according to claim 1 is characterized in that this first metal layer also comprises shared distribution, is parallel to this scan wiring in fact, and this shared distribution and this data wiring overlap.
5. dot structure according to claim 4, it is characterized in that also comprising bed course, be arranged at above this dielectric layer top and this dielectric layer between this shared distribution and this data wiring between this scan wiring and this data wiring, and the unsteady metal level of this patterning also comprises and being arranged between this bed course and this dielectric layer.
6. dot structure according to claim 5 is characterized in that this bed course and this semiconductor layer belong to same rete.
7. dot structure according to claim 1 is characterized in that the pattern of the unsteady metal level of this patterning is identical with the pattern of this second metal level.
8. dot structure according to claim 7 is characterized in that also comprising bed course, is arranged at this patterning and floats between metal level and this data wiring.
9. dot structure according to claim 8 is characterized in that this bed course and this semiconductor layer belong to same rete.
10. dot structure according to claim 7 is characterized in that the material of the unsteady metal level of this patterning comprises opaque metal.
11. dot structure according to claim 1 is characterized in that the material of the unsteady metal level of this patterning comprises transparent metal.
12. dot structure according to claim 1 is characterized in that the material of the unsteady metal level of this patterning comprises opaque metal.
13. dot structure according to claim 1 is characterized in that this patterning floats metal layer thickness between 100 dusts～1800 dusts.
14. dot structure according to claim 1 is characterized in that this patterning floats metal layer thickness between 500 dusts～1500 dusts.
15. dot structure according to claim 1 is characterized in that this semiconductor layer comprises:
Channel layer; And
Ohmic contact layer is arranged on this channel layer.
16. dot structure according to claim 1 is characterized in that also comprising protective seam, is arranged on this substrate, and covers this first metal layer and this second metal level.
17. dot structure according to claim 1 is characterized in that this protective seam has opening, exposes this drain electrode, and this pixel electrode is electrically connected with this drain electrode by this opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101242564A CN100533236C (en) | 2005-11-29 | 2005-11-29 | Pixel structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101242564A CN100533236C (en) | 2005-11-29 | 2005-11-29 | Pixel structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1979314A true CN1979314A (en) | 2007-06-13 |
| CN100533236C CN100533236C (en) | 2009-08-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101242564A Active CN100533236C (en) | 2005-11-29 | 2005-11-29 | Pixel structure |
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| Country | Link |
|---|---|
| CN (1) | CN100533236C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015096309A1 (en) * | 2013-12-26 | 2015-07-02 | 京东方科技集团股份有限公司 | Thin-film transistor, manufacturing method therefor, array substrate, and display device |
| CN109270733A (en) * | 2018-11-13 | 2019-01-25 | 成都中电熊猫显示科技有限公司 | A kind of display panel, array substrate and display device |
| CN109346464A (en) * | 2015-10-23 | 2019-02-15 | 稳懋半导体股份有限公司 | The circuit arrangement method of compound semiconductor integrated circuit |
| WO2019052265A1 (en) * | 2017-09-15 | 2019-03-21 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method therefor, and electronic apparatus |
| WO2020037717A1 (en) * | 2018-08-21 | 2020-02-27 | 武汉华星光电半导体显示技术有限公司 | Array substrate |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105097898B (en) * | 2015-06-02 | 2019-12-31 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display device |
| CN108258060B (en) * | 2018-01-16 | 2022-02-08 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method and display device |
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2005
- 2005-11-29 CN CNB2005101242564A patent/CN100533236C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015096309A1 (en) * | 2013-12-26 | 2015-07-02 | 京东方科技集团股份有限公司 | Thin-film transistor, manufacturing method therefor, array substrate, and display device |
| US9502576B2 (en) | 2013-12-26 | 2016-11-22 | Boe Technology Group Co., Ltd. | Thin film transistor and method for manufacturing the same, array substrate, display device |
| CN109346464A (en) * | 2015-10-23 | 2019-02-15 | 稳懋半导体股份有限公司 | The circuit arrangement method of compound semiconductor integrated circuit |
| CN109346464B (en) * | 2015-10-23 | 2023-11-28 | 稳懋半导体股份有限公司 | Circuit layout method of compound semiconductor integrated circuit |
| WO2019052265A1 (en) * | 2017-09-15 | 2019-03-21 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method therefor, and electronic apparatus |
| WO2020037717A1 (en) * | 2018-08-21 | 2020-02-27 | 武汉华星光电半导体显示技术有限公司 | Array substrate |
| CN109270733A (en) * | 2018-11-13 | 2019-01-25 | 成都中电熊猫显示科技有限公司 | A kind of display panel, array substrate and display device |
| CN109270733B (en) * | 2018-11-13 | 2022-11-08 | 成都中电熊猫显示科技有限公司 | Display panel, array substrate and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100533236C (en) | 2009-08-26 |
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Effective date of registration: 20160816 Address after: The Marshall Islands Majuro Adger Island Road trust company Tektronix Tektronix Adger areas MH96960 Patentee after: Hao Chi intangible asset management Investment Limited Address before: Taiwan, Taipei, China Zhongshan North Road three paragraph twenty-two Patentee before: Chunghwa Picture Tubes Ltd. |
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Effective date of registration: 20161205 Address after: 430070 Hubei City, Wuhan Province, East Lake Development Zone, high tech Avenue, No. 666 biological city C5 building, Patentee after: Wuhan Hua Xing photoelectricity technology corporation, Ltd. Address before: The Marshall Islands Majuro Adger Island Road trust company Tektronix Tektronix Adger areas MH96960 Patentee before: Hao Chi intangible asset management Investment Limited |