CN1971529A - Device and method to regulate automatically data sampling dot of output interface of testing data - Google Patents
Device and method to regulate automatically data sampling dot of output interface of testing data Download PDFInfo
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Abstract
The invention relates to a device of automatic adjusting data sampling point of data-out port, it includes: scanning element which is used to scan the scanning chain circuit with test data, and judge whether the sampling point is reliable and output the test successful information when the sampling point is reliable; adjusting unit which is used to set the initial point of scanning unit and make the sampling point postpone for predetermined time when the sampling point is unreliable; the first judging unit which is used to judge whether the time value of sampling point is lower than lower limit, send said sampling point to scanning unit when the time value of sampling point is not lower than lower limit, send failure test information when the time value of sampling point is lower than lower limit. The invention also provides a corresponding method. The invention avoids the manual intervention in cause of adjusting data sampling point of data-out port and increase the application efficiency.
Description
Technical field
The present invention relates to field tests, or rather, relate to a kind of device and method of automatic adjustment test data output port data sampled point.
Background technology
Boundary scan technique has been reformed the test mode of device and peripheral circuit thereof by insert controllability and the observability that boundary scan cell improves device between device input and output pin and kernel circuitry.Its proposition be for solve the problem of interconnecting test on the circuit board, developed into afterwards be applied to logic chip plate programming and FLASH in multiple occasions such as plate programmings.At present, most chips are all supported boundary scan testing.
For ease of narration, relevant abbreviation of the boundary scan relevant with the present invention and term are listed below:
JTAG:Joint Test Action Group, JTAG;
BS:Boundary Scan, boundary scan;
BSC:Boundary Scan Cell, boundary scan cell;
TCK:Test ClocK, test clock;
TAP:Test Access Port, test access port;
TDI:Test Data Input, the test data input;
TDO:Test Data Output, test data output;
TMS:Test Mode Select, test pattern is selected;
TRST:Test Reset, test reset;
BSDL:Boundary-Scan Description Language, Boundary Sweep Description Language.
As shown in Figure 1, a boundary scan and test system is made up of computing machine 11, Boundary Scan Controller 12 and circuit-under-test plate 13 3 parts usually.Wherein computing machine 11 can be personal computer, portable machine, workstation etc.Boundary Scan Controller 12 is communicated by letter with computing machine 11 by interfaces such as PCI, ISA, USB, and the data conversion that computing machine 11 is sent is the required data layout of boundary scan, and produces tck signal; Simultaneously, Boundary Scan Controller 12 links to each other with circuit-under-test plate 13 by test access port (TAP) and carries out the relevant data transmission of boundary scan testing, and data packets for transmission is drawn together test pattern and selected (TMS), test clock (TCK), test data input (TDI), test reset (TRST), test data output (TDO) data etc.
In boundary scan and test system, when a plurality of boundary scanning chips are tested, usually they are linked to be a boundary scan chain, as shown in Figure 2.Wherein the data of test and excitation are by the input of TDI port, and the data pass test data output port of test response reclaims.Since test signal from the output terminal of circuit-under-test plate 13 to there being bigger transmission delay the Boundary Scan Controller 12, therefore Boundary Scan Controller 12 will be carried out suitable time-delay when the data that reclaim are sampled, to obtain the test data output port data synchronous sampling point of corresponding test data input.In general test controller postpones the TCK periodic sampling at least half, the test data output port data sequential of this moment as shown in Figure 3, Boundary Scan Controller 12 begins sampling at the negative edge of first clock period.
But when the test data output port of last device on the Board Under Test was far away to the transmission range between the Boundary Scan Controller 12, transmission delay will increase.If in above-mentioned transmission link, have chip for driving, also can further produce delay.In this case, continue to use half TCK periodic sampling of delay will cause the sampled data mistake.For avoiding mistake, sampled point should be adjusted, postpone the corresponding time backward.Fig. 4 and Fig. 5 are respectively the test data output port data when being delayed half period and a semiperiod, for guarantee correctly to adopt the required test data output port data sampling point position of output data.By Fig. 4 and Fig. 5 as seen, if sampled point is selected mistake, can't obtain correct test data output port data.
Above-mentioned Fig. 3, Fig. 4, Fig. 5 are to be the situation of TCK at sampling clock, also can utilize other clock signal to sample in the practical application, and sampling clock and test clock TCK are the relation of frequency multiplication as long as make.The frequency of sampling clock is high more, and the adjustment of sampled point is just accurate more.
The adjustment of test data output port data sampled point is at present all manually finished, process is generally: the sampled point that will postpone half TCK cycle is as initial sampled point, just manually test data output port data synchronous sampling point is postponed certain hour backward when finding test or program fail, failure postpones again again, till success.The shortcoming of this manual intervention method of prior art is conspicuous: inefficiency, use cost height, be unfavorable for the extensive realization of test automatically.
Summary of the invention
For avoiding the manual intervention in the boundary scan testing process, raise the efficiency, reduce test manpower and time cost, realize test automatically, the embodiment of the invention has creatively proposed a kind of device of automatic adjustment test data output port data sampled point, includes:
Scanning element is used for the use test data scan chain circuit is scanned, and judges according to scanning result whether sampled point is reliable, and successful information is tested in output when sampled point is reliable;
Adjustment unit is used to be provided with the initial sampled point of scanning element, and makes set sampled point delay scheduled time when scanning element determines that sampled point is unreliable;
First judging unit, whether the sampled point time value that is used to judge described adjustment unit setting is lower than predetermined lower limit and when determining that the sampled point time value is not less than predetermined lower limit the sampled point of described setting is sent to scanning element, and the sampled point time value after determining delay scheduled time is lower than under the predetermined sampled point in limited time the information of output test crash.
Embodiments of the invention also provide a kind of method of automatic adjustment test data output port data sampled point, may further comprise the steps:
(a) sampled point is set to test data output synchronous sampling point;
(b) to tested link input test data, carry out test operation and whether reliable at the current sampling point current sampling point that judges, if current sampling point is reliable, execution in step (c) then; If current sampling point is unreliable, then execution in step (d);
(c) output test success message;
(d) make the current sampling point delay scheduled time, and judge whether the current sampling point behind the delay scheduled time is lower than predetermined lower limit, if current sampling point is lower than then execution in step (e) of lower limit; If current sampling point is not less than lower limit, execution in step (b);
(e) output test crash message.
By using this method, avoided the manual intervention in the test data output port data synchronous sampling point adjustment process, improved application efficiency, increased the automaticity of chip testing; Can enhance productivity aborning, reduce the time cost of human input and manual intervention.
Description of drawings
Embodiments of the present invention is further illustrated below in conjunction with accompanying drawing, in the accompanying drawing:
Fig. 1 is that the existing boundary scan test system constitutes synoptic diagram;
Fig. 2 is an existing boundary scan link synoptic diagram of being made up of three each and every one boundary scanning chips;
Fig. 3 is the synoptic diagram of link test data-out port data in the TCK of first clock period negative edge sample graph 2;
Fig. 4 is the synoptic diagram of link test data-out port data in the TCK of second clock period rising edge sample graph 2;
Fig. 5 is the synoptic diagram of link test data-out port data in the TCK negative edge sample graph 2 of the 3rd clock period;
Fig. 6 is existing boundary scanning chip structural representation.
Fig. 7 is the structured flowchart that the present invention adjusts the embodiment of test data output port data sampled point device automatically;
Fig. 8 is the structured flowchart of first embodiment of scanning element among Fig. 7;
Fig. 9 is the structured flowchart of second embodiment of scanning element among Fig. 7;
Figure 10 is the structured flowchart of the 3rd embodiment of scanning element among Fig. 7;
Figure 11 is the process flow diagram that the present invention adjusts first embodiment of test data output port data sampled point method automatically.
Embodiment
The scan chain circuit that the boundary scanning chip that relates in the test constitutes as shown in Figure 2, Fig. 2 has only three chips, the scan chain circuit that one or more chips are arranged similarly, the test data output signal of each chip is as the test data input (if next chip exists) of adjacent next chip in the link.Wherein the structural representation of each chip as shown in Figure 6.
From the chip structure of Fig. 6 as can be seen, test data can have two paths from being input to output:
One paths is through order register, i.e. test data input port → order register → test data output port, and the link that each chip all adopts this path to constitute is called the order register link;
Another paths is through boundary scan cell (BSC), promptly test data input port → BSC → ... the link that → BSC → test data output port, each chip all adopt this path to constitute is called the boundary scan cell link.
The length of this two paths just length of order register and the number of BSC can be obtained from BSDL (Boundary-Scan Description Language, Boundary Sweep Description Language) file automatically.
As shown in Figure 7, be the structured flowchart that the present invention adjusts the device embodiment of test data output port data sampled point automatically.In the present embodiment, the device of automatically adjusting test test data output sampled point includes: scanning element 73, unit 74, first judging unit 76 are set.
In the present embodiment, scanning element 73 is connected to test access port (Test Access Port on the scan chain circuit by a coupling arrangement, TAP), thereby test data and TCK frequency are input to the test data input port and the test clock of scan chain circuit, and pass through this test data output port acquisition output data.In actual applications, coupling arrangement can be jtag controller.
The amplitude of 74 pairs of adjustment units sampled point each time delay, promptly above-mentioned schedule time value can be regulated according to the needs of test, for example postpones half TCK cycle or 1/4 TCK cycle at every turn, also can be any corresponding numerical value.Usually reliability requirement is high more, and the amplitude of each time delay is more little.
As shown in Figure 8, be the detailed structure synoptic diagram of scanning element 73 first embodiment among Fig. 7.In the present embodiment, scanning element 73 is used for the scan instruction chain of registers, and it specifically comprises first command unit 81, second judging unit 82 and the 3rd judging unit 83.
First command unit 81 is used for the scan instruction chain of registers, just with data by test data input port input, via order register, and export by the test data output port.Second judging unit 82 is used under the sampled point that adjustment unit 74 is provided with, output data according to the test data output port, judge whether current sampling point is reliable, whether the data of promptly judging test data output port output are identical with the test data of input, and (in the present embodiment, the initial sampled point of the 4th judging unit 92 is T
s), if inequality, then send signal to adjustment unit 74, make the current sampling point delay scheduled time by adjustment unit 74, and making first command unit 81 continue the scan instruction chain of registers, second judging unit 82 judges whether the sampled point behind the delay scheduled time is reliable; Then further judge whether the number of times that first command unit 81 scans reaches pre-determined number under current sampling point as if identical by the 3rd judging unit 83, if reach then output test successful information, otherwise whether reliably continue at the current sampling point current sampling point that judges by second judging unit 82.
As shown in Figure 9, be the detailed structure synoptic diagram of scanning element 73 second embodiment among Fig. 7.In the present embodiment, scanning element 73 specifically comprises first data cell 91, the 4th judging unit 92 and the 5th judging unit 93.
As shown in figure 10, be the detailed structure synoptic diagram of scanning element 73 the 3rd embodiment among Fig. 7.In the present embodiment, scanning element 73 is used for scan instruction chain of registers and boundary scan cell link, and it specifically comprises second command unit 101, the 6th judging unit 102, the 7th judging unit 103, second data cell 105, the 8th judging unit 104 and the 9th judging unit 106.
Similarly, the number of times that scans under same sampled point in the foregoing description can be selected the requirement and the test duration of reliability according to system.
As shown in Figure 7, be the process flow diagram that the present invention adjusts first embodiment of testing clock frequency method automatically.In the present embodiment, unite and use instruction scan and data scanning whether sampled point is reliably judged, specifically may further comprise the steps:
Step 701 is obtained the total command link length of boundary scan link and total boundary scan cell length.In this step, can realize by the BSDL file of each boundary scanning chip or the file of each boundary scanning chip performance parameter of similar description on the analysis boundary scan link, wherein total command link length is the summation of length of the order register of each boundary scanning chip, and total boundary scan cell length is the summation of the BSC number of each boundary scanning chip.
Step 702, sampled point are set to half clock period Ts of test data input port data delay.
Step 703, the use test data are carried out m instruction scan under the sampled point that is provided with, and judge whether current sampling point is reliable, whether the data of promptly judging the output of test data output interface are consistent with the data of test data input interface input, wherein Shu Ru scanning can be specific data such as 0x55AA etc. with data, also can be random data.Judge that current sampling point is unreliable, execution in step 707 if arbitrary result is inconsistent; If m result be unanimity then execution in step 704.
M time above-mentioned instruction scan can realize by following steps:
(b11) test data is imported from the test data input interface, exported from the test data output interface through the order register link;
(b12) whether consistent in the current sampling point described output data that judges with described input data, if output data is inconsistent with the input data, determine that then current sampling point is unreliable, execution in step 707; Otherwise execution in step (b13);
(b13) number of times with use test data scanning under the current sampling point adds 1, and judges whether the number of times of scanning under the current sampling point reaches m time, if the scanning times under the current sampling point reaches m time, determines that then current sampling point is reliable, execution in step 704; Otherwise execution in step (b11).
Step 704, the use test data are carried out the scan operation of n secondary data under current sampling point, and to from the data of test data output interface output with judge from whether test data input interface data consistent, wherein Shu Ru test data can be specific data such as 0x55AA etc., also can be random data.If n result be unanimity then execution in step 705; If arbitrary time the result is inconsistent, determine that then current sampling point is unreliable, execution in step 707.
Above-mentioned n secondary data scanning can realize by following steps:
(b21) test data is imported from the test data input interface, exported from the test data output interface through the boundary scan cell link;
(b22) whether consistent in the current sampling point described output data that judges with described input data, if output data is inconsistent with the input data, determine that then current sampling point is unreliable, execution in step 707; Otherwise execution in step (b23);
(b23) number of times with use test data scanning under the current sampling point adds 1, and judges whether the number of times of scanning reaches n time, if the scanning times under the current sampling point reaches n time, determines that then current sampling point is reliable, execution in step 705; Otherwise execution in step (b21).
Step 705 determines that current sampling point is reliable, and report is adjusted successfully;
Step 707 makes the current sampling point delay scheduled time, and execution in step 708 then;
Step 708 judges whether the sampled point behind the delay scheduled time has been lower than predetermined lower limit, does not have reliable sampled point if be lower than then illustrate in setting range, and the report failure also finishes adjustment process; The execution in step 703 if sampled point behind the delay scheduled time is not less than predetermined lower bound.
Above-mentioned m and n are predefined cycle indexes, select according to requirement and test duration to reliability, and for example m=n=10 also can be other natural number.Usually reliability requirement is higher high more, and the value of m, n is big more; Test duration is long more, and the value of m, n is big more.
Automatically adjust among second embodiment of method of test data output sampled point in the present invention, only use instruction scan to judge whether sampled point is reliable.Similar to the above embodiments, in the present embodiment, after obtaining the total command link length of boundary scan link, carry out instruction scan, and judge whether current sampling point is reliable.If current sampling point is reliable, promptly the data of each test data output interface output and the data consistent that the test data input interface is imported in m instruction scan are then reported successfully; Otherwise make the current sampling point delay scheduled time successively, and use the sampled point behind the delay scheduled time to carry out instruction scan, be lower than lower limit up to reducing the post-sampling point, the report failure.
Automatically adjust among the 3rd embodiment of method of test data output sampled point in the present invention, only use data scanning to judge whether sampled point is reliable.Similar to the above embodiments, in the present embodiment, obtaining the laggard line data scanning of total boundary scan cell length, and judging whether current sampling point is reliable.If current sampling point is reliable, promptly the data consistent of the data of each test data output interface output and the input of test data input interface in the scanning of n secondary data is then reported successfully; Otherwise make the current sampling point delay scheduled time successively, and use the sampled point behind the delay scheduled time to carry out data scanning, up to the lower limit that is lower than of delay scheduled time post-sampling point, the report failure.
Instruction scan in the foregoing description and data scanning are that all support the operation that the chip of boundary scan is all supported, therefore has versatility, realize automatic adjustment test data output sampled point, thereby improved testing efficiency, and reduced the human input in the test process.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (8)
1, a kind of device of automatic adjustment test data output port data sampled point is characterized in that, includes:
Scanning element is used for the use test data scan chain circuit is scanned, and judges according to scanning result whether sampled point is reliable, and successful information is tested in output when sampled point is reliable;
Adjustment unit is used to be provided with the initial sampled point of scanning element, and makes set sampled point delay scheduled time when scanning element determines that sampled point is unreliable;
First judging unit, whether the sampled point time value that is used to judge described adjustment unit setting is lower than predetermined lower limit and when determining that the sampled point time value is not less than predetermined lower limit the sampled point of described setting is sent to scanning element, and the sampled point time value after determining delay scheduled time is lower than under the predetermined sampled point in limited time the information of output test crash.
2, the device of automatic adjustment test data output port data sampled point according to claim 1 is characterized in that described scanning element comprises
First command unit is used for the scan instruction chain of registers;
Second judging unit is used for judging according to the output data of test data output port whether current sampling point is reliable, and make the current sampling point delay scheduled time by adjustment unit when definite current sampling point being unreliable under the sampled point that adjustment unit is provided with;
The 3rd judging unit, be used to judge whether the number of times that first command unit scans reaches pre-determined number under current sampling point, and when reaching pre-determined number output test successful information, when reaching pre-determined number, whether reliably do not continue at the current sampling point current sampling point that judges by second judging unit.
3, the device of automatic adjustment test data output port data sampled point according to claim 1 is characterized in that described scanning element comprises
First data cell is used to carry out the scanning of boundary scan link;
The 4th judging unit is used for judging according to the scanning result of described first data cell whether current sampling point is reliable under the sampled point that adjustment unit is provided with, and makes the current sampling point delay scheduled time by adjustment unit when definite current sampling point is unreliable;
The 5th judging unit, be used to judge whether the number of times that first data cell scans reaches pre-determined number under current sampling point, and when reaching pre-determined number output test successful information, when reaching pre-determined number, whether reliably do not continue at the current sampling point current sampling point that judges by the 4th judging unit.
4, the device of automatic adjustment test data output port data sampled point according to claim 1 is characterized in that described scanning element comprises
Second command unit is used for the scan instruction chain of registers;
The 6th judging unit is used for judging according to the output data of test data output port whether current sampling point is reliable, and make the current sampling point delay scheduled time by adjustment unit when definite current sampling point being unreliable under the sampled point that adjustment unit is provided with;
Whether the 7th judging unit is used to judge whether the number of times that second command unit scans reaches pre-determined number under current sampling point, and continue at the current sampling point current sampling point that judges reliable by the 6th judging unit when not reaching pre-determined number;
Second data cell is used for scanning boundary scanning element link when the 7th judging unit determines that instruction scan reaches pre-determined number;
The 8th judging unit, be used under the sampled point when the 7th judging unit determines that instruction scan reaches pre-determined number, judge according to the output data of test data output port whether current sampling point is reliable, and when definite current sampling point is unreliable, make the current sampling point delay scheduled time by adjustment unit;
The 9th judging unit, be used to judge whether the number of times that second data cell scans reaches pre-determined number under current sampling point, and when reaching pre-determined number output test successful information, when reaching pre-determined number, whether reliably do not continue at the current sampling point current sampling point that judges by the 8th judging unit.
5, according to the device of each described automatic adjustment test data output port data sampled point among the claim 1-4, it is characterized in that described scanning element includes coupling arrangement, described coupling arrangement is connected to the test access interface on the scan chain circuit.
6, a kind of method of automatic adjustment test data output port data sampled point is characterized in that, may further comprise the steps:
(a) sampled point is set to test data output synchronous sampling point;
(b) to tested link input test data, carry out test operation and whether reliable at the current sampling point current sampling point that judges, if current sampling point is reliable, execution in step (c) then; If current sampling point is unreliable, then execution in step (d);
(c) output test success message;
(d) make the current sampling point delay scheduled time, and judge whether the current sampling point behind the delay scheduled time is lower than predetermined lower limit, if current sampling point is lower than then execution in step (e) of lower limit; If current sampling point is not less than lower limit, execution in step (b);
(e) output test crash message.
7, the method for automatic adjustment test data output port data sampled point according to claim 6 is characterized in that, described step (b) comprises step:
(b11) test data is imported from the output data input interface, exported from the test data output interface through the order register link;
(b12) whether consistent in the current sampling point described output data that judges with described input data, if output data is inconsistent with the input data, determine that then current sampling point is unreliable, execution in step (d); Otherwise execution in step (b13);
(b13) judge whether the number of times that scans under the current sampling point reaches pre-determined number,, determine that then current sampling point is reliable, execution in step (c) if the scanning times under the current sampling point reaches pre-determined number; Otherwise execution in step (b11).
8, the method for automatic adjustment test data output port data sampled point according to claim 6 is characterized in that, described step (b) comprises step:
(b21) test data is imported from the test data input interface, exported from the test data output interface through the boundary scan cell link;
(b22) whether consistent in the current sampling point described output data that judges with described input data, if output data is inconsistent with the input data, determine that then current sampling point is unreliable, execution in step (d); Otherwise execution in step (b23); Otherwise execution in step (b23);
(b23) judge whether the number of times that scans under the current sampling point reaches pre-determined number,, determine that then current sampling point is reliable, execution in step (c) if reach pre-determined number at the scanning times of current sampling point; Otherwise execution in step (b21).
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103163451A (en) * | 2013-03-06 | 2013-06-19 | 中国人民解放军国防科学技术大学 | Super computing system oriented self-gating boundary scan test method and device |
| CN105102996A (en) * | 2013-04-12 | 2015-11-25 | 爱德万测试公司 | Scan speed optimization of input and output paths |
| CN105408873A (en) * | 2013-05-02 | 2016-03-16 | 微软技术许可有限责任公司 | Activity based sampling of diagnostics data |
| CN108228878A (en) * | 2018-01-23 | 2018-06-29 | 北京华睿集成科技有限公司 | The data managing method and its module of Distributed Measurement System |
| CN110928765A (en) * | 2019-10-11 | 2020-03-27 | 京东数字科技控股有限公司 | Link testing method and device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2299943A1 (en) * | 2000-03-03 | 2001-09-03 | Shane M. Rogers | Apparatus for adjusting a local sampling rate based on the rate of reception of packets |
| US7325175B2 (en) * | 2005-05-04 | 2008-01-29 | Broadcom Corporation | Phase adjust using relative error |
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2006
- 2006-11-24 CN CNB2006101238845A patent/CN100426252C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103163451A (en) * | 2013-03-06 | 2013-06-19 | 中国人民解放军国防科学技术大学 | Super computing system oriented self-gating boundary scan test method and device |
| CN105102996A (en) * | 2013-04-12 | 2015-11-25 | 爱德万测试公司 | Scan speed optimization of input and output paths |
| CN105102996B (en) * | 2013-04-12 | 2018-01-02 | 爱德万测试公司 | The sweep speed of input and outgoing route optimizes |
| CN105408873A (en) * | 2013-05-02 | 2016-03-16 | 微软技术许可有限责任公司 | Activity based sampling of diagnostics data |
| CN105408873B (en) * | 2013-05-02 | 2018-02-13 | 微软技术许可有限责任公司 | System and method for the sampling based on activity of diagnostic data |
| CN108228878A (en) * | 2018-01-23 | 2018-06-29 | 北京华睿集成科技有限公司 | The data managing method and its module of Distributed Measurement System |
| CN108228878B (en) * | 2018-01-23 | 2020-08-11 | 北京华睿集成科技有限公司 | Data management method and module of distributed measurement system |
| CN110928765A (en) * | 2019-10-11 | 2020-03-27 | 京东数字科技控股有限公司 | Link testing method and device |
| CN110928765B (en) * | 2019-10-11 | 2021-08-03 | 京东数字科技控股有限公司 | Link testing method and device |
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