CN112597723B

CN112597723B - Testability design method for FPGA embedded IP

Info

Publication number: CN112597723B
Application number: CN202110023275.7A
Authority: CN
Inventors: 季顺南; 张勇; 王俊; 温长清
Original assignee: Shenzhen Pango Microsystems Co Ltd
Current assignee: Shenzhen Pango Microsystems Co Ltd
Priority date: 2021-01-08
Filing date: 2021-01-08
Publication date: 2022-09-30
Anticipated expiration: 2041-01-08
Also published as: CN112597723A

Abstract

The invention provides a design method for testability of an IP embedded in an FPGA, which comprises the following steps: receiving a design file and a synthesis library, and carrying out logic synthesis to generate a synthesized netlist; receiving the synthesized netlist, inserting the synthesized netlist into a first register chain and generating a netlist after inserting the chain; receiving and modifying the netlist after the chain insertion, inserting a second register chain and generating a modified netlist; and receiving the modified netlist, generating a test vector and completing simulation. The design method of testability of the invention, it is through inserting the second register chain, in order to change the input excitation of the embedded IP, thus make the defect in the embedded IP detectable through DFT use case; and on the premise of avoiding great modification to the circuit structure of the embedded IP, the DFT test coverage rate of the embedded IP can be obviously improved.

Description

Testability design method for FPGA embedded IP

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of integrated circuit chips, in particular to a testability design method for an IP embedded in an FPGA.

[ background ] A method for producing a semiconductor device

Design for testability (DFT) is a key link of large-scale digital IC Design, and a sample wafer with process defects can be quickly screened out through DFT test vectors before a specific function test is carried out on the sample wafer, so that the test efficiency of the sample wafer is greatly improved. The coverage rate of the test vector reflects the probability that the DFT design can detect the sample wafer defects, namely the higher the coverage rate is, the more comprehensive the sample wafer inspection is, and the smaller the possibility of missing the defective sample wafer is.

Different from the design of an ASIC, the design of the FPGA not only comprises a programmable logic part designed by a customized circuit, but also comprises an embedded special IP part which is designed by independently completing automatic processes such as logic synthesis, layout and wiring and the like through a standard process library, such as a PCIE controller, a DDR controller and the like. Therefore, the DFT design of the whole chip cannot be automatically completed by an EDA tool like a common ASIC, but the DFT design is independently performed on each embedded dedicated IP, and then the DFT design and the programmable logic are integrated together to form a complete FPGA chip. Based on the above factors, the DFT coverage of FPGA design is easy to control unlike ASIC, which requires human intervention to improve the DFT coverage by modifying the circuit structure.

In the prior art, after entering the IP, configuration points or control information of the IP is sampled through a register after passing through a series of combinational logic, and the partial combinational logic cannot realize the coverage of the DFT test by inserting a register chain (the sampled register), thereby reducing the DFT coverage of the IP.

[ summary of the invention ]

The invention aims to provide a testability design method for an embedded IP of an FPGA (field programmable gate array) so as to improve the test coverage rate.

In order to achieve the purpose, the invention provides a design method for testability of an embedded IP of an FPGA, which comprises the following steps:

receiving a design file and a synthesis library, and carrying out logic synthesis to generate a synthesized netlist;

receiving the synthesized netlist, inserting a first register chain and generating a netlist after chain insertion;

receiving and modifying the netlist after the chain insertion, inserting a second register chain and generating a modified netlist;

and receiving the modified netlist, generating a test vector and completing simulation.

Preferably, the receiving the design file and the synthesis library, and before the performing logic synthesis to generate the synthesized netlist, further includes outputting an embedded IP including combinatorial logic for generating an operation result.

Preferably, the first register chain is located on an output side of the combinational logic.

Preferably, the second register chain is located on the input side of the combinational logic.

Preferably, the inserting the first register chain and generating the netlist after inserting the chain are inserting the first register chain and generating the netlist after inserting the chain through an EDA tool.

Preferably, the generating of the test vector and the completing of the simulation are that the test vector is generated by an EDA tool and the simulation is completed.

The invention has the beneficial effects that: a design for testability approach is provided that changes the input stimulus of an embedded IP by inserting a second chain of registers so that defects within the embedded IP can be detected by DFT use cases; and on the premise of avoiding great modification to the circuit structure of the embedded IP, the DFT test coverage rate of the embedded IP can be obviously improved.

[ description of the drawings ]

FIG. 1 is a flowchart illustrating a design for testability method according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a design for testability method according to an embodiment of the present invention;

FIG. 3 is a circuit structure for a design for testability method according to an embodiment of the present invention.

[ detailed description ] A

In order to make the objects, technical solutions and advantages of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below with reference to the specific embodiments of the present disclosure and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present specification without making any creative effort belong to the protection scope of the present specification. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

The terms "first," "second," and "third," etc. in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

As shown in fig. 1, an embodiment of the present invention provides a design-for-testability method for an embedded IP of an FPGA (Field-Programmable Gate Array), where the design-for-testability method includes:

s10, receiving the design file and the synthesis library, and carrying out logic synthesis to generate a synthesized netlist;

s20, receiving the synthesized netlist, inserting a first register chain and generating a netlist after inserting the chain;

s30, receiving and modifying the netlist after chain insertion, inserting a second register chain and generating a modified netlist;

and S40, receiving the modified netlist, generating a test vector and completing simulation.

According to the design method for testability, the second register chain is inserted to change the input excitation of the embedded IP, so that the defects in the embedded IP can be detected through a DFT case; and on the premise of avoiding great modification to the circuit structure of the embedded IP, the DFT test coverage rate of the embedded IP can be obviously improved.

Preferably, the first inserted register chain is located on the output side of the combinational logic.

Preferably, the second inserted register chain is located on the input side of the combinational logic.

In order not to affect the input in the IP normal function mode, the DFT mode and the normal mode are isolated by a 2-to-1 selector, i.e. each register in the second inserted register chain is connected to the combinational logic through a selector.

In one embodiment, in step S20, the step of inserting the first register chain and generating the inserted netlist is to insert the first register chain and generate the inserted netlist by an EDA tool (DFT Compiler of Synopsys).

S20, receiving the synthesized netlist, inserting a first register chain through an EDA tool and generating a netlist after chain insertion; and receiving the synthesized netlist, replacing a register in the synthesized netlist by an EDA tool and inserting the register into a first register chain. Specifically, a first constraint file is set according to the number of registers in the synthesized netlist, the first constraint file is used for configuring the number of register chains and specific information of each register chain, and the specific information includes the number of registers contained in each register chain, input ports and output ports of the register chains and the like, so that the EDA tool is enabled to complete the insertion of the register chains.

The design method for testability of the invention has the advantages that the number of the registers is certain, the chain inserting process of DFT is to divide the registers with certain number into a plurality of groups, and each group is connected in series to form a chain, thereby completing the design for testability. From the above, the EDA tool needs to know how the registers in the design are grouped, which registers are grouped into one group, and the number of registers included in each group.

In one embodiment, the generating test vectors and completing the simulation in step S40 is generating test vectors and completing the simulation by an EDA tool (TetraMAX, Synopsys, inc.).

And S40, receiving the modified netlist, generating a test vector according to the second constraint file through an EDA tool, and completing simulation. The contents of the second constraint file are substantially identical to the first constraint file, and include the number of configuration register chains, and specific information for each register chain. And after the simulation is passed, the test vector is used for the final chip DFT test.

The test vector is an excitation signal for testing.

According to the testability design method, the EDA tool is inserted into the first register chain to generate a netlist after chain insertion, namely, the existing register in the IP is replaced and inserted into the first register chain, and the netlist with the register chain (after chain insertion) is output; after that, a second register chain is inserted through the modified netlist, wherein each register in the second register chain is used for driving 1 input signal in the IP directly to the combinational logic, and in the DFT mode, the input of the combinational logic is driven to generate different combinations by inputting different values to the second register chain, thereby realizing the coverage of the combinational logic DFT test.

In one embodiment, as shown in fig. 2, the design for testability method includes:

s100, outputting an embedded IP (used for a pre-designed circuit function module in an ASIC or an FPGA) comprising combinational logic for generating an operation result; specifically, through architectural design, coding and functional simulation, an embedded IP including combinatorial logic for generating an operation result is output.

S200, receiving a design file and a synthesis library, and carrying out logic synthesis to generate a synthesized netlist; the design file is HDL code, namely receiving HDL code and a synthesis library, and converting the HDL code and the synthesis library into a synthesized netlist through logic synthesis. The synthesized netlist is the DFT basis.

S300, receiving the synthesized netlist, inserting a first register chain and generating a netlist after inserting the chain; and receiving the synthesized netlist, replacing a register in the synthesized netlist and inserting the register into a first register chain. Specifically, a first constraint file is set according to the number of registers in the synthesized netlist, and the first constraint file is used for configuring the number of register chains.

S400, receiving and modifying the netlist after the chain insertion, inserting a second register chain and generating a modified netlist; and modifying the netlist after the chain insertion to modify the combinational logic gate of the embedded IP, inserting a second register chain and generating a modified netlist, so that an input signal directly connected to the combinational logic in the IP is driven by a certain register in the second register chain, and a node in the combinational logic has testability.

And S500, receiving the modified netlist, generating a test vector and completing simulation. Specifically, the modified netlist is received, a test vector is generated according to a second constraint file, and simulation is completed.

In one embodiment, in step S300, the inserting the first register chain and generating the inserted netlist is by EDA tool (DFT Compiler of Synopsys) inserting the first register chain and generating the inserted netlist.

S300, receiving the synthesized netlist, inserting a first register chain through an EDA tool and generating a netlist after inserting the chain; and receiving the synthesized netlist, replacing a register in the synthesized netlist by an EDA tool and inserting the register into a first register chain. Specifically, a first constraint file is set according to the number of registers in the synthesized netlist, and the first constraint file is used for configuring the number of register chains.

In one embodiment, the generating test vectors and completing the simulation in step S500 is generating test vectors and completing the simulation by EDA tool (TetraMAX of Synopsys, inc.).

And S500, receiving the modified netlist, generating a test vector according to the second constraint file through an EDA tool, and completing simulation. And after the simulation is passed, the test vector is used for the DFT test of the final sample wafer.

The test vector is an excitation signal for testing.

According to the testability design method, the EDA tool is inserted into the first register chain to generate the netlist after chain insertion, namely, the existing register in the IP is replaced and inserted into the first register chain, and the netlist with the register chain (after chain insertion) is output; after that, a second register chain is inserted through the modified netlist, wherein each register in the second register chain is used for driving 1 input signal in the IP directly to the combinational logic, and in the DFT mode, the input of the combinational logic is driven to generate different combinations by inputting different values to the second register chain, thereby realizing the coverage of the combinational logic DFT test.

As shown in fig. 3, the circuit structure of the testability design method according to the present invention includes an embedded IP and an interconnection line resource or parameter configuration RAM connected to the embedded IP. The embedded IP comprises combinational logic, a first register chain at an output side of the combinational logic, a second register chain at an input side of the combinational logic, and a selector set between the combinational logic and the second register chain.

The selector group consists of several selectors S.

The first register chain consists of a number of registers D.

The second register chain is composed of a plurality of registers T, specifically, an output end of a previous register T and an input end of a next register T in the second register chain are connected to an input end of a corresponding selector S, an input end of the first register T receives an input signal scan _ in, an output end of the last register T outputs a scan output signal scan _ out, the other input end of the selector S in the selector group is connected to an interconnection line resource or parameter configuration RAM, and a control end of the selector S in the selector group receives a mode control signal test _ mode.

The selectors S in the selector group are configured to the DFT mode and the normal mode by the mode control signal test _ mode signal and are isolated.

When the mode control signal test _ mode is 1, indicating that the chip is operating in DFT mode, the inputs to the combinational logic are independent of the inputs to normal mode (from interconnect resources or parameter configuration RAM) and dependent on the values of the registers in the second register chain. When the EDA tool is used for generating a test case, the EDA tool is connected into different vectors in series through the input signal scan _ in according to the second register chain, so that the combinational logic is driven to generate different operation results, and the originally untestable points in the combinational logic become the testable points.

When the mode control signal test _ mode is 0, the chip works in a common mode, and the input of the combinational logic comes from the interconnection line resource or the parameter configuration RAM.

The design method for testability inserts the second register chain, so that most of the nodes which cannot be tested in the combinational logic originally can be changed into testable nodes under the driving of the second register chain, thereby greatly improving the DFT coverage rate of IP and further improving the efficiency of sample screening.

While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.

Claims

1. A design method for testability of an IP embedded in an FPGA is characterized by comprising the following steps:

outputting an embedded IP including combinatorial logic for generating an operation result;

receiving the synthesized netlist, setting a first constraint file according to the number of registers in the synthesized netlist, inserting a first register chain and generating a netlist after inserting the chain, wherein the first register chain is positioned on the output side of the combinational logic;

receiving and modifying the netlist after the chain insertion, inserting a second register chain and generating a modified netlist, wherein the second register chain is positioned on the input side of the combinational logic;

receiving the modified netlist, generating a test vector according to a second constraint file, and completing simulation; the first constraint file and the second constraint file respectively comprise the number of the configuration register chains and specific information of each register chain.

2. The method for design for testability according to claim 1, wherein the inserting the first register chain and generating the post-insertion netlist is by an EDA tool.

3. The method of claim 1, wherein the generating test vectors and performing simulation comprises generating test vectors and performing simulation using an EDA tool.