CN102081689B - Method for designing testability of chip - Google Patents
Method for designing testability of chip Download PDFInfo
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- CN102081689B CN102081689B CN 201010620100 CN201010620100A CN102081689B CN 102081689 B CN102081689 B CN 102081689B CN 201010620100 CN201010620100 CN 201010620100 CN 201010620100 A CN201010620100 A CN 201010620100A CN 102081689 B CN102081689 B CN 102081689B
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Abstract
The invention relates to a method for designing testability of a chip, which comprises the steps: (1) insertion of a built-in self test circuit of a memory; (2) insertion of a boundary scan circuit; (3) integration of a testability circuit; (4) insertion of a scan chain circuit; and (5) generation of automatic test generated vectors. In order to solve the technical problems that in the traditional chip design process, a set of complete and systematical method in test methods aiming at different test objects is not available, tools such as a DFT (diagnostic function test) tool, a logic synthesis tool, a circuit simulation tool and the like are not joined and the design program is complicated, the invention provides the process guarantee for automation of the DFT design and complete and systematical correctness of the DFT design.
Description
Technical field
The present invention relates to a kind of method for designing of chip, relate in particular to the method for a kind of DFT of being used for insertion, logic synthesis, emulation and static timing analysis.
Background technology
Testability Design DFT (Design For Testability) is exactly controllability and an observability of attempting to increase signal in the circuit, so as in time economically test chip whether have physical imperfection, make the user take good chip.Do you why to be DFT? Because in the design process of chip; Just domain of handing over to GDSII of register transfer level RTL just; Last chip need be manufactured in factory and do, and just chip is made according to the data GDSII that you provide by producer.Defective possibly occur in this flowchart process, this defective possibly be that physics exists, and also possibly be that the leftover problem in the middle of the design causes, and also defective possibly occur in the process that encapsulates on the one hand in addition.For can there be defective physically in the chip that guarantees us, so will be Testability Design DFT.It is thus clear that in present IC design and the production, Testability Design DFT is an important means of chip production test.Testability Design DFT mainly comprises the contents such as insertion, the insertion of register scan chain and test vector production of memory built in self test of sram circuit MBIST, boundary scan chain.
But in existing design, the insertion of DFT, logic synthesis and emulation etc. do not have the complete method for designing of a cover, between instruments such as DFT instrument, logic synthesis tool, circuit simulation, can't well be connected.
Summary of the invention
There is not the method for a cover holonomic system in order to solve the method for testing that is directed against different tested objects in the existing chip design process; Instruments such as DFT instrument, logic synthesis tool, circuit simulation can't be realized being connected; The complicated technology of designing program problem; The present invention provides a kind of DFT method for designing of chip, and the present invention is for the robotization that improves the DFT design and guarantee that comprehensive system correctness of DFT design provides the flow process guarantee.
Technical solution of the present invention:
A kind of design method of testability of chip, its special character may further comprise the steps:
1] insertion of memory built in self test of sram circuit:
1.1] the gate level netlist file of the comprehensive one-tenth of RTL code based on technology library;
1.2] the insertion strategy of define storage built-in self-test circuit MBIST and the memory bank file that memory built in self test of sram circuit MBIST insertion needs, said insertion strategy comprises insertion algorithm and the pin multiplexing strategy of memory built in self test of sram circuit MBIST;
1.3] adopt the memory built in self test of sram of DFT instrument to insert instrument and based on the insertion strategy of memory built in self test of sram circuit MBIST memory built in self test of sram circuit MBIST is inserted the gate level netlist file; Output storage built-in self-test net meter file and memory built in self test of sram vector, said memory built in self test of sram vector comprise the setting value of memory built in self test of sram circuit and through the memory built in self test of sram circuit memory is tested after test value;
1.4] with step 1.3] middle memory built in self test of sram net meter file of exporting and memory built in self test of sram vector structure test environment; Adopt emulation tool to carry out the emulation first time; When test value and setting value are inconsistent; Then execution in step 1.2], when test value is consistent with setting value, then carry out following steps;
2] insertion of boundary scan chain:
2.1] with step 1.3] and in the design top document of reservoir built-in self-test net meter file of output as the insertion object of boundary scan chain; The insertion strategy of definition boundary scan chain, the insertion strategy of said boundary scan chain is the order of the pin of boundary scan chain;
2.2] adopt the boundary scan of DFT instrument to insert instrument and based on the insertion strategy of boundary scan chain boundary scan chain is inserted the insertion object of boundary scan chain; Output RTL code net meter file and boundary scan chain test vector, said boundary scan chain test vector comprises the setting value of boundary scan chain and the test value of chip pin being tested through boundary scan chain;
2.3] with step 2.2] middle RTL code net meter file of exporting and boundary scan chain test vector structure simulated environment; Adopt emulation tool to carry out the emulation second time, when test value and setting value were inconsistent, then execution in step 2.1], when test value is consistent with setting value, then carry out following steps;
3] testability circuit synthesis:
3.1] adopt the logic synthesis tool of DFT instrument to carry out RTL code net meter file comprehensively, output boundary scanning net meter file;
3.2] utilize step 3.1] and in boundary scan net meter file and the step 2.2 of output] the boundary scan chain test vector structure simulated environment of output; Adopt emulation tool to carry out emulation for the third time; When test value and setting value do not wait; Then execution in step 3.1], when test value is consistent with setting value, then carry out following steps;
4] insertion of scan chain circuits:
4.1] the insertion strategy of definition scan chain circuits and the running environment of supporting to insert strategy; The insertion strategy of said scan chain circuits comprises the length of number and every scan chain of scan chain, and said running environment comprises experimentation file (Test Procedure) and DFT library file;
4.2] adopt the scan chain circuits of DFT instrument insert instrument and according to step 4.1] in defined insertions strategy scan chain circuits is inserted the boundary scan net meter file, output scanning chain net meter file and testing scanning chain are vectorial; Said testing scanning chain vector comprise the setting value of scan chain circuits and through scan chain circuits register is tested after test value;
4.3] utilize scan chain net meter file and testing scanning chain vector to make up simulated environment, adopt emulation tool to carry out the 4th emulation, when test value and setting value were inconsistent, then execution in step 4.1], when test value is consistent with setting value, then carry out step;
5] generation of the vectorial atpg of test generation automatically:
5.1] the automatic generation strategy that generates library file and test the generation vector automatically of testing of definition, said automatic test generation vector generation strategy comprises file output format, clock frequency and test pin distribution;
5.2] adopt the automatic test of DFT instrument to generate vectorial instrument according to step 5.1] defined vector produces strategy and produce automatically that test generates vector, said automatic test generates vector and comprises that automatic test generates the setting value of vector and generates the test value that vector is tested gate level circuit through automatic test;
5.3] scan chain net meter file and the vectorial simulated environment that makes up of automatic test generation; Adopt emulation tool to carry out the 5th emulation, when test value and setting value did not wait, then execution in step 5.1]; When test value was consistent with setting value, then the vectorial atpg of test generation was for use automatically in reservation.
Above-mentioned steps 3] also comprise step 3.3] static timing analysis:
3.3.1] definition static timing analysis script, the script of said static timing analysis comprises the setting value of boundary scan chain and the test value of chip pin being tested through boundary scan chain;
3.3.2] static timing analysis, when test value and setting value were inconsistent, then execution in step 3.1], when test value is consistent with setting value, then carry out following steps.
Above-mentioned steps 4] also comprise step 4.4] static timing analysis:
4.4.1] script of definition static timing analysis, the script of said static timing analysis comprise the setting value of scan chain circuits and through scan chain circuits register is tested after test value;
4.4.2] static timing analysis, when test value and setting value were inconsistent, then execution in step 4.1], when test value is consistent with setting value, then carry out following steps.
Above-mentioned steps 5] also comprise step 5.4] static timing analysis:
5.4.1] script of definition static timing analysis, the script of said static timing analysis comprises that automatic test generates the setting value of vector and generates the test value that vector is tested gate level circuit through automatic test;
5.4.2] static timing analysis, when test value and setting value when inconsistent, then execution in step 5.1], when test value is consistent with setting value, keep then that should to test generation ATPG vector automatically for use.
Above-mentioned steps 5] also comprise step 5.4] static timing analysis:
5.4.1] script of definition static timing analysis, the script of said static timing analysis comprises that automatic test generates the setting value of vector and generates the test value that vector is tested gate level circuit through automatic test;
5.4.2] static timing analysis, when test value and setting value when inconsistent, then execution in step 5.1], when test value is consistent with setting value, keep then that should to test generation ATPG vector automatically for use.
Above-mentioned steps 1.3] the realization script be:
mbistarchitect./netlist/mydesign_fix_timing.v-verilog\
-top?mydesign_top\
-lverilog./libs/*.v\
-logfile?mbist.log-replace\
-dofile./scripts/mbist.do\
-nogui\
-insertion
Be to use gate level netlist file (Verilog) and memory bank file (atpg) in the design under the libs file in the said script, mbist.do is the insertion strategy of memory built in self test of sram circuit.
Above-mentioned steps 4.2] the realization script be:
fastscan?mydesign_dft.v-verilog\
-dofile?scan_fs.dofile\
-lib?smic18m.atpg\
-log?fastscan.log-replace\
-nogui
Above-mentioned steps 5.2] the realization script be:
dftadvisor?mydesign_pst_timing.v-verilog\
-top?mydesign_top\
-lib?smic18m.atpg\
-log?dfta.log-replace\
-nogui\
-dofile?scan_dfta.dofile
It is above-mentioned that comprehensive to become gate level netlist file based on technology library be the RTL Compiler tool implementation that adopts DC synthesis tool or the Cadence company of Synopsys company the RTL code.
The advantage that the present invention had:
The present invention is a kind of whole flow process that is used for Testability Design (DFT) process; Can between instruments such as DFT instrument, logic synthesis tool, circuit simulation, static timing analysis tool, realize seamless connection; Thereby the complete method of a kind of DFT insertion, logic synthesis, emulation and static timing analysis is provided, the final automaticity that improves design.
Description of drawings
Fig. 1 is a schematic flow sheet of the present invention;
Fig. 2 is an another kind of schematic flow sheet of the present invention;
Fig. 3 is the embodiments of the invention synoptic diagram.
Embodiment
A kind of design method of testability of chip may further comprise the steps:
1] insertion of memory built in self test of sram circuit:
1.1] the gate level netlist file of the comprehensive one-tenth of RTL code based on technology library;
Adopt the DC synthesis tool of Synopsys company or the RTL Compiler instrument of Cadence company.
1.2] the insertion strategy of define storage built-in self-test circuit MBIST and the memory bank file that memory built in self test of sram circuit MBIST insertion needs, said insertion strategy comprises insertion algorithm and the pin multiplexing strategy of memory built in self test of sram circuit MBIST;
1.3] adopt the memory built in self test of sram of DFT instrument to insert instrument and based on the insertion strategy of memory built in self test of sram circuit MBIST memory built in self test of sram circuit MBIST is inserted the gate level netlist file; Output storage built-in self-test net meter file and memory built in self test of sram vector, said memory built in self test of sram vector comprise the setting value of memory built in self test of sram circuit and through the memory built in self test of sram circuit memory is tested after test value;
1.4] with step 1.3] middle memory built in self test of sram net meter file of exporting and memory built in self test of sram vector structure test environment; Adopt emulation tool to carry out the emulation first time; When test value and setting value are inconsistent; Then execution in step 1.2], when test value is consistent with setting value, then carry out following steps;
2] insertion of boundary scan chain:
2.1] with step 1.3] and in the design top document of reservoir built-in self-test net meter file of output as the insertion object of boundary scan chain; The insertion strategy of definition boundary scan chain, the insertion strategy of said boundary scan chain is the order of the pin of boundary scan chain;
2.2] adopt the boundary scan of DFT instrument to insert instrument and based on the insertion strategy of boundary scan chain boundary scan chain is inserted the insertion object of boundary scan chain; Output RTL code net meter file and boundary scan chain test vector, said boundary scan chain test vector comprises the setting value of boundary scan chain and the test value of chip pin being tested through boundary scan chain;
2.3] with step 2.2] middle RTL code net meter file of exporting and boundary scan chain test vector structure simulated environment; Adopt emulation tool to carry out the emulation second time, when test value and setting value were inconsistent, then execution in step 2.1], when test value is consistent with setting value, then carry out following steps;
3] testability circuit synthesis:
3.1] adopt the logic synthesis tool of DFT instrument to carry out RTL code net meter file comprehensively, output boundary scanning net meter file;
3.2] utilize step 3.1] and in boundary scan net meter file and the step 2.2 of output] the boundary scan chain test vector structure simulated environment of output; Adopt emulation tool to carry out emulation for the third time; When test value and setting value do not wait; Then execution in step 3.1], when test value is consistent with setting value, then carry out following steps;
3.3] static timing analysis:
3.3.1] definition static timing analysis script, the script of said static timing analysis comprises the setting value of boundary scan chain and the test value of chip pin being tested through boundary scan chain;
3.3.2] static timing analysis, when test value and setting value were inconsistent, then execution in step 3.1], when test value is consistent with setting value, then carry out following steps.
4] insertion of scan chain circuits:
4.1] the insertion strategy of definition scan chain circuits and the running environment of supporting to insert strategy; The insertion strategy of said scan chain circuits comprises the length of number and every scan chain of scan chain, and said running environment comprises experimentation file (Test Procedure) and DFT library file;
4.2] adopt the scan chain circuits of DFT instrument insert instrument and according to step 4.1] in defined insertions strategy scan chain circuits is inserted the boundary scan net meter file, output scanning chain net meter file and testing scanning chain are vectorial; Said testing scanning chain vector comprise the setting value of scan chain circuits and through scan chain circuits register is tested after test value;
4.3] utilize scan chain net meter file and testing scanning chain vector to make up simulated environment, adopt emulation tool to carry out the 4th emulation, when test value and setting value were inconsistent, then execution in step 4.1], when test value is consistent with setting value, then carry out step;
4.4] static timing analysis:
4.4.1] script of definition static timing analysis, the script of said static timing analysis comprise the setting value of scan chain circuits and through scan chain circuits register is tested after test value;
4.4.2] static timing analysis, when test value and setting value were inconsistent, then execution in step 4.1], when test value is consistent with setting value, then carry out following steps.
5] generation of the vectorial atpg of test generation automatically:
5.1] defining test generation library file and the vectorial strategy that produces automatically, the said vectorial strategy that produces comprises file output format, clock frequency and test pin distribution;
5.2] adopt the automatic test of DFT instrument to generate vectorial instrument according to step 5.1] defined vector produces strategy and produce automatically that test generates vector, said automatic test generates vector and comprises that automatic test generates the setting value of vector and generates the test value that vector is tested gate level circuit through automatic test;
5.3] scan chain net meter file and the vectorial simulated environment that makes up of automatic test generation; Adopt emulation tool to carry out the 5th emulation, when test value and setting value did not wait, then execution in step 5.1]; When test value was consistent with setting value, then test generation atpg vector was for use automatically in reservation.
5.4] static timing analysis:
5.4.1] script of definition static timing analysis, the script of said static timing analysis comprises that automatic test generates the setting value of vector and generates the test value that vector is tested gate level circuit through automatic test;
5.4.2] static timing analysis, when test value and setting value when inconsistent, then execution in step 5.1], when test value is consistent with setting value, keep then that should to test generation atpg vector automatically for use.
Above-mentioned steps 1.3] can adopt following script to realize:
mbistarchitect./netlist/mydesign_fix_timing.v-verilog\
-top?mydesign_top\
-lverilog./libs/*.v\
-logfile?mbist.log-replace\
-dofile./scripts/mbist.do\
-nogui\
-insertion
Be to use gate level netlist file (Verilog) and memory bank file (atpg) in the design under the libs file in the said script, mbist.do is the insertion strategy of memory built in self test of sram circuit.
Above-mentioned steps 4.2] can adopt following script to realize:
fastscan?mydesign_dft.v-verilog\
-dofile?scan_fs.dofile\
-lib?smic18m.atpg\
-log?fastscan.log-replace\
-nogui
Above-mentioned steps 5.2] can adopt following script to realize:
dftadvisor?mydesign_pst_timing.v-verilog\
-top?mydesign_top\
-lib?smic18m.atpg\
-log?dfta.log-replace\
-nogui\
-dofile?scan_dfta.dofile
Embodiment:
This flow process has been accomplished DFT design and a test vector production and an emulation based on typical SoC mainly based on the DFT instrument (MBISTArchitect, BSDArchitect, FastScan, DFTAdvisor) of Mentor, the DC synthesis tool of Synopsys company, the instruments such as emulation tool ModelSim of Mentor company.
(1) synthesis tool that uses company such as SynopSys is the comprehensive gate level netlist file that becomes based on technology library of RTL code.
(2) write the memory bank file that the MBISTArchitect of Mentor company needs.After this two step was finished, the preliminary work of DFT design was accomplished.
(3) use the MBISTArchitect tool memory built-in self-test circuit of Mentor company to insert the MBIST circuit.Concrete realization script is:
mbistarchitect./netlist/mydesign_fix_timing.v-verilog\
-top?mydesign_top \
-lverilog./libs/*.v\
-logfile?mbist.log-replace\
-dofile./scripts/mbist.do\
-nogui\
-insertion
Be gate level netlist file (Verilog) and the memory bank file (atpg) that uses in the design under the libs file in the above-mentioned script, mbist.do is the strategy that needs the MIBST circuit of insertion, and different design demand has different designs.
(4) use the circuit meshwork list file and the test vector that produce in the MBIST process to make up test environment.Emulation tool can use the emulation tools such as ModelSim of Mentor company.Emulation is through entering into next step.
(5) need split the note that comes respectively to the design top layer of the net meter file that produces in the middle of the MBIST process and other parts entering in the process at first of boundary scan chain and be mydesign_fix_timingg_ist_top.v and mydesign_notop.v.Split the insertion that the design top document that comes out is used for boundary scan chain.
In this process, need be ready to the order of the pin of boundary scan chain.
Based on different separately designs, adopt certain insertion strategy to carry out the insertion of boundary scan chain then.
(6) be incorporated into called after mydesign_top_bscan.v together to the design document and the original mydesign_notop.v of the boundary scan chain of the final top layer that generates in the boundary scan insertion process.Utilize the test vector file that generates to make up simulated environment, use emulation tool to carry out emulation.
(6) utilize synthesis tool to carry out mydesign_top_bscan.v comprehensively.(, needing comprehensive) so that next step uses owing in the insertion process of MBIST, boundary scan chain, produced a part of RTL code.
The comprehensive net meter file of (7) the 6th steps need carry out emulation and static timing analysis STA.Emulation and STA enter into the scan chain insertion process after analyzing and passing through.
(8) insertion process of scan chain.Prepare Test Procedure file, DFT library file and scan chain earlier and insert policy script (number that comprises scan chain, settings such as the length of every scan chain.Being provided with here can be different according to different designs.Suggestion makes that as far as possible the length of every scan chain is consistent, and not too long).The insertion script of scan chain is following:
fastscan?mydesign_dft.v-verilog\
-dofile?scan_fs.dofile\
-lib?smic18m.atpg\
-log?fastscan.log-replace\
-nogui
(9) can produce net meter file and test vector after scan chain inserts, make up simulated environment based on these files and carry out emulation.Carry out static timing analysis simultaneously.
(10) production run of ATPG vector.Prepare atpg library file and vectorial production strategy script earlier.The insertion script of scan chain is following:
dftadvisor?mydesign_pst_timing.v-verilog\
-top?mydesign_top\
-lib?smic18m.atpg\
-log?dfta.log-replace\
-nogui\
-dofile?scan_dfta.dofile
(11) after the atpg vector is produced, make up simulated environment and carry out gate level circuit emulation.Carry out static timing analysis STA simultaneously.
(12) after domain is produced, carry out the domain post-simulation based on structure simulated environment such as the test file after the production of atpg vector, domain sdf files.Carry out static timing analysis simultaneously.Through representing that then whole DFT process finishes.
Claims (6)
1. the design method of testability of a chip is characterized in that: may further comprise the steps:
1] insertion of memory built in self test of sram circuit:
1.1] the gate level netlist file of the comprehensive one-tenth of RTL code based on technology library;
1.2] the insertion strategy of define storage built-in self-test circuit and the memory bank file that the insertion of memory built in self test of sram circuit needs, said insertion strategy comprises the insertion algorithm and the pin multiplexing strategy of memory built in self test of sram circuit;
1.3] adopt the memory built in self test of sram of Testability Design DFT instrument to insert instrument and based on the insertion strategy of memory built in self test of sram circuit the memory built in self test of sram circuit is inserted the gate level netlist file; Output storage built-in self-test net meter file and memory built in self test of sram vector, said memory built in self test of sram vector comprise the setting value of memory built in self test of sram circuit and through the memory built in self test of sram circuit memory is tested after test value;
1.4] with step 1.3] middle memory built in self test of sram net meter file of exporting and memory built in self test of sram vector structure test environment, adopt emulation tool to carry out the emulation first time;
1.5] when through the step 1.3 after the emulation for the first time] and in test value and setting value when inconsistent, then be back to step 1.2], when test value is consistent with setting value, then carry out following steps;
2] insertion of boundary scan chain:
2.1] with step 1.3] and in the design top document of memory built in self test of sram net meter file of output as the insertion object of boundary scan chain; Define the insertion strategy of boundary scan chain simultaneously, the insertion strategy of said boundary scan chain is the order of the pin of boundary scan chain;
2.2] adopt the boundary scan of Testability Design DFT instrument to insert instrument and based on the insertion strategy of boundary scan chain boundary scan chain is inserted the insertion object of boundary scan chain; Output RTL code net meter file and boundary scan chain test vector, said boundary scan chain test vector comprises the setting value of boundary scan chain and the test value of chip pin being tested through boundary scan chain;
2.3] with step 2.2] middle RTL code net meter file of exporting and boundary scan chain test vector structure simulated environment; Adopt emulation tool to carry out emulation second time, when through the step 2.2 after the emulation for the second time] when middle test value and setting value are inconsistent, then be back to step 2.1], when test value is consistent with setting value, then carry out following steps;
3] testability circuit synthesis:
3.1] adopt the logic synthesis tool of Testability Design DFT instrument to carry out RTL code net meter file comprehensively, output boundary scanning net meter file;
3.2] utilize step 3.1] and in boundary scan net meter file and the step 2.2 of output] the boundary scan chain test vector structure simulated environment of output; Adopt emulation tool to carry out emulation for the third time; When through the step 2.2 after the emulation for the third time] in test value when not waiting with setting value; Then be back to step 3.1], when test value is consistent with setting value, then carry out following steps;
4] insertion of scan chain circuits:
4.1] the insertion strategy of definition scan chain circuits and the running environment of supporting to insert strategy; The insertion strategy of said scan chain circuits comprises the length of number and every scan chain of scan chain, and said running environment comprises experimentation file and Testability Design DFT library file;
4.2] adopt the scan chain circuits of Testability Design DFT instrument insert instrument and according to step 4.1] in defined insertions strategy scan chain circuits is inserted the boundary scan net meter file, output scanning chain net meter file and testing scanning chain are vectorial; Said testing scanning chain vector comprise the setting value of scan chain circuits and through scan chain circuits register is tested after test value;
4.3] utilize scan chain net meter file and testing scanning chain vector to make up simulated environment; Adopt emulation tool to carry out the 4th emulation; When through the step 4.2 after the 4th emulation] in test value with setting value when inconsistent; Then be back to step 4.1], when test value is consistent with setting value, then carry out step;
5] test generates vectorial generation automatically:
5.1] the automatic generation strategy that generates library file and test the generation vector automatically of testing of definition, the generation strategy of said automatic test generation vector comprises file output format, clock frequency and test pin distribution;
5.2] adopt the automatic test of Testability Design DFT instrument to generate vectorial instrument according to step 5.1] defined vector produces strategy and produce automatically that test generates vector, said automatic test generates vector and comprises that automatic test generates the setting value of vector and generates the test value that vector is tested gate level circuit through automatic test;
5.3] generate the vectorial simulated environment that makes up based on the scan chain net meter file with testing automatically; Adopt emulation tool to carry out the 5th emulation; When through the step 5.2 after the 5th emulation] in test value and setting value when not waiting; Then be back to step 5.1], when test value is consistent with setting value, then keeps and should wait to stay chip testing to use by automatic test generation vector.
2. the design method of testability of chip according to claim 1 is characterized in that:
Said step 3] also comprise step 3.3] static timing analysis:
3.3.1] definition static timing analysis script, the script of said static timing analysis comprises the setting value of boundary scan chain and the test value of chip pin being tested through boundary scan chain;
3.3.2] carry out static timing analysis, when test value and setting value are inconsistent, then be back to step 3.1], when test value was consistent with setting value, then execution in step 4].
3. the design method of testability of chip according to claim 1 and 2 is characterized in that:
Said step 4] also comprise step 4.4] static timing analysis:
4.4.1] script of definition static timing analysis, the script of said static timing analysis comprise the setting value of scan chain circuits and through scan chain circuits register is tested after test value;
4.4.2] carry out static timing analysis, when test value and setting value are inconsistent, then be back to step 4.1], when test value was consistent with setting value, then execution in step 5].
4. the design method of testability of chip according to claim 3 is characterized in that:
When said step 5.3] when middle test value was consistent with setting value, this tested the step that the chip testing to be stayed of generation vector is used automatically no longer to carry out reservation, and execution in step 5.4] static timing analysis:
5.4.1] script of definition static timing analysis, the script of said static timing analysis comprises that automatic test generates the setting value of vector and generates the test value that vector is tested gate level circuit through automatic test;
5.4.2] carry out static timing analysis, when test value and setting value are inconsistent, then be back to step 5.1], when test value was consistent with setting value, then keeping test automatically, to generate vector for use.
5. the design method of testability of chip according to claim 1 and 2 is characterized in that:
When said step 5.3] when middle test value was consistent with setting value, this tested the step that the chip testing to be stayed of generation vector is used automatically no longer to carry out reservation, and execution in step 5.4] static timing analysis:
5.4.1] script of definition static timing analysis, the script of said static timing analysis comprises that automatic test generates the setting value of vector and generates the test value that vector is tested gate level circuit through automatic test;
5.4.2] carry out static timing analysis, when test value and setting value are inconsistent, then be back to step 5.1], when test value was consistent with setting value, then keeping test automatically, to generate vector for use.
6. the design method of testability of chip according to claim 4 is characterized in that:
Said step 1.1] comprehensive to become gate level netlist file based on technology library be the RTL Compiler tool implementation that adopts DC synthesis tool or the Cadence company of Synopsys company the RTL code.
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| CN108052769A (en) * | 2017-12-28 | 2018-05-18 | 天津芯海创科技有限公司 | Netlist emulation verification method and device |
| CN111381148B (en) * | 2018-12-29 | 2023-02-21 | 华润微集成电路(无锡)有限公司 | System and method for realizing chip test |
| CN112945418B (en) * | 2019-12-09 | 2023-06-30 | 圣邦微电子（北京）股份有限公司 | Temperature measuring device and temperature measuring method of integrated chip |
| CN112764987B (en) * | 2021-01-07 | 2021-12-24 | 无锡众星微系统技术有限公司 | Automatic generation method of chip monitoring signal |
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