CN102081689A - Method for designing testability of chip - Google Patents
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- CN102081689A CN102081689A CN 201010620100 CN201010620100A CN102081689A CN 102081689 A CN102081689 A CN 102081689A CN 201010620100 CN201010620100 CN 201010620100 CN 201010620100 A CN201010620100 A CN 201010620100A CN 102081689 A CN102081689 A CN 102081689A
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CN 201010620100 CN102081689B (en) | 2010-12-31 | 2010-12-31 | Method for designing testability of chip |
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Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103530479A (en) * | 2013-10-31 | 2014-01-22 | 哈尔滨工业大学 | Partial testability design system and method for electronic design interchange format (EDIF) netlist-class circuits and based on Perl |
CN103632019A (en) * | 2013-12-25 | 2014-03-12 | 哈尔滨工业大学 | Automatic realization system and method for partial testability design for Perl-based Verilog netlist circuit |
CN103699422A (en) * | 2013-12-25 | 2014-04-02 | 哈尔滨工业大学 | System and method for performing testability design on verilog netlist description of circuit through Perl |
CN104123407A (en) * | 2014-06-19 | 2014-10-29 | 电子科技大学 | Automatic testability model building method based on circuit simulation |
CN104424369A (en) * | 2013-08-28 | 2015-03-18 | 京微雅格(北京)科技有限公司 | Time sequence estimation method for FPGA (field programmable gate array) post-mapping net list |
CN105372582A (en) * | 2015-12-14 | 2016-03-02 | 浪潮(北京)电子信息产业有限公司 | Generation method and system of module-level boundary scan chains |
CN106934153A (en) * | 2017-03-13 | 2017-07-07 | 北京智芯微电子科技有限公司 | A kind of method and device of extraction device model parameter |
CN108052769A (en) * | 2017-12-28 | 2018-05-18 | 天津芯海创科技有限公司 | Netlist emulation verification method and device |
CN108957301A (en) * | 2017-05-27 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | Test method, test device and built-in chip type circuit can be tested |
CN109145334A (en) * | 2017-06-27 | 2019-01-04 | 深圳市中兴微电子技术有限公司 | A kind of method and device of chip design treatment |
CN111381148A (en) * | 2018-12-29 | 2020-07-07 | 无锡华润矽科微电子有限公司 | System and method for realizing chip test |
CN112597723A (en) * | 2021-01-08 | 2021-04-02 | 深圳市紫光同创电子有限公司 | Testability design method for FPGA embedded IP |
CN112764987A (en) * | 2021-01-07 | 2021-05-07 | 无锡众星微系统技术有限公司 | Automatic generation method of chip monitoring signal |
CN112945418A (en) * | 2019-12-09 | 2021-06-11 | 圣邦微电子(北京)股份有限公司 | Temperature measuring device and temperature measuring method of integrated chip |
CN113609804A (en) * | 2021-07-27 | 2021-11-05 | 西安芯海微电子科技有限公司 | Case generation method and device, test method and testability design method |
CN114444419A (en) * | 2022-04-11 | 2022-05-06 | 奇捷科技(深圳)有限公司 | Method and equipment for generating new version circuit of chip and storage medium |
CN114492265A (en) * | 2022-04-02 | 2022-05-13 | 奇捷科技(深圳)有限公司 | Method, equipment and storage medium for determining chip testable design |
CN115656791A (en) * | 2022-12-29 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | Test method and test platform for chip testability design |
Citations (1)
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CN101317180A (en) * | 2005-12-02 | 2008-12-03 | Nxp股份有限公司 | Method for providing an IC design and IC design tool |
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2010
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Patent Citations (1)
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CN101317180A (en) * | 2005-12-02 | 2008-12-03 | Nxp股份有限公司 | Method for providing an IC design and IC design tool |
Non-Patent Citations (3)
Title |
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《Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2009 3rd IEEE International Symposium on 》 20091029 Jinghe Wei等 Design and implement for test in a complex system on chip 120-122 , * |
《中国优秀硕士学位论文全文数据库 信息科技辑》 20101015 王君虎 高性能可测试性电路设计 I135-83 , 第10期 * |
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Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104424369A (en) * | 2013-08-28 | 2015-03-18 | 京微雅格(北京)科技有限公司 | Time sequence estimation method for FPGA (field programmable gate array) post-mapping net list |
CN104424369B (en) * | 2013-08-28 | 2017-08-25 | 京微雅格(北京)科技有限公司 | The sequential evaluation method of netlist after a kind of FPGA mappings |
CN103530479B (en) * | 2013-10-31 | 2016-09-21 | 哈尔滨工业大学 | The part design for Measurability system of EDIF netlist level circuit based on Perl and part design for Measurability method |
CN103530479A (en) * | 2013-10-31 | 2014-01-22 | 哈尔滨工业大学 | Partial testability design system and method for electronic design interchange format (EDIF) netlist-class circuits and based on Perl |
CN103632019A (en) * | 2013-12-25 | 2014-03-12 | 哈尔滨工业大学 | Automatic realization system and method for partial testability design for Perl-based Verilog netlist circuit |
CN103699422A (en) * | 2013-12-25 | 2014-04-02 | 哈尔滨工业大学 | System and method for performing testability design on verilog netlist description of circuit through Perl |
CN104123407A (en) * | 2014-06-19 | 2014-10-29 | 电子科技大学 | Automatic testability model building method based on circuit simulation |
CN104123407B (en) * | 2014-06-19 | 2017-04-05 | 电子科技大学 | A kind of testability model auto-creating method based on circuit simulation |
CN105372582B (en) * | 2015-12-14 | 2018-05-25 | 浪潮(北京)电子信息产业有限公司 | A kind of generation method and system of module level boundary scan chain |
CN105372582A (en) * | 2015-12-14 | 2016-03-02 | 浪潮(北京)电子信息产业有限公司 | Generation method and system of module-level boundary scan chains |
CN106934153A (en) * | 2017-03-13 | 2017-07-07 | 北京智芯微电子科技有限公司 | A kind of method and device of extraction device model parameter |
CN108957301A (en) * | 2017-05-27 | 2018-12-07 | 深圳市中兴微电子技术有限公司 | Test method, test device and built-in chip type circuit can be tested |
CN108957301B (en) * | 2017-05-27 | 2021-02-09 | 深圳市中兴微电子技术有限公司 | Test method and device for testable chip and built-in circuit of testable chip |
CN109145334A (en) * | 2017-06-27 | 2019-01-04 | 深圳市中兴微电子技术有限公司 | A kind of method and device of chip design treatment |
CN109145334B (en) * | 2017-06-27 | 2023-04-07 | 深圳市中兴微电子技术有限公司 | Method and device for chip design processing |
CN108052769A (en) * | 2017-12-28 | 2018-05-18 | 天津芯海创科技有限公司 | Netlist emulation verification method and device |
CN111381148A (en) * | 2018-12-29 | 2020-07-07 | 无锡华润矽科微电子有限公司 | System and method for realizing chip test |
CN111381148B (en) * | 2018-12-29 | 2023-02-21 | 华润微集成电路(无锡)有限公司 | System and method for realizing chip test |
CN112945418A (en) * | 2019-12-09 | 2021-06-11 | 圣邦微电子(北京)股份有限公司 | Temperature measuring device and temperature measuring method of integrated chip |
CN112945418B (en) * | 2019-12-09 | 2023-06-30 | 圣邦微电子(北京)股份有限公司 | Temperature measuring device and temperature measuring method of integrated chip |
CN112764987A (en) * | 2021-01-07 | 2021-05-07 | 无锡众星微系统技术有限公司 | Automatic generation method of chip monitoring signal |
CN112597723A (en) * | 2021-01-08 | 2021-04-02 | 深圳市紫光同创电子有限公司 | Testability design method for FPGA embedded IP |
CN113609804A (en) * | 2021-07-27 | 2021-11-05 | 西安芯海微电子科技有限公司 | Case generation method and device, test method and testability design method |
CN113609804B (en) * | 2021-07-27 | 2023-10-20 | 西安芯海微电子科技有限公司 | Case generation method and device, test method and testability design method |
CN114492265A (en) * | 2022-04-02 | 2022-05-13 | 奇捷科技(深圳)有限公司 | Method, equipment and storage medium for determining chip testable design |
CN114444419A (en) * | 2022-04-11 | 2022-05-06 | 奇捷科技(深圳)有限公司 | Method and equipment for generating new version circuit of chip and storage medium |
CN115656791A (en) * | 2022-12-29 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | Test method and test platform for chip testability design |
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Application publication date: 20110601 Assignee: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Assignor: 631ST Research Institute OF AVIC Contract record no.: 2014610000016 Denomination of invention: Method for designing testability of chip Granted publication date: 20121003 License type: Exclusive License Record date: 20140320 |
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Effective date of registration: 20221205 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 710068 No. 156 Taibai North Road, Shaanxi, Xi'an Patentee before: 631ST Research Institute OF AVIC |